Hybrid pin schottky diode based on p-type island and super junction structure and preparation method thereof

Abstract

The application discloses a mixed PIN Schottky diode based on a P-type island and a super-junction structure and a preparation method thereof. + a Ga2O3 substrate layer, an n ‑ Ga2O3 drift layer, and an anode, wherein the n ‑ Ga2O3 drift layer and the anode are provided with a plurality of heavily doped P-type islands; a plurality of lightly doped P-type regions are correspondingly arranged below the heavily doped P-type islands to be in contact with the n ‑ Ga2O3 drift layer to form a super-junction structure; wherein the heavily doped P-type islands and the lightly doped P-type regions are both made of gallium nitride material. The mixed PIN Schottky diode based on the P-type island and the super-junction structure provided by the application adopts a plurality of heavily doped P-type island structures, introduces a lightly doped P-type region below the heavily doped P-type islands to form a super-junction structure, depletes electrons below a Schottky contact region, reduces a reverse leakage current of the device, increases a breakdown voltage of the device, and simultaneously uses P-type GaN as material of the heavily doped P-type islands and the lightly doped P-type regions to avoid a problem of difficulty in preparation of P-type Ga2O3.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of microelectronics, and particularly relates to a hybrid PIN Schottky diode based on a P-type island and a super-junction structure and a preparation method thereof. BACKGROUND

[0002] With the development of power supply, motor driver and electric vehicle, higher requirements are put forward for energy-saving electronic systems. After the first generation of semiconductor materials represented by Si and Ge, the second generation of semiconductor materials represented by GaAs and InP, and the third generation of semiconductor materials represented by GaN and SiC, the materials for preparing high-power devices have gradually developed to super-wide bandgap semiconductor materials. As one of the super-wide bandgap semiconductor materials, Ga2O3 material has great application potential in high-power electronic devices due to its unique advantages such as super-wide bandgap (4.9eV), high theoretical breakdown field strength (8MV / cm) and high BFOM value (3444).

[0003] A Schottky barrier diode (SBD) has a low on-resistance and a small reverse recovery time. However, it has a significant electric field concentration effect, and the device is prone to breakdown at the edge of the Schottky junction. A PIN diode has a low leakage current and a high breakdown voltage, so a hybrid PIN Schottky diode is usually formed by introducing a PIN structure into an SBD, so that the device has good forward and reverse characteristics.

[0004] However, the existing Ga2O3-based hybrid PIN Schottky diode still has a large on-resistance, and the breakdown voltage needs to be further improved. In addition, Ga2O3 is prone to introduce donor levels such as oxygen vacancies, making it difficult to prepare P-type Ga2O3. SUMMARY

[0005] In order to solve the above problems in the prior art, the application provides a hybrid PIN Schottky diode based on a P-type island and a super-junction structure and a preparation method thereof. The technical problems to be solved by the application are solved by the following technical solutions:

[0006] A hybrid PIN Schottky diode based on a P-type island and a super-junction structure, from bottom to top, comprises: a cathode, an n + -Ga2O3 substrate layer, an n - -Ga2O3 drift layer, an anode, wherein,

[0007] The n - -Ga2O3 drift layer and the anode are provided with a plurality of heavily doped P-type islands on the contact surface;

[0008] A plurality of lightly doped P-type regions are arranged below the heavily doped P-type island to be electrically connected with the n - The Ga2O3 drift layer forms a super junction structure.

[0009] In one embodiment of the present application, the heavily doped P-type island is in a trapezoidal structure.

[0010] In one embodiment of the present application, the thickness of the heavily doped P-type island is 250-500 nm, the length of the upper base is 0.5-3 μm, and the length of the lower base is 1-5 μm.

[0011] In one embodiment of the present application, the doping ion of the heavily doped P-type island is Mg ion, and the doping concentration is 1×10 18 -1×10 19 cm -3 .

[0012] In one embodiment of the present application, the lightly doped P-type region is in a multi-stage inclined slot structure, and the inclination angle of each stage is sequentially decreased from top to bottom.

[0013] In one embodiment of the present application, the doping ion of the lightly doped P-type region is Mg ion, and the doping concentration is 1×10 16 -1×10 18 cm -3 .

[0014] In one embodiment of the present application, the lightly doped P-type region is in a two-stage inclined slot structure; wherein,

[0015] The upper base of the first-stage inclined slot located at the top layer has a horizontal length of 1-5 μm, a height of 0.2-2 μm, and an inclination angle of 30°-80°;

[0016] The second-stage inclined slot located below the first-stage inclined slot has a height of 0.2-2 μm and an inclination angle of 10°-60°.

[0017] In one embodiment of the present application, the heavily doped P-type island and the lightly doped P-type region are both made of gallium nitride material.

[0018] Another embodiment of the present application further provides a preparation method of the hybrid PIN Schottky diode based on the P-type island and the super junction structure, comprising:

[0019] Selecting an n + -Ga2O3 substrate and performing cleaning;

[0020] Epitaxially growing a low-doped n + -Ga2O3 drift layer on one side of the n - -Ga2O3 substrate;

[0021] Performing ion implantation on the n- The Ga2O3 drift layer is etched for multiple times to form a plurality of multi-order inclined groove structures;

[0022] Lightly doped P-type material is deposited on the whole sample surface to form a lightly doped P-type region in the multi-order inclined groove structure;

[0023] Heavily doped P-type material is deposited on the whole sample surface and etched to form a heavily doped P-type island above the lightly doped P-type region;

[0024] The n + A cathode is made on the other side of the Ga2O3 substrate, and an anode is made on the obtained sample surface, so that the preparation of the device is completed.

[0025] In an embodiment of the present application, the n - The Ga2O3 drift layer is etched for multiple times to form a plurality of multi-order inclined groove structures, including:

[0026] The n - A first-order groove region with an inclined angle of α' is photoetched on the Ga2O3 drift layer;

[0027] On the basis of the first-order groove region, a second-order groove region with an inclined angle of β is photoetched, so that a two-inclined groove structure with the inclined angle of the first-order inclined groove being α and the inclined angle of the second-order inclined groove being β is formed; wherein α>α' and α>β.

[0028] Advantages of the present application:

[0029] 1. The hybrid PIN Schottky diode based on the P-type island and super-junction structure provided by the present application adopts a plurality of heavily doped P-type island structures, and a lightly doped P-type region is introduced below the P-type island structures to form a super-junction structure, so that the reverse leakage current of the device is reduced and the breakdown voltage of the device is increased by depleting the electrons below the Schottky contact region;

[0030] 2. The P-type island structure is designed into a trapezoidal structure and the doping concentration thereof is increased to form a heavily doped P-type island in the present application, so that the contact area of the P-type island and the anode metal is increased and the on-resistance of the device is reduced;

[0031] 3. The lightly doped P-type region is arranged as a multi-order inclined groove structure in the present application, so that the electric field concentration is alleviated and the electric field distribution is more uniform, and the breakdown voltage of the device is further improved;

[0032] 4. The P-type island and the P-type region are formed by using P-type gallium nitride material in the present application, the preparation process of which is relatively mature, and the P-type gallium nitride prepared has excellent quality and the doping concentration thereof can be specifically characterized and accurately controlled, which is helpful to improve the performance of the device.

[0033] The application will be described in further detail below with reference to the drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a structure schematic diagram of a hybrid PIN Schottky diode based on P-type island and super-junction structure provided by an embodiment of the application.

[0035] Figure 2 is a preparation method flowchart of a hybrid PIN Schottky diode based on P-type island and super-junction structure provided by an embodiment of the application.

[0036] Figures 3a-3g is a process chart of preparing a hybrid PIN Schottky diode with a two-order inclined groove structure of a lightly doped P-type region provided by an embodiment of the application. DETAILED DESCRIPTION

[0037] The application will be described in further detail below with reference to the drawings and embodiments.

[0038] Embodiment one

[0039] Please refer to Figure 1 , Figure 1 is a structure schematic diagram of a hybrid PIN Schottky diode based on P-type island and super-junction structure provided by an embodiment of the application, which includes, from bottom to top, a cathode 1, an n + -Ga2O3 substrate layer 2, an n - -Ga2O3 drift layer 3, and an anode 4, wherein,

[0040] The n - -Ga2O3 drift layer 3 and the anode 4 are provided with a plurality of heavily doped P-type islands 5 on the contact surface.

[0041] The heavily doped P-type islands 5 are correspondingly provided with a plurality of lightly doped P-type regions 6 below, so as to form a super-junction structure with the n - -Ga2O3 drift layer 3.

[0042] This embodiment adopts a plurality of heavily doped P-type island structures, and introduces a lightly doped P-type region below to form a super-junction structure, so as to deplete the electrons below the Schottky contact area, reduce the reverse leakage current of the device, and increase the breakdown voltage of the device.

[0043] Further, the heavily doped P-type islands 5 are in a trapezoidal structure.

[0044] Further, the thickness of the trapezoidal P-type island is 250-500 nm, the upper base length is 0.5-3 μm, and the lower base length is 1-5 μm.

[0045] In the embodiment, the doping ions of the heavily doped P-type island 5 are Mg ions, and the doping concentration is 1×10 18 ~1×10 19 cm -3 .

[0046] The embodiment increases the contact area of the P-type island and the anode metal, and reduces the on-resistance of the device by designing the P-type island structure into a trapezoidal structure and increasing the doping concentration to form a heavily doped P-type island.

[0047] Further, please continue to refer to Figure 1 , wherein the lightly doped P-type region 6 is a multi-order trapezoidal structure, and the inclination angles of each order of trapezoidal are sequentially reduced from top to bottom.

[0048] In the embodiment, the lightly doped P-type region 6 is located directly below the heavily doped P-type island 5, and the doping ions are also Mg ions, and the doping concentration is 1×10 16 ~1×10 18 cm -3 .

[0049] Optionally, as an implementation manner of the present application, the lightly doped P-type region 6 is a two-order trapezoidal structure, as shown in Figure 1 ; wherein,

[0050] The upper bottom of the first-order trapezoidal located at the top layer has a horizontal length of 1-5 μm, a height of 0.2-2 μm, and an inclination angle α of 30°-80°;

[0051] The second-order trapezoidal located below the first-order trapezoidal has a height of 0.2-2 μm and an inclination angle β of 10°-60°, and satisfies β < α.

[0052] The embodiment sets the lightly doped P-type region as a multi-order trapezoidal structure, moderates the electric field concentration, makes the electric field distribution more uniform, and further improves the breakdown voltage of the device.

[0053] Further, in the embodiment, the heavily doped P-type island 5 and the lightly doped P-type region 6 both adopt gallium nitride material, the preparation process of which is relatively mature, the P-type gallium nitride prepared has excellent quality, and the doping concentration can be specifically characterized and accurately controlled, which helps to improve the device performance and avoids the problem that P-type Ga2O3 is difficult to prepare in the prior art. In addition, P-type regions can also be realized by using other P-type substitutes such as P-type NiO.

[0054] Optionally, in the embodiment, the metal layer of the cathode 1 is a Ti / Au or Ti / Al / Ni / Au metal combination. The metal of the anode 4 is a Ni / Au combination or a Pt / Au combination.

[0055] Specifically, if the cathode metal is a Ti / Au combination, the growth thickness of the first layer of metal Ti is 10-50 nm, and the growth thickness of the second layer of metal Au is 100-400 nm. If the cathode metal is a Ti / Al / Ni / Au combination, the growth thickness of the first layer of metal Ti is 10-200 nm, the growth thickness of the second layer of metal Al is 10-200 nm, the growth thickness of the third layer of metal Ni is 10-200 nm, and the growth thickness of the fourth layer of metal Au is 50-400 nm.

[0056] The anode metal can be a Ni / Au combination or a Pt / Au combination, wherein the growth thickness of the first layer of metal Ni or Pt is 10-50 nm, and the growth thickness of the second layer of metal Au is 100-400 nm.

[0057] In addition, other metal combinations can be used to realize the anode and the cathode in the embodiment, and the present application is not limited in this regard.

[0058] Optionally, in the embodiment, n + The doping ions of the Ga2O3 substrate layer 2 are Si ions or Sn ions, and the doping concentration is 1x10 18 ~1x10 20 cm -3 , and the thickness is 300-650 μm; n - The doping ions of the Ga2O3 drift layer 3 are Si ions or Sn ions, and the doping concentration is 1x10 16 ~1x10 18 cm -3 , and the growth thickness is 5-15 μm.

[0059] The embodiment aims to solve the problems of large on-resistance, low breakdown voltage of the current hybrid PIN Schottky diode, and difficulty in preparing P-type Ga2O3, and provides a hybrid PIN Schottky diode based on a P-type island and a super-junction structure, which adopts a ladder-shaped structure of a heavily doped P-type island, introduces a lightly doped P-type region below the heavily doped P-type island, and designs the P-type region into a multi-stage inclined groove structure, simultaneously uses P-type gallium nitride as the P-type region, realizes a hybrid PIN Schottky diode structure based on P-type gallium nitride, reduces the on-resistance of the device, reduces the reverse leakage current of the device, increases the breakdown voltage of the device, improves the performance of the device, and avoids the problem of difficulty in preparing P-type Ga2O3 in the prior art.

[0060] Embodiment Two

[0061] Based on the above-mentioned embodiment one, the embodiment provides a preparation method of a hybrid PIN Schottky diode based on a P-type island and a super-junction structure. Please refer to Figure 2 , Figure 2This is a schematic flowchart of a hybrid PIN Schottky diode fabrication method based on a P-type island and superjunction structure provided by an embodiment of the present invention, specifically including:

[0062] S1: Select n + -Ga2O3 substrate and then cleaned.

[0063] Specifically, the doping ions can be selected as Si ions or Sn ions, and the doping concentration can be 1×10⁻⁶. 18 ~1×10 20 cm -3 n with a thickness of 300–650 μm + -Ga2O3 material is used as the substrate material. Existing standard cleaning methods can be referenced for this n + The Ga2O3 substrate is cleaned, but the specific cleaning process is not described in detail in this embodiment.

[0064] S2: In n + -Low-doped n-type epitaxial growth on one side of Ga2O3 substrate - -Ga2O3 drift layer.

[0065] Specifically, this embodiment uses the MOCVD method to clean the n + The Ga2O3 substrate was placed in an MOCVD apparatus, and the flow rate of trimethylgallium™Ga was 4.0 × 10⁻⁶. -6 ~8.0×10 -6 mol / min, O2 flow rate is 1.5 × 10 -2 ~3.5×10 -2 Under process conditions of mol / min, temperature of 70–100℃, and pressure of 500 Pa, at n + -Low-doped n-type atoms are formed on one side of the Ga2O3 substrate. - -Ga2O3 drift layer. Where, n - The Ga2O3 drift layer is doped with either Si or Sn ions at a concentration of 1 × 10⁻⁶. 16 ~1×10 18 cm -3 The growth thickness is 5–15 μm.

[0066] S3: For the n - The Ga2O3 drift layer is etched multiple times to form several multi-level oblique groove structures.

[0067] In this embodiment, the preferred multi-stage inclined groove structure is a two-stage inclined groove, then step S3 includes:

[0068] First, a photolithography process is used on the n - - A first-order groove region with an inclination angle of α′ is photolithographically etched on the Ga2O3 drift layer;

[0069] Then, based on the first-order groove region, a second-order groove region with an inclination angle of β is photolithographically etched, thereby forming a two-inclination groove structure with an inclination angle of α for the first-order groove and an inclination angle of β for the second-order groove; wherein, α>α′, α>β.

[0070] In addition, based on actual design requirements, etching can be performed again on the basis of the second-order groove area to form a multi-order oblique groove structure with two or more orders.

[0071] S4: Deposit lightly doped P-type material across the entire sample surface to form a lightly doped P-type region within the multi-level sloping groove structure.

[0072] Preferably, in this embodiment, a lightly doped P-type region is prepared using P-type gallium nitride material.

[0073] Specifically, using the MOCVD method, in low-doped n - P was prepared on Ga2O3. - -GaN layer (i.e., lightly doped P-type region). Wherein, P... - The GaN layer is doped with Mg ions, and the doping concentration is 1×10⁻⁶. 16 ~1×10 18 cm -3 The growth thickness is 400–4000 nm.

[0074] S5: Deposit heavily doped P-type material across the entire sample surface and etch to form heavily doped P-type islands over the lightly doped P-type regions.

[0075] Preferably, in this embodiment, heavily doped P-type islands are prepared using P-type gallium nitride material.

[0076] Specifically, based on step S4, P is formed on the sample surface using the MOCVD method. + -GaN layer. Where, P + The GaN layer is doped with Mg ions at a concentration of 1 × 10⁻⁶. 18 ~1×10 19 cm -3 The growth thickness is 250–500 nm.

[0077] Then, etching is performed to create openings. Photoresist is spin-coated onto P-type gallium nitride, and after photolithography, several trapezoidal P-type structures are etched using an ICP (Inductively Coupled Plasma) system. + -GaN islands, exposing the Schottky contact area, and removing the photoresist.

[0078] The specific parameters of the etching process are as follows: upper electrode power 250-300 W, lower electrode power 40-80 W, chamber pressure 9-12 mTorr, gas flow BCl3 / Cl2 30-60 / 30-60 sccm, and chuck temperature 15-20 DEG C.

[0079] In the embodiment, steps S4 and S5 can also be performed simultaneously, and in actual application, the preparation steps can be adjusted as needed, which is not specifically limited in the embodiment.

[0080] S6: forming an anode on the n + The other side of the Ga2O3 substrate is made into a cathode, and an anode is made on the surface of the obtained sample, so that the preparation of the device is completed.

[0081] First, a bottom electrode (cathode) is made. On the n + The other side of the Ga2O3 substrate is made into a cathode. A Ti / Au or Ti / Al / Ni / Au metal combination is evaporated on the back of the Ga2O3 substrate in sequence by using an electron beam evaporation table. After the electrode metal is evaporated, rapid thermal annealing is performed at 500-800 DEG C in an N2 environment for 50-80 s to form an ohmic contact.

[0082] Specifically, the cathode metal can be a Ti / Au combination, the growth thickness of the first layer of metal Ti is 10-50 nm, and the growth thickness of the second layer of metal Au is 100-400 nm.

[0083] In addition, the cathode metal can also be a Ti / Al / Ni / Au combination, the growth thickness of the first layer of metal Ti is 10-200 nm, the growth thickness of the second layer of metal Al is 10-200 nm, the growth thickness of the third layer of metal Ni is 10-200 nm, and the growth thickness of the fourth layer of metal Au is 50-400 nm.

[0084] Then, a top electrode (anode) is made. After photolithography, a Ni / Au combination or a Pt / Au combination is evaporated on the surface of the device in sequence by using an electron beam as an anode.

[0085] Specifically, the anode metal can be a Ni / Au combination or a Pt / Au combination, wherein the growth thickness of the first layer of metal Ni or Pt is 10-50 nm, and the growth thickness of the second layer of metal Au is 100-400 nm.

[0086] Thus far, the preparation of the hybrid PIN Schottky diode based on the P-type island and the super-junction structure is completed.

[0087] Embodiment three

[0088] Based on the above embodiment two, the preparation process of the present application will be introduced in detail below by taking the preparation of the mixed PIN Schottky diode with the second-order inclined groove structure of the light-doped P-type region as an example in combination with the accompanying drawings. Please refer to Figures 3a-3g , Figures 3a-3g is the process flow of the preparation of the mixed PIN Schottky diode with the second-order inclined groove structure of the light-doped P-type region provided by the embodiment of the present application, and specifically comprises the following steps:

[0089] Step 1: Selecting an n + -Ga2O3 substrate and performing cleaning.

[0090] Step 2: Epitaxially growing a low-doped n + -Ga2O3 drift layer on one side of the n - -Ga2O3 substrate.

[0091] Specifically, the cleaned n + -Ga2O3 substrate is placed into a MOCVD device to form a low-doped n -6 -Ga2O3 drift layer on one side of the n -6 -Ga2O3 substrate under the process conditions of a TMGa flow of 4.0×10 -2 ~ 3.5×10 -2 mol / min, an O2 flow of 1.5×10 + ~ 3.5×10 - mol / min, a temperature of 70~100℃, and a pressure of 500Pa, as shown in Figure 3a .

[0092] Step 3: Spin-coating photoresist and photoetching the first-order groove region pattern.

[0093] Specifically, the first-order groove is etched by using an ICP device, and the inclination angle of the side surface of the first-order groove is α'. After the etching is completed, the photoresist is removed, as shown in Figure 3b .

[0094] The photoetching conditions are as follows: upper electrode power of 200~350W, lower electrode power of 40~60W, chamber pressure of 4~20mTorr, Cl2 gas flow of 30~60sccm, and temperature of 10~50℃.

[0095] Step 4: Spin-coating photoresist and photoetching the second-order groove region pattern.

[0096] Specifically, the second-order groove is etched by using the ICP device, and the inclination angle of the first-order groove is α and the inclination angle of the second-order groove is β. After the etching is completed, the photoresist is removed, as shown in Figure 3c .

[0097] The photoetching condition is: upper electrode power 200-350 W, lower electrode power 40-60 W, chamber pressure 4-20 mTorr, Cl2 gas flow 30-60 sccm, and temperature 10-50℃.

[0098] In the embodiment, the second-order groove is formed by etching the sidewall of the first-order groove, so that α>α'. Through process control, the first-order groove has a horizontal length of 1-5 μm, a height of 0.2-2 μm, and an angle α of 30°-80°; and the second-order groove has a height of 0.2-2 μm and an angle β of 10°-60°.

[0099] Step 5: using MOCVD method, P - -Ga2O3 layer is prepared on the low-doped n - -GaN layer. + -GaN layer, as shown in Figure 3d .

[0100] The doping ion of the P - -GaN layer is Mg ion, and the doping concentration is 1×10 16 -1×10 18 cm -3 -1×10 + cm 18 -1×10 19 cm -3 , and the growth thickness is 250-500 nm.

[0101] Step 6: hole etching.

[0102] Specifically, photoresist is spin-coated on the P-type gallium nitride, and after photoetching, ICP equipment is used to etch a plurality of trapezoidal structure P + -GaN islands, expose the Schottky contact area, and remove the photoresist; as shown in Figure 3e .

[0103] The photoetching condition is: upper electrode power 250-300 W, lower electrode power 40-80 W, chamber pressure 9-12 mTorr, gas flow BCl3 / Cl2 30-60 / 30-60 sccm, and chuck temperature 15-20℃.

[0104] Step 7: making a bottom electrode (cathode).

[0105] The n +Growth of the cathode of the hybrid PIN Schottky diode on the other side surface of the Ga2O3 substrate. The Ti / Au metal combination is evaporated on the back surface of the Ga2O3 substrate in sequence by using an electron beam evaporation station. After the electrode metal is evaporated, rapid thermal annealing is performed in an N2 environment at 500-800°C for 50-80s to form an ohmic contact, as shown in Figure 3f .

[0106] The growth thickness of the first layer of metal Ti is 10-50nm, and the growth thickness of the second layer of metal Au is 100-400nm.

[0107] Step 8: Fabrication of the top electrode (anode).

[0108] The Ni / Au combination is evaporated on the surface of the device in sequence by using an electron beam as the anode, as shown in Figure 3g . The anode metal is a Ni / Au combination or a Pt / Au combination, the growth thickness of the first layer of metal Ni or Pt is 10-50nm, and the growth thickness of the second layer of metal Au is 100-400nm.

[0109] At this point, the fabrication of the hybrid PIN Schottky diode with a second-order inclined groove structure is completed.

[0110] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0111] In addition, the terms "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified.

[0112] In the present application, unless specifically stated and limited otherwise, the first feature "on" or "under" the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature "on", "above" and "over" the second feature includes that the first feature is directly above and obliquely above the second feature, or only means that the first feature is higher than the second feature in horizontal height. The first feature "under", "below" and "underneath" the second feature includes that the first feature is directly below and obliquely below the second feature, or only means that the first feature is lower than the second feature in horizontal height.

[0113] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and integrate different embodiments or examples described in the present application.

[0114] The above is a further detailed description of the present application in combination with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as falling within the protection scope of the present application.

Claims

1. A hybrid PIN Schottky diode based on P-type island and super junction structure, characterized in that, comprises successively from bottom to top: a cathode (1), n + a Ga2O3 substrate layer (2), n - a Ga2O3 drift layer (3), an anode (4), wherein, The n - A plurality of heavily doped P-type islands (5) are arranged on the contact surface between the Ga2O3 drift layer (3) and the anode (4); the heavily doped P-type islands (5) have a trapezoidal structure; the doping ions of the heavily doped P-type islands (5) are Mg ions, and the doping concentration is 1×10 18 ~1×10 19 cm -3 ; Corresponding to the heavy doped P type island (5), a plurality of lightly doped P type regions (6) are arranged, so as to be connected with the n - The Ga2O3 drift layer (3) forms a super junction structure; the lightly doped P type region (6) is a multi-stage inclined slot structure, and the inclined angle of each stage is sequentially reduced from top to bottom; the doping ion of the lightly doped P type region (6) is Mg ion, and the doping concentration is 1×10 16 ~1×10 18 cm -3 ; The heavily doped P-type island (5) and the lightly doped P-type region (6) are both made of gallium nitride material.

2. The hybrid PIN Schottky diode based on P-type island and super-junction structure according to claim 1, characterized in that, The thickness of the heavily doped P-type island (5) is 250-500 nm; the upper base length is 0.5-3 μm, and the lower base length is 1-5 μm.

3. The hybrid PIN Schottky diode based on P-type island and super-junction structure according to claim 1, characterized in that, The lightly doped P-type region (6) is a two-stage oblique groove structure; wherein, The upper base of the first-stage oblique groove on the top layer has a lateral length of 1-5 μm, a height of 0.2-2 μm, and an inclination angle of 30-80°; The second-stage oblique groove below the first-stage oblique groove has a height of 0.2-2 μm and an inclination angle of 10-60°.

4. A preparation method of a hybrid PIN Schottky diode based on P-type island and super-junction structure, characterized in that, Comprise: Selecting n + - Ga2O3substrate and cleaning; In n + - a low-doped n - - a Ga2O3 drift layer; n - The Ga2O3 drift layer is etched multiple times to form a plurality of multi-stage inclined groove structures, and the inclination angles of each stage of the inclined grooves decrease in turn from top to bottom. A lightly doped P-type material is deposited on the whole sample surface to form a lightly doped P-type region in the multi-stage inclined chute-shaped structure; the lightly doped P-type region is made of gallium nitride material; the doping ion of the lightly doped P-type region (6) is Mg ion, and the doping concentration is 1×10 16 ~1×10 18 cm -3 ; Depositing heavily doped P-type material on the whole sample surface and etching to form a heavily doped P-type island above the lightly doped P-type region; the heavily doped P-type island is in a trapezoidal structure; the heavily doped P-type island is made of gallium nitride material; the doping ion of the heavily doped P-type island (5) is Mg ion, and the doping concentration is 1×10 18 ~1×10 19 cm -3 ; In the n + The other side of the Ga2O3 substrate is fabricated with a cathode, and an anode is fabricated on the surface of the resulting sample, thereby completing the device.

5. The preparation method of the hybrid PIN Schottky diode based on P-type island and super-junction structure according to claim 4, characterized in that, n - - performing multiple etching on the Ga2O3 drift layer to form a plurality of multi-stage inclined channel structures, comprising: The photoetching process is adopted to photoetch the first-order groove region with the inclination angle of a' on the n - -Ga2O3 drift layer; On the basis of the first-stage groove region, a second-stage groove region with an inclination angle of β is photoetched, thereby forming a two-stage oblique groove structure with the first-stage oblique groove having an inclination angle of α and the second-stage oblique groove having an inclination angle of β; wherein α>α', and α>β.

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