Semiconductor device

Abstract

The utility model discloses a semiconductor device. The semiconductor device includes: a substrate; the buffer layer is positioned on one side of the substrate; the channel layer is located on the side, away from the substrate, of the buffer layer; the composite barrier layer comprises a first barrier layer and a second barrier layer, the first barrier layer is located on the side, away from the buffer layer, of the channel layer, and the second barrier layer is located on the side, away from the channel layer, of the first barrier layer; the band gap of the second barrier layer is larger than that of the first barrier layer; the dielectric layer is located on the side, away from the channel layer, of the composite barrier layer; the grid is located on one side, away from the composite barrier layer, of the dielectric layer; the source electrode is located on the side, away from the channel layer, of the composite barrier layer; and the drain electrode is positioned on one side, far away from the channel layer, of the composite barrier layer. According to the technical scheme, the dynamic characteristics of the depletion type gallium nitride semiconductor device are improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Technology

[0002] Gallium nitride semiconductor devices possess excellent electrical performance due to the high concentration of two-dimensional electron gas (2DEG) in the heterojunction formed by the channel layer and the barrier layer.

[0003] For depletion-type gallium nitride semiconductor devices, defects or interface states on the surface of the existing barrier layer can easily trap electrons in the channel, which has a significant impact on the dynamic characteristics of the device. Utility Model Content

[0004] This invention provides a semiconductor device to improve the dynamic characteristics of depletion-mode gallium nitride semiconductor devices.

[0005] According to one aspect of the present invention, a semiconductor device is provided, comprising:

[0006] Substrate;

[0007] A buffer layer is located on one side of the substrate;

[0008] The channel layer is located on the side of the buffer layer away from the substrate;

[0009] A composite barrier layer, comprising a first barrier layer and a second barrier layer, wherein the first barrier layer is located on the side of the channel layer away from the buffer layer, and the second barrier layer is located on the side of the first barrier layer away from the channel layer; the band gap of the second barrier layer is larger than the band gap of the first barrier layer.

[0010] A dielectric layer is located on the side of the composite barrier layer away from the channel layer;

[0011] The gate is located on the side of the dielectric layer away from the composite barrier layer;

[0012] The source electrode is located on the side of the composite barrier layer away from the channel layer;

[0013] The drain is located on the side of the composite barrier layer away from the channel layer.

[0014] Optionally, the composite barrier layer further includes a third barrier layer located on the side of the second barrier layer away from the first barrier layer.

[0015] Optionally, the band gap of the second barrier layer is larger than the band gap of the third barrier layer.

[0016] Optionally, the thickness of the second barrier layer is less than or equal to 20% of the thickness of the first barrier layer.

[0017] Optionally, the thickness of the second barrier layer is greater than or equal to 0.1 nanometers.

[0018] Optionally, the thickness of the second barrier layer is less than or equal to 3 nanometers.

[0019] Optionally, the second barrier layer includes an aluminum nitride barrier layer.

[0020] Optionally, the second barrier layer includes a gallium nitride aluminum barrier layer.

[0021] Optionally, the first barrier layer includes a gallium nitride aluminum barrier layer.

[0022] Optionally, the third barrier layer includes an aluminum gallium nitride barrier layer.

[0023] The semiconductor device provided by this invention comprises a first barrier layer and a second barrier layer forming a composite barrier layer, which is used to generate polarization with the channel layer, thereby creating a 2DEG between the composite barrier layer and the channel layer. The band gap of the second barrier layer is larger than that of the first barrier layer, effectively modulating the energy band of the second barrier layer. This makes it difficult for defects or interface states on the surface of the composite barrier layer to trap electrons in the channel, effectively improving the dynamic characteristics of the depletion-mode GaN HEMT device, improving leakage current, increasing gate breakdown voltage, and enhancing device reliability.

[0024] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0027] Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0028] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or apparatuses is not necessarily limited to those explicitly listed, but may include other steps or apparatuses not explicitly listed or inherent to such processes, methods, products, or apparatuses.

[0030] To improve the dynamic characteristics of depletion-mode gallium nitride semiconductor devices, the present invention provides the following technical solution:

[0031] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. The semiconductor device includes: a substrate 100; a buffer layer 200 located on one side of the substrate 100; a channel layer 300 located on the side of the buffer layer 200 away from the substrate 100; and a composite barrier layer 400, the composite barrier layer 400 including a first barrier layer 410 and a second barrier layer 420, the first barrier layer 410 being located on the side of the channel layer 300 away from the buffer layer 200, and the second barrier layer 420 being located on the side of the channel layer 300 away from the buffer layer 200. 0 is located on the side of the first barrier layer 410 away from the channel layer 300; the band gap of the second barrier layer 420 is larger than the band gap of the first barrier layer 410; the dielectric layer 500 is located on the side of the composite barrier layer 400 away from the channel layer 300; the gate 600 is located on the side of the dielectric layer 500 away from the composite barrier layer 400; the source 700 is located on the side of the composite barrier layer away from the channel layer 300; and the drain 800 is located on the side of the composite barrier layer 400 away from the channel layer 300.

[0032] For example, such as Figure 1As shown, the gallium nitride device also includes a buffer layer 200, which is used to mitigate the lattice mismatch problem between the substrate 100 and the channel layer 300. The channel layer 300 includes one or more of GaN, AlGaN, and InGaN layers.

[0033] In this embodiment, the semiconductor device is a depletion-type GaN semiconductor device, wherein the dielectric layer 500 is located on the side of the composite barrier layer 400 away from the channel layer 300.

[0034] The first barrier layer 410 and the second barrier layer 420 together form a composite barrier layer 400, which is used to generate polarization with the channel layer 300 so that 2DEG is generated between the composite barrier layer 400 and the channel layer 300.

[0035] In this embodiment, the substrate 100 is made of silicon. Of course, in other embodiments, the substrate 100 can also be made of other substrate materials, such as sapphire, gallium nitride, silicon carbide, and diamond. The substrate 100 is used to support structures such as the buffer layer 200, the channel layer 300, the composite barrier layer 400, and the dielectric layer 500.

[0036] The technical solution provided by this utility model involves a first barrier layer 410 and a second barrier layer 420 forming a composite barrier layer 400, which is used to generate a polarization effect with the channel layer 300, thereby generating a 2DEG between the composite barrier layer 400 and the channel layer 300. The band gap of the second barrier layer 420 is larger than that of the first barrier layer 410, effectively modulating the energy band of the second barrier layer 420. This makes it difficult for defects or interface states on the surface of the composite barrier layer 400 to trap electrons in the channel, effectively improving the dynamic characteristics of the depletion-mode GaN HEMT device, improving device leakage current, increasing gate breakdown voltage, and enhancing device reliability.

[0037] Optionally, based on the above technical solutions, such as Figure 2 As shown, Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. The composite barrier layer 400 further includes a third barrier layer 430, which is located on the side of the second barrier layer 420 away from the first barrier layer 410.

[0038] Specifically, the third barrier layer 430, the second barrier layer 420, and the first barrier layer 410 together form a composite barrier layer 400, which further increases the thickness and number of barrier layers, and further enhances the concentration of 2DEG generated between the channel layer 300 and the composite barrier layer 400.

[0039] Optionally, based on the above technical solutions, such as Figure 2 As shown, the band gap of the second barrier layer 420 is larger than that of the third barrier layer 430.

[0040] Specifically, the band gap of the second barrier layer 420 is larger than that of the first barrier layer 410, and the band gap of the second barrier layer 420 is larger than that of the third barrier layer 430. Electrons in the channel cannot jump to the second barrier layer 420 and are captured by defects or interface states on the surface of the third barrier layer 430. This effectively improves the dynamic characteristics of the depletion-mode GaN HEMT device, improves device leakage current, increases gate breakdown voltage, and enhances device reliability.

[0041] Optionally, based on the above technical solutions, such as Figure 1 and Figure 2 As shown, the thickness of the second barrier layer 420 is less than or equal to 20% of the thickness of the first barrier layer 410.

[0042] Specifically, the thickness of the second barrier layer 420 is thinner and needs to be within 20% of the thickness of the first barrier layer 410. This avoids the problem of excessive on-resistance and low two-dimensional electron gas concentration caused by the setting of the second barrier layer 420 with a relatively high band gap.

[0043] Optionally, based on the above technical solutions, such as Figure 1 and Figure 2 As shown, the thickness of the second barrier layer 420 is greater than or equal to 0.1 nanometers.

[0044] Specifically, if the thickness of the second barrier layer 420 is less than 0.1 nanometers, its thickness is too small, resulting in a weak blocking effect on electrons in the channel. Therefore, the thickness of the second barrier layer 420 needs to be set to be greater than or equal to 0.1 nanometers.

[0045] Optionally, based on the above technical solutions, such as Figure 1 and Figure 2 As shown, the thickness of the second barrier layer 420 is less than or equal to 3 nanometers.

[0046] Specifically, when the thickness of the second barrier layer 420 is greater than 3 nanometers, the device is too thick, the on-resistance of the device is too large, which is not conducive to improving the dynamic characteristics of the semiconductor device.

[0047] Optionally, based on the above technical solutions, such as Figure 1 and Figure 2 As shown, the second barrier layer 420 includes an aluminum nitride barrier layer.

[0048] Specifically, when the first barrier layer 410 and the third barrier layer 430 include a gallium nitride barrier layer or a gallium aluminum nitride barrier layer, the aluminum content of the aluminum nitride barrier layer is greater than that of the first barrier layer 410 and the third barrier layer 430. This results in the band gap of the second barrier layer 420 being greater than that of the first barrier layer 410 and the third barrier layer 430. Electrons in the channel cannot jump to the second barrier layer 420 and are captured by defects or interface states on the surface of the third barrier layer 430. This effectively improves the dynamic characteristics of the depletion-mode GaNHEMT device, improves device leakage current, increases gate withstand voltage, and enhances device reliability.

[0049] Optionally, based on the above technical solutions, such as Figure 1 and Figure 2 As shown, the second barrier layer 420 includes a gallium nitride aluminum barrier layer.

[0050] Optionally, based on the above technical solutions, such as Figure 1 and Figure 2 As shown, the first barrier layer 410 includes a gallium nitride aluminum barrier layer.

[0051] Optionally, based on the above technical solutions, such as Figure 1 and Figure 2 As shown, the third barrier layer 430 includes a gallium nitride aluminum barrier layer.

[0052] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.

[0053] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A buffer layer is located on one side of the substrate; The channel layer is located on the side of the buffer layer away from the substrate; A composite barrier layer, comprising a first barrier layer and a second barrier layer, wherein the first barrier layer is located on the side of the channel layer away from the buffer layer, and the second barrier layer is located on the side of the first barrier layer away from the channel layer; the band gap of the second barrier layer is larger than the band gap of the first barrier layer. A dielectric layer is located on the side of the composite barrier layer away from the channel layer; The gate is located on the side of the dielectric layer away from the composite barrier layer; The source electrode is located on the side of the composite barrier layer away from the channel layer; The drain is located on the side of the composite barrier layer away from the channel layer.

2. The semiconductor device according to claim 1, characterized in that, The composite barrier layer further includes a third barrier layer, which is located on the side of the second barrier layer away from the first barrier layer.

3. The semiconductor device according to claim 2, characterized in that, The band gap of the second barrier layer is larger than that of the third barrier layer.

4. The semiconductor device according to claim 1, characterized in that, The thickness of the second barrier layer is less than or equal to 20% of the thickness of the first barrier layer.

5. The semiconductor device according to claim 1, characterized in that, The thickness of the second barrier layer is greater than or equal to 0.1 nanometers.

6. The semiconductor device according to claim 5, characterized in that, The thickness of the second barrier layer is less than or equal to 3 nanometers.

7. The semiconductor device according to claim 1, characterized in that, The second barrier layer includes an aluminum nitride barrier layer.

8. The semiconductor device according to claim 1, characterized in that, The second barrier layer includes a gallium nitride aluminum barrier layer.

9. The semiconductor device according to claim 1, characterized in that, The first barrier layer includes a gallium nitride aluminum barrier layer.

10. The semiconductor device according to claim 2, characterized in that, The third barrier layer includes an aluminum gallium nitride barrier layer.

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