Integrated circuit chip and method of forming the same

Abstract

Various embodiments of the present invention relate to an integrated circuit (IC) chip including a display pixel in which a bottom electrode is separate from and abuts a reflector. A light emitting device is disposed on top of the reflector, and a top electrode is disposed on top of the light emitting device. A coupling structure extends from the bottom electrode along a side of the reflector to an interface between the light emitting device and the reflector to electrically couple the bottom electrode to the light emitting device. Embodiments of the present invention also relate to another integrated circuit chip and a method of forming the same.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to integrated circuit chips and methods of forming the same. BACKGROUND

[0002] Microdisplays are small displays typically having screen sizes with diagonals less than one or two inches. Microdisplays are used in mobile applications, head-mounted displays, projectors, and digital cameras, among other uses. Microdisplays include a plurality of pixels that cooperate to generate an image by transmission, reflection, or emission of light. Emissive microdisplays are increasingly used. SUMMARY

[0003] Some embodiments of the present invention provide an integrated circuit chip comprising a display pixel, wherein the display pixel comprises a bottom electrode, a reflector abutting the bottom electrode, a light emitting device disposed above the reflector, a top electrode disposed above the light emitting device, and a coupling structure extending from the bottom electrode along a side of the reflector to an interface between the light emitting device and the reflector to electrically couple the bottom electrode to the light emitting device.

[0004] Other embodiments of the present invention provide an integrated circuit chip comprising a semiconductor device, a bottom electrode disposed above the semiconductor device, an interconnect structure between and electrically coupled to the bottom electrode and the semiconductor device, a reflector above the interconnect structure and abutting the bottom electrode, a light emitting device disposed above the reflector, a coupling via disposed above the bottom electrode and electrically coupled to the bottom electrode, wherein the coupling via extends from a top to a bottom along a side of the reflector, and a coupling layer laterally extending from a bottom surface of the light emitting device to the coupling via.

[0005] Still other embodiments of the present invention provide a method for forming an integrated circuit (IC) chip comprising forming a bottom electrode disposed above a semiconductor device and electrically coupled to the semiconductor device by an interconnect structure, depositing a pixel dielectric layer covering the bottom electrode, forming a reflector inserted into the pixel dielectric layer, wherein the reflector comprises a first metal and is adjacent to the bottom electrode, performing a selective etch of the pixel dielectric layer to form a via opening disposed above the bottom electrode and exposing the bottom electrode, forming a coupling structure disposed above the reflector and extending from the reflector to the bottom electrode through the via opening, wherein the coupling structure comprises a second metal, and forming a light emitting device disposed above the coupling structure and the reflector. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the application are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not to scale. On the contrary, the dimensions of the various features can be arbitrarily expanded or reduced for clarity. Like reference numerals can be used to denote like features throughout the specification and figures.

[0007] Figure 1 A cross-sectional view of some embodiments of an integrated circuit (IC) chip comprising display pixels with a bottom electrode and a reflector that are separate is provided.

[0008] Figure 2A and Figure 2B A top view of some different embodiments of the reflector of Figure 1 and Figure 1 A top view of some different embodiments of the coupling structure of

[0009] Figures 3A to 31 A cross-sectional view of some alternative embodiments of the IC chip of Figure 1 is provided.

[0010] Figure 4 An enlarged cross-sectional view of some embodiments of the IC chip of Figure 1 is provided.

[0011] Figures 5 to 15 A series of cross-sectional views of some embodiments of a method for forming an IC chip comprising display pixels with a bottom electrode and a reflector that are separate is provided.

[0012] Figure 16 A block diagram of some embodiments of the method of Figures 5 to 15 is provided.

[0013] Figures 17 to 21 A series of cross-sectional views of some alternative embodiments of the method of Figures 5 to 15 is provided. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments, or examples, for implementing different components of the provided subject matter. Each of the described embodiments can be implemented alone or in combination with one another. For the purpose of clarity, not all combinations of the embodiments described herein are made. The detailed description includes specific details for the purpose of providing a thorough understanding of the innovative teachings. However, it will be apparent to those skilled in the art that the innovative teachings can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the innovative subject matter. The following description and drawings are illustrative of the innovative subject matter and are not to be construed as limiting the inventive subject matter. Numerous specific details are described to provide a thorough understanding of the innovative subject matter. However, in certain instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the inventive subject matter. The innovative subject matter is described with reference to the following drawings, in which like reference numerals refer to like elements in the figures. The drawings are intended to depict only typical aspects of the innovative subject matter and are not intended to limit the scope of the innovative subject matter. In the drawings: Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this innovative subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the inventive subject matter and will not be interpreted in an overly literal sense unless expressly so defined herein.

[0015] Moreover, relative terms such as "below" or "lower", "above" or "upper", can be used herein to describe a relationship of one element or component to another element or component as illustrated in the figures. Such relative terms can be used to describe specific spatial and / or topological relationships for a device in use or operation. The device can be oriented in other ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein can be interpreted accordingly.

[0016] An integrated circuit (IC) chip can include a microdisplay structure integrated with display drivers on a common semiconductor substrate. The microdisplay structure is disposed above the display drivers on a front side of the common semiconductor substrate and includes a plurality of pixels. The pixels can include a bottom electrode / reflector, a light emitting device disposed above the bottom electrode / reflector, and a top electrode disposed above the light emitting device.

[0017] A challenge for the IC chip is that the bottom electrode / reflector is typically a metal that has a high reactivity with oxygen and is oxidized to form a dielectric natural oxide. For example, the bottom electrode / reflector can be aluminum or some other suitable metal. Due to the high reactivity, it is likely that a natural oxide layer is formed along the top of the reflector during fabrication of the IC chip. The natural oxide layer electrically isolates the bottom electrode / reflector from the light emitting device because the natural oxide layer is a dielectric. This in turn creates an electrical break, resulting in a lower yield for mass production.

[0018] To mitigate this challenge, the bottom electrode / reflector can be a metal that has a low reactivity with oxygen and / or is oxidized to form a conductive natural oxide. However, such a metal has a low reflectivity. Thus, if such a metal is used, the microdisplay structure will have poor optical performance.

[0019] Various embodiments of the present invention are directed to an IC chip including a display pixel in which a bottom electrode and a reflector are separate, and a method of forming the IC chip. A light emitting device is disposed above the reflector, and a top electrode is disposed above the light emitting device. A coupling structure extends from the bottom electrode along a side of the reflector to a bottom surface of the light emitting device to electrically couple the bottom surface to the bottom electrode.

[0020] Because the bottom electrode and the reflector are separate, and because the coupling structure extends from the bottom electrode to the bottom surface of the light emitting device, electrical coupling from the bottom surface of the light emitting device to the display drivers or some other suitable circuit is independent of the reflector. As such, the materials of the reflector, the bottom electrode, and the coupling structure can be selected separately in order to achieve both good optical performance and prevent oxidation-induced electrical break from the bottom electrode to the bottom surface of the light emitting device.

[0021] The material of the reflector can be selected to have high reflectivity, even though it can also have high reactivity with oxygen and even though it can be oxidized to form a dielectric native oxide. The high reflectivity can facilitate good optical performance. The material of the bottom electrode and the conductive structure can be selected to have low reactivity with oxygen, respectively, and even though the reflectivity of the material can be low, it can be oxidized to form a native conductive oxide. The low reactivity and the conductive native oxide can prevent electrical disconnection from the bottom electrode to the bottom surface of the light emitting device, and thus the yield of mass production can be high.

[0022] Reference Figure 1 A cross-sectional view 100 of some embodiments of an IC chip including a display pixel 102 is provided, in which a bottom electrode 104 and a reflector 106 are separated. The display pixel 102 is disposed on top of and electrically coupled to an interconnect structure 108, which includes a bottom electrode via 110b that is inserted into an interconnect dielectric layer 112. The interconnect structure 108 can provide, for example, electrical coupling from the bottom electrode 104 to display driver circuitry or other suitable circuitry.

[0023] The bottom electrode 104 is disposed on top of the bottom electrode via 110b and under a pixel dielectric layer 114. In addition, the bottom electrode 104 is separated from the bottom electrode via 110b by a bottom electrode barrier 116 and electrically coupled to the bottom electrode via 110b. In optional embodiments, the bottom electrode barrier 116 can be omitted. The bottom electrode barrier 116 is electrically conductive and blocks diffusion material from the bottom electrode via 110b to the bottom electrode 104. The bottom electrode barrier 116 can be, for example, or include, titanium nitride (e.g., TiN), tantalum nitride (e.g., TaN), some other suitable material, or any combination of the above.

[0024] The reflector 106 is inserted into and extends through the pixel dielectric layer 114. In addition, the reflector 106 interfaces with and partially covers the bottom electrode 104. In optional embodiments, the reflector 106 and the bottom electrode 104 are laterally spaced apart such that the bottom electrode 104 is not covered by the reflector 106. The reflector 106 includes a conductor 106b and a native oxide layer 106n on top of the conductor 106b. The conductor 106b is or includes an electrically conductive material, and the native oxide layer 106n is or includes a native oxide of the electrically conductive material. In some embodiments, the native oxide layer 106n can be discontinuous or can be omitted.

[0025] The light emitting device 118 is disposed on top of the reflector 106, and the top electrode 120 is disposed on top of the light emitting device 118. The top electrode 120 is transparent, and can be or include, for example, gold (e.g., Au), silver (e.g., Ag), indium tin oxide (ITO), some other suitable conductive material, or any combination of the above. The light emitting device 118 can be, for example, a micro light emitting diode, an organic light emitting diode (OLED), a light emitting diode (LED), or some other suitable device.

[0026] The coupling structure 122 is disposed on top of the bottom electrode 104 and the reflector 106. Further, the coupling structure 122 extends from a top surface of the bottom electrode 104 along a side of the reflector 106 to a bottom surface of the light emitting device 118 to provide electrical coupling from the bottom electrode 104 to the light emitting device 118. The coupling structure 122 includes a coupling layer 1221 and a coupling via 122v.

[0027] The coupling via 122v is a portion of the coupling layer 1221 that has a top recess and extends from the bottom electrode 104 through the pixel dielectric layer 114. In an optional embodiment, the coupling via 122v is distinct from the coupling layer 1221. The coupling layer 1221 extends from the coupling via 122v to an interface 124 between the light emitting device 118 and the reflector 106 to provide electrical coupling from the coupling via 122v to the bottom surface of the light emitting device 118.

[0028] Because the bottom electrode 104 and the reflector 106 are separated, and because the coupling structure 122 extends from the bottom electrode 104 to the bottom surface of the light emitting device 118, electrical coupling from the bottom surface to the interconnect structure 108 is through the bottom electrode 104 and the coupling structure 122, rather than through the reflector 106. Accordingly, the materials of the reflector 106, the bottom electrode 104, and the coupling structure 122 can be selected separately to achieve good optical performance and to prevent oxidation-induced electrical disconnection from the bottom electrode 104 to the bottom surface of the light emitting device 118.

[0029] The material of the reflector 106 can be selected so that it has high reflectivity, even though it can also have high reactivity with oxygen and can be oxidized to form a dielectric native oxide. High reflectivity can facilitate good optical performance. The materials of the bottom electrode 104 and the coupling structure 122 can be selected separately so that the material has low reactivity with oxygen and is oxidized to form a conductive native oxide, even though the material can have low reflectivity. Low reactivity and a conductive native oxide can prevent native oxide-induced electrical disconnection from the bottom electrode 104 to the bottom surface of the light emitting device 118, so that the yield of high volume manufacturing can be high. Also, note that metals that have low reactivity with oxygen and / or are oxidized to form a conductive native oxide tend to have low reflectivity.

[0030] With continued reference to Figure 1 In optional embodiments, either the first or second dielectric layers 114a, 114b are omitted. The first and second dielectric layers 114a, 114b are different materials, and can be or include, for example, silicon oxide (e.g., Si02), silicon nitride (e.g., SiN), some other suitable material, or any combination of the above. In some embodiments, the first dielectric layer 114a is silicon nitride and the second dielectric layer 114b is silicon oxide, or vice versa.

[0031] In some embodiments, the bottom electrode via 110b is or includes copper, tungsten, some other suitable conductive material and / or metal, or any combination of the above. In some embodiments in which the bottom electrode via 110b is or includes copper, the bottom electrode barrier 116 is or includes tantalum nitride or some other suitable barrier material for copper. In some embodiments in which the bottom electrode via 110b is or includes tungsten, the bottom electrode barrier 116 is or includes titanium nitride or some other suitable barrier material for tungsten. In some embodiments, the interconnect dielectric layer 112 is or includes silicon oxide (e.g., Si02) and / or some other suitable dielectric.

[0032] In some embodiments, the reflector 106 is more reactive with oxygen than the coupling structure 122 and / or the bottom electrode 104. For example, the reflector 106 can react with oxygen with less energy than the coupling structure 122 and / or the bottom electrode 104. In some embodiments, the reflector 106 reacts with oxygen with less than about 3 electron volts (eV), 4 eV, or some other suitable amount of energy. In some embodiments, the reflector 106 can reflect a greater percentage of radiation emitted by the light emitting device 118 than the coupling structure 122 and / or the bottom electrode 104. For example, the reflector 106 can reflect a greater percentage of radiation than the coupling structure 122 and / or the bottom electrode 104. In some embodiments, the conductor 106b is or includes aluminum and / or some other suitable metal. In some embodiments, the conductor 106b is or includes aluminum and the native oxide layer 106n is or includes aluminum oxide. In optional embodiments, the reflector 106 is a dielectric, such that the conductor 106b and the native oxide layer 106n are replaced by dielectric layers.

[0033] In some embodiments, the width Wr of the reflector 106 is or includes about 100 nanometers to about 50 micrometers, about 100 nanometers to about 25 micrometers, about 25 to 50 micrometers, or some other suitable value. In some embodiments, the height Hr of the reflector is about 1 to 20 kiloangstroms, about 1 to 10 kiloangstroms, about 10 to 20 kiloangstroms, or some other suitable value.

[0034] In some embodiments, the bottom electrode 104 and the coupling structure 122 are the same material. In other embodiments, the bottom electrode 104 and the coupling structure 122 are different materials. The bottom electrode 104 and / or the coupling structure 122 can be, for example, or include, tantalum nitride (e.g., TaN), titanium nitride (e.g., TiN), ITO, platinum (e.g., Pt), gold (e.g., Au), some other suitable metal and / or conductive material, or any combination of the above. In addition, the bottom electrode 104 and / or the coupling structure 122 can be, for example, or include, a noble metal and / or an inert metal. In some embodiments, the bottom electrode 104 and / or the coupling structure 122 have low reactivity with oxygen. For example, the bottom electrode 104 and / or the coupling structure 122 can react with oxygen depending on an energy greater than about 5 eV, 6 eV, or some other suitable amount. In some embodiments, a native oxide of the bottom electrode 104 is conductive and / or a native oxide of the coupling structure 122 is conductive. In some embodiments, a native oxide of the bottom electrode 104 and / or a native oxide of the coupling structure 122 has a lower resistivity than the native oxide layer 106n.

[0035] In some embodiments, the width Wv of the coupling via 122v is about 50 to 1000 nanometers, about 50 to 500 nanometers, about 500 to 1000 nanometers, or some other suitable value. If the width Wv is too small (e.g., less than about 50 nanometers), process control during formation of the coupling via 122v can be excessively difficult, and manufacturing yield can be low. If the width Wv is too large (e.g., greater than about 1000 nanometers), pixel density can be low. In addition, topography at the display pixel 102 can have high variations, which can present processing challenges and reduce manufacturing yield.

[0036] In some embodiments, the thickness Tc of the coupling layer 122l is about 50 to 1000 angstroms, about 50 to 500 angstroms, about 500 to 1000 angstroms, or some other suitable value. If the thickness Tc is too small (e.g., less than about 50 angstroms), resistance from the bottom electrode 104 to the bottom surface of the light emitting device 118 can be high, and electrical performance can be poor. If the thickness Tc is too large (e.g., greater than about 1000 angstroms), topography at the display pixel 102 can have high variations, which can present processing challenges and reduce manufacturing yield.

[0037] Referring to Figure 2A and Figure 2B , top-down views 200A, 200B of some different embodiments of the reflector 106 of Figure 1 and the coupling structure 122 of Figure 1 are provided. Figure 1 The cross-sectional view 100 of Figures 2A to 2Bline A-A or along Figures 2A to 2B some other suitable line.

[0038] In Figure 2A , the reflector 106 and the coupling structure 122 collectively define a square or a rectangle. Further, the coupling structure 122 is at a corner of the square or the rectangle, and is itself triangular. In alternative embodiments, the coupling structure 122 is at any other corner of the square or the rectangle shape.

[0039] In Figure 2B , the reflector 106 and the coupling structure 122 are the same as Figure 2A , except that the coupling structure 122 is offset from a corner of the square or the rectangle. Further, the coupling structure 122 is itself a square or a rectangle.

[0040] While Figure 2A and Figure 2B show the reflector 106 and the coupling structure 122 collectively defining a square or a rectangle, in alternative embodiments, the reflector 106 and the coupling structure 122 can define a circle, a triangle, or some other suitable shape. Further, in alternative embodiments, the individual shapes of the reflector 106 and the coupling structure 122 can also be different. For example, Figure 2A the coupling structure 122 of

[0041] Referring to Figures 3A to 31 , cross-sectional views 300A to 300I are provided of some different alternative embodiments of the IC chip of Figure 1 .

[0042] In Figure 3A , the bottom electrode 104 and the bottom electrode barrier 116 extend along a bottom surface of the reflector 106 from a first sidewall of the reflector 106 to a second sidewall of the reflector 106 opposite the first sidewall. Further, the bottom electrode 104 and the bottom electrode barrier 116 have an individual width that is greater than a width Wr of the reflector 106. Correspondingly, within the cross-sectional view 300A of Figure 3A , the bottom electrode 104 directly contacts an entire bottom surface of the reflector 106. In some embodiments, outside of the cross-sectional view 300A of Figure 3A , the bottom electrode 104 further directly contacts an entire bottom surface of the reflector 106.

[0043] In Figure 3BIn some embodiments, the coupling via 122v is always solid (e.g., completely fills the via opening in which it is formed) rather than U-shaped or V-shaped. In addition, the top surface of the coupling layer 1221 is planar and continuous from a first side of the coupling via 122v to a second side of the coupling via 122v opposite the first side at a height above the reflector 106. Because the coupling via 122v is always solid, the electrical resistance from the bottom electrode 104 to the bottom surface of the light emitting device 118 is reduced and the electrical performance of the display pixel 102 is improved.

[0044] In Figure 3C , the coupling layer 1221 has a width that is greater than the width Wr of the reflector 106 and extends along the top surface of the reflector 106 from a first sidewall of the reflector 106 to a second sidewall of the reflector 106 opposite the first sidewall. In addition, the coupling layer 1221 has a width that is greater than the width of the light emitting device 118 and extends along the bottom surface of the light emitting device 118 from a first sidewall of the light emitting device 118 to a second sidewall of the light emitting device 118 opposite the first sidewall. Accordingly, in Figure 3C , the cross-sectional view 300C of the display pixel 102, the coupling layer 1221 directly contacts the entire top surface of the reflector 106 and directly contacts the entire bottom surface of the light emitting device 118. In some embodiments, the coupling layer 1221 further directly contacts the entire top surface of the reflector 106 and / or the coupling layer 1221 further directly contacts the entire bottom surface of the light emitting device 118 outside of Figure 3C , the cross-sectional view 300B of the display pixel 102. Figure 3C , the cross-sectional view 300B of the display pixel 102.

[0045] The contact area of the coupling layer 1221 directly contacting the bottom surface of the light emitting device 118 is greater than the contact area in Figure 1 because the coupling layer 1221 covers the top surface of the reflector 106. As such, the contact resistance between the bottom surface of the light emitting device 118 and the coupling layer 1221 is reduced. This in turn can improve the electrical performance (e.g., power consumption) of the display pixel 102. Additionally, because the coupling layer 1221 covers the top surface of the reflector 106, the coupling layer 1221 is transparent to the radiation emitted by the light emitting device 118. For example, the coupling layer 1221 can be or include ITO, gold (e.g., Au), silver (e.g., Ag), some other suitable material, or any combination of the above. The transparency prevents the coupling layer 1221 from affecting or reducing the impact of the coupling layer 122 on the optical performance of the display pixel 102.

[0046] In Figure 3D , the display pixel 102 is the same as Figure 3C except that the coupling via 122v is always solid (e.g., completely fills the via opening in which it is formed) as described with respect to Figure 3B .

[0047] In some embodiments, the display pixel 102 is the same as in Figure 3E , except that the coupling via 122v and the coupling layer 122l are different from each other. For example, the coupling via 122v and the coupling layer 122l can be different materials. Figure 3D

[0048] In some embodiments, the coupling via 122v is or includes tantalum nitride, titanium nitride, some other suitable material, or any combination of the above, and / or the coupling layer 122l is or includes ITO, gold (e.g., Au), silver (e.g., Ag), some other suitable material, or any combination of the above. In some embodiments, the coupling via 122v is opaque to radiation emitted by the light emitting device 118, whereas the coupling layer 122l is transparent to the radiation. In some embodiments, the coupling layer 122l has a higher transmissivity to radiation emitted by the light emitting device 118 than the coupling via 122v. In some embodiments, the coupling via 122v and the coupling layer 122l have the same or similar transmissivity to radiation emitted by the light emitting device 118.

[0049] In some embodiments, the display pixel 102 is the same as in Figure 3F , except that the coupling via 122v directly contacts a sidewall of the reflector 106. In addition, a bottom surface of the coupling via 122v has a stepped profile. In alternative embodiments, the bottom surface of the coupling via 122v is flat from a first side of the coupling via 122v to a second side of the coupling via 122v opposite the first side.

[0050] In some embodiments, the display pixel 102 is the same as in Figure 3G , except that the bottom electrode 104 and the bottom electrode barrier 116 are laterally separated from the reflector 106, such that the reflector 106 is not disposed on top of the bottom electrode 104 and the bottom electrode barrier 116.

[0051] In some embodiments, the display pixel 102 is the same as in Figure 3H , except that the bottom electrode barrier 116 is omitted. As a result, the bottom electrode 104 directly contacts the bottom electrode via 110b.

[0052] In some embodiments, the display pixel 102 is the same as in Figure 31 , except that the IC chip includes a pair of coupling structures 122 respectively on opposite sides of the reflector 106. The coupling structures 122 are independent of the bottom electrode 104 and are respectively disposed on top of the bottom electrode 104. In addition, the coupling structures 122 respectively extend from the bottom electrode 104 through the pixel dielectric layer 114 to a bottom surface of the light emitting device 118 on opposite sides of the reflector 106.

[0053] The bottom electrode 104 is independent of the bottom electrode via 110b and is respectively disposed on top of the bottom electrode via 110b, which is formed by the interconnect structure 108 in​Figure 3H The cross-sectional view 300H shows an external electrical short circuit. Furthermore, the bottom electrode 104 is spaced apart from and electrically coupled to the bottom electrode through-hole 110b via the bottom electrode block 116. The bottom electrode 104, bottom electrode through-hole 110b, bottom electrode block 116, and coupling structure 122 are related to... Figure 1 The corresponding objects described are the same.

[0054] Because the multiple coupling structures 122 and the multiple bottom electrodes 104 provide electrical coupling from the bottom surface of the light-emitting device 118 to the interconnect structure 108, the resistance between them is reduced. This reduced resistance can, in turn, enhance the electrical performance (e.g., power consumption) of the display pixels 102.

[0055] although Figures 3A to 31 Described Figure 1 Variations of display pixel 102 can be applied to any of the variations or combinations of variations. Figures 3A to 31 Any of the display pixels 102. For example, Figure 3D The display pixel 102 may optionally have a bottom electrode 104 and a bottom electrode block 116 extending along the bottom surface of the reflector 106 from a first sidewall of the reflector 106 to a second sidewall of the reflector 106 opposite to the first sidewall, as per [reference to...]. Figure 3A As described and shown. As another example, Figure 31 The display pixel 102 may optionally have a solid coupling via 122v, rather than... Figure 3B The U-shape or V-shape shown and described.

[0056] refer to Figure 4 Provided Figure 1 An enlarged cross-sectional view 400 of some embodiments of an IC chip is shown, wherein the IC chip includes a plurality of display pixels 102 and a plurality of semiconductor devices 402. Each display pixel 102 is as shown in relation to... Figure 1 The description defines and specifies the display structure.

[0057] The semiconductor devices 402 define display driver circuitry configured to drive the display structure. The semiconductor devices 402 are independent of the display pixels 102 and are respectively disposed underneath the display pixels 102. Further, the semiconductor devices 402 are electrically coupled to the individual display pixels 102 by the interconnect structure 108 and the semiconductor devices 402 are configured to drive the individual display pixels 102. In some embodiments, the semiconductor devices 402 are metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (finFETs), gate-all-around field effect transistors (GAAFETs), or some other suitable type of transistor and / or semiconductor device. The semiconductor devices 402 include individual well regions 404, individual pairs of source / drain regions 406, and individual gate electrodes 408.

[0058] The well regions 404 are respectively inserted into a top of the semiconductor substrate 410 and correspond to doped regions of the semiconductor substrate 410. Further, the well regions 404 have a different doping type and / or a different doping concentration than a bulk of the semiconductor substrate 410. In optional embodiments, the semiconductor devices 402 share a common well region 404 and / or omit the well regions 404.

[0059] The pairs of source / drain regions 406 are respectively inserted into a top of the semiconductor substrate 410 at the well regions 404. In some embodiments, the source / drain regions 406 correspond to doped regions of the semiconductor substrate 410 having a different doping type than an adjoining region of the semiconductor substrate 410 and / or the well regions 404. In other embodiments, the source / drain regions 406 are different than the semiconductor substrate 410 and have a different semiconductor material than the semiconductor substrate 410. The source / drain regions 406 of each pair are laterally spaced apart to define a channel region 412 extending between the pair of source / drain regions 406.

[0060] The gate electrodes 408 are respectively disposed on top of the channel regions 412 laterally between the corresponding pairs of source / drain regions 406. Further, the gate electrodes 408 are separated from the semiconductor substrate 410 by a common gate dielectric layer 414. In optional embodiments, the gate electrodes 408 are separated from the semiconductor substrate 410 by individual gate dielectric layers 414.

[0061] Isolation structures 416 are inserted into a top of the semiconductor substrate 410 to laterally separate the semiconductor devices 402 from one another. Further, the isolation structures 416 include a dielectric material to provide electrical isolation between the semiconductor devices 402. In some embodiments, the isolation structures 416 are shallow trench isolation (STI) structures, field oxide isolation structures, or some other suitable isolation structure.

[0062] The interconnect structure 108 is located between the display pixels 102 and the semiconductor devices 402 to electrically couple the display pixels 102 to the semiconductor devices 402, respectively. The interconnect structure 108 includes a plurality of wires 418 and a plurality of vias 110, and the plurality of vias 110 includes bottom electrode vias 110b at the display pixels 102, respectively. The wires 418 and the vias 110 are grouped into a plurality of wire levels and a plurality of via levels, respectively, that are alternately stacked from the semiconductor devices 402 to the display pixels 102.

[0063] Although Figure 4 the display pixels 102 are described and shown configured according to the same embodiment, the display pixels 102 can be optionally configured according to different embodiments. For example, one of the display pixels 102 can be configured according to an embodiment of Figure 1 , and another one of the display pixels 102 can be configured according to an embodiment of Figures 3A to 31 . Furthermore, although Figure 4 the display pixels 102 are described and shown configured according to the same embodiment, the display pixels 102 can be optionally configured according to different embodiments. For example, one of the display pixels 102 can be configured according to an embodiment of Figure 1 , and another one of the display pixels 102 can be configured according to an embodiment of Figure 3B .

[0064] Referring to Figures 5 to 15 , a series of cross-sectional views 500-1500 of some embodiments of a method for forming an IC chip including display pixels are provided, in which the bottom electrode and the reflector are separated. The IC chip can be, for example, the one shown and described with respect to Figure 4 .

[0065] As shown in cross-sectional view 500 of Figure 5 , a plurality of semiconductor devices 402 is formed. The semiconductor devices 402 are formed to be inserted into a top portion of a semiconductor substrate 410, separated from each other by isolation structures 416. The semiconductor devices 402 and the isolation structures 416 are as described with respect to Figure 4 . For example, the semiconductor devices 402 can be MOSFETs, finFETs, GAAFETs, or some other suitable type of semiconductor devices.

[0066] The display pixels 102 are also formed by Figure 5A cross-sectional view 500 shows formation of an interconnect structure 108 that covers and is electrically coupled to the semiconductor device 402. The interconnect structure 108 includes a plurality of wires 418 and a plurality of vias 110 that are inserted into the interconnect dielectric layer 112. The wires 418 and the vias 110 are respectively grouped into a plurality of wire levels and a plurality of via levels that are alternately stacked to define conductive paths that respectively lead from the semiconductor device 402 to bottom electrode vias 110b at a top of the interconnect structure 108. The bottom electrode vias 110b are independent of the semiconductor device 402 and are respectively disposed above the semiconductor device 402.

[0067] As shown in a cross-sectional view 600, a plurality of bottom electrodes 104 and a plurality of bottom electrode barriers 116 are formed that are disposed above and electrically coupled to the interconnect structure 108. In an optional embodiment, the plurality of bottom electrode barriers 116 are not formed. The bottom electrode barriers 116 are respectively disposed above and electrically coupled to the bottom electrode vias 110b, and the bottom electrodes 104 are respectively disposed above and electrically coupled to the bottom electrode barriers 116. Thus, the bottom electrodes 104 are respectively electrically coupled to the bottom electrode vias 110b through the bottom electrode barriers 116. Figure 6 The bottom electrode barriers 116 are electrically conductive and are diffusion barriers for the material of the bottom electrode vias 110b. For example, when the bottom electrode vias 110b are tungsten or include tungsten, the bottom electrode barriers 116 can be or include titanium nitride or some other suitable barrier material. As another example, when the bottom electrode vias 110b are copper or include copper, the bottom electrode barriers 116 can be or include tantalum nitride or some other suitable barrier material.

[0068] In some embodiments, a thickness Tbb of the bottom electrode barriers 116 is about 10 to 10,000 Angstroms, about 10 to 5,000 Angstroms, about 50 to 10,000 Angstroms, or some other suitable amount. If the thickness Tbb is too large (e.g., greater than about 10,000 Angstroms), the electrical resistance from the bottom electrode vias 110b to the bottom electrodes 104 can be high, and the electrical performance (e.g., power consumption) can be poor. If the thickness Tbb is too small (e.g., less than about 10 Angstroms), the bottom electrode barriers 116 can not be suitable for preventing diffusion of the material of the bottom electrode vias 110b.

[0069]

[0070] ​The bottom electrode 104 can be or include, for example, tantalum nitride (e.g., TaN), titanium nitride (e.g., TiN), ITO, platinum (e.g., Pt), gold (e.g., Au), some other suitable metal and / or conductive material, or any combination thereof. In some embodiments, the bottom electrode 104 is or includes a noble metal and / or an inert metal. In some embodiments, the bottom electrode 104 has low reactivity with oxygen. For example, the bottom electrode 104 can react with oxygen depending on an energy greater than about 5 eV, 6 eV, or some other suitable amount. In some embodiments, a native oxide of the bottom electrode 104 (to the extent it forms) is conductive.

[0071] In some embodiments, the thickness Tbe of the bottom electrode 104 is about 10 to 10,000 Angstroms, about 10 to 5,000 Angstroms, about 50 to 10,000 Angstroms, or some other suitable amount. If the thickness Tbe is too large (e.g., greater than about 10,000 Angstroms), the electrical resistance from the bottom surface of the bottom electrode 104 to the top surface of the bottom electrode 104 can be high, and the electrical performance (e.g., power consumption) can be poor. In some embodiments, the width Wbe of the bottom electrode 104 is about 50 to 50,000 nanometers, about 50 to 25,000 nanometers, about 25,000 to 50,000 nanometers, or some other suitable amount. If the width Wbe is too small (e.g., less than about 50 nanometers), the landing of a subsequently formed coupling via on the bottom electrode 104 can be challenging, whereby electrical disconnection can occur and yield can be low. If the width Wbe is too large (e.g., greater than about 50 micrometers), the pixel density can be low, thereby increasing cost.

[0072] The process for forming the plurality of bottom electrodes 104 and the plurality of bottom electrode barriers 116 includes: 1) depositing a barrier layer covering the interconnect structure 108; 2) depositing an electrode layer covering the barrier layer; and 3) patterning the barrier layer and the electrode layer into the bottom electrodes 104 and the bottom electrode barriers 116, respectively. The patterning can be performed, for example, by a photolithography / etching process or by some other suitable selective etching and / or patterning process. In alternative embodiments, the plurality of bottom electrodes 104 and the plurality of bottom electrode barriers 116 are formed by some other suitable process.

[0073] As Figure 7As shown in cross-sectional view 700, a pixel dielectric layer 114 is deposited covering the interconnect structure 108 and the bottom electrode 104. Furthermore, a pixel dielectric layer 114 conformally to the bottom electrode 104 is deposited, such that the top surface of the pixel dielectric layer 114 is not flat. The pixel dielectric layer 114 includes a first dielectric layer 114a and a second dielectric layer 114b disposed on top of the first dielectric layer 114a. In optional embodiments, the first or second dielectric layers 114a, 114b are omitted. The first dielectric layer 114a and the second dielectric layer 114b are different materials. For example, the first dielectric layer 114a may be or include silicon nitride and / or some other suitable nitride, and / or the second dielectric layer 114b may be or include silicon oxide and / or some other suitable oxide, and vice versa. Note that other materials are also possible.

[0074] In some embodiments, the thickness Tdl of the first dielectric layer 114a is about 100 to 10,000 angstroms, about 100 to 5,000 angstroms, about 5,000 to 10,000 angstroms, or some other suitable amount. Additionally, in some embodiments, the thickness Td2 of the second dielectric layer 114b is about 1,000 to 10,000 angstroms, about 1,000 to 5,500 angstroms, about 5,500 to 10,000 angstroms, or some other suitable amount.

[0075] like Figure 8 As shown in cross-sectional view 800, planarization is performed on the pixel dielectric layer 114 to smooth its top surface. As a result of planarization, the thickness Tpd of the pixel dielectric layer 114 directly above the bottom electrode 104 is smaller than the thickness Tpd of the pixel dielectric layer 114 laterally offset from the side of the bottom electrode 104. Planarization can be performed, for example, by chemical mechanical polishing (CMP) or by some other suitable planarization process.

[0076] like Figure 9 As shown in the cross-sectional view 900, the pixel dielectric layer 114 is patterned to form a plurality of reflector openings 902. The reflector openings 902 are independent of the semiconductor device 402 and are respectively positioned above the semiconductor device 402. Furthermore, the reflector openings 902 expose the top surface of the interconnect dielectric layer 112 and the top surface of the bottom electrode 104. In an alternative embodiment, the reflector openings 902 are located above the bottom electrode 104, such that the reflector openings 902 expose the bottom electrode 104 instead of the interconnect dielectric layer 112. For example, when forming according to... Figure 3A or Figure 3B This alternative embodiment can be produced when the display pixels of the embodiment are formed. In the alternative embodiment, the reflector opening 902 is spaced apart from the bottom electrode 104, such that the reflector opening 902 exposes the interconnect dielectric layer 112 but does not expose the bottom electrode 104. For example, when forming according to Figure 3GThis optional embodiment can be produced when considering the display pixels of the embodiments in the example.

[0077] In some embodiments, the top surface portion 904 of the bottom electrode 104 exposed in the reflector opening 902 is patterned, thereby giving the top surface of the bottom electrode 104 a stepped profile. In alternative embodiments, the top surface is flat after patterning. In some embodiments, the width Wr of the reflector opening 902 is about 100 to 50,000 nanometers, about 100 to 25,000 nanometers, about 25,000 to 50,000 nanometers, or some other suitable amount.

[0078] Patterning can be performed, for example, by photolithography / etching processes or by some other suitable selective etching and / or patterning processes. Etching in photolithography / etching processes can be performed, for example, by dry etching, wet etching, some other suitable type of etching, or any combination thereof.

[0079] like Figure 10 As shown in the cross-sectional view 1000, the deposited reflective layer 1002 covers the pixel dielectric layer 114 and fills the reflector opening 902 (see example). Figure 9 Furthermore, the deposited reflector layer 1002 conforms to the topography of the IC chip, resulting in an uneven top surface of the reflector layer 1002. The reflector layer 1002 is conductive and may be, for example, or include aluminum, some other suitable metal and / or conductive materials, or any combination thereof. In an alternative embodiment, the reflector layer 1002 is a dielectric. Since the reflector layer 1002 is not used for electrically coupling the subsequently formed light-emitting device to the interconnect structure 108, the reflector layer 1002 can be a dielectric. Although the reflector layer 1002 can be a dielectric, it is noted that metals are generally more reflective than dielectrics.

[0080] In some embodiments, the reflector layer 1002 is more reflective than the bottom electrode 104 for radiation emitted by the subsequently formed light-emitting device. For example, the reflector layer 1002 may reflect a greater percentage of incident radiation from the light-emitting device than the bottom electrode 104. In some embodiments, the reflector layer 1002 is more reactive with oxygen than the bottom electrode 104. For example, the reflector layer 1002 may require less energy to react with oxygen compared to the bottom electrode 104. In some embodiments, the reflector layer 1002 requires less than about 4 eV, 3 eV, or some other suitable amount of energy to react with oxygen, and / or the bottom electrode 104 requires more than about 5 eV, 6 eV, or some other suitable amount of energy to react with oxygen. In some embodiments, the native oxide of the reflector layer 1002 is dielectric and / or has a greater resistivity than the native oxide of the bottom electrode 104.

[0081] like Figure 11as shown in cross-sectional view 1100, planarization is performed on the reflector layer 1002 (see, e.g., FIG. 1 1 1 ) to smooth the top surface of the reflector layer 1002 and confine the reflector layer 1002 to the reflector openings 902 (see, e.g., FIG. 1 12). In addition, the planarization forms a plurality of reflectors 106 from the portions of the reflector layer 1002 that are confined to the reflector openings 902. The reflectors 106 are independent of the reflector openings 902 and respectively fill the reflector openings 902. In addition, the reflectors 106 include separate conductors 106b and separate native oxide layers 106n. The planarization can be performed, e.g., by CMP or by some other suitable planarization process. Figure 10 ) to smooth the top surface of the reflector layer 1002 and confine the reflector layer 1002 to the reflector openings 902 (see, e.g., FIG. 1 12). In addition, the planarization forms a plurality of reflectors 106 from the portions of the reflector layer 1002 that are confined to the reflector openings 902. The reflectors 106 are independent of the reflector openings 902 and respectively fill the reflector openings 902. In addition, the reflectors 106 include separate conductors 106b and separate native oxide layers 106n. The planarization can be performed, e.g., by CMP or by some other suitable planarization process. Figure 9 ) to smooth the top surface of the reflector layer 1002 and confine the reflector layer 1002 to the reflector openings 902 (see, e.g., FIG. 1 12). In addition, the planarization forms a plurality of reflectors 106 from the portions of the reflector layer 1002 that are confined to the reflector openings 902. The reflectors 106 are independent of the reflector openings 902 and respectively fill the reflector openings 902. In addition, the reflectors 106 include separate conductors 106b and separate native oxide layers 106n. The planarization can be performed, e.g., by CMP or by some other suitable planarization process.

[0082] The conductors 106b are the same material as the reflector layer 1002. The native oxide layers 106n are respectively disposed on the conductors 106b and are formed from oxidation of the conductors 106b during the planarization. In optional embodiments, the native oxide layers 106n are formed during subsequent processing, such that there is no native oxide layer 106n. In addition, the native oxide layers 106n are native oxides of the reflector layer 1002. In some embodiments, the conductors 106b are or include aluminum, whereas the native oxide layers 106n are or include aluminum oxide. However, other suitable materials are possible. In some embodiments, the native oxide layers 106n are dielectric and / or have a greater resistivity than the native oxide of the bottom electrode 104.

[0083] As shown in cross-sectional view 1200, the patterned pixel dielectric layer 114 is patterned to form a plurality of via openings 1202. The via openings 1202 are independent of the bottom electrodes and are respectively disposed on the bottom electrodes 104. In addition, the via openings 1202 expose the top surfaces of the bottom electrodes 104 and are spaced apart from the reflectors 106. In optional embodiments, the via openings 1202 overlap the reflectors 106 and expose sidewalls of the reflectors 106. Figure 12 In some embodiments, the width Wv of the via openings 1202 is about 100 to 1000 nanometers, about 100 to 550 nanometers, about 550 to 1000 nanometers, or some other suitable amount. If the width Wv is too small (e.g., less than about 50 nanometers), process control during formation of the via openings 1202 can be very difficult, and manufacturing yield can be low. If the width Wv is too large (e.g., greater than about 1000 nanometers), pixel density can be low. In addition, topography at the via openings 1202 can have a high degree of variation, which can present processing challenges and reduce manufacturing yield.

[0084]

[0085] ​Patterning can be performed, for example, by photolithography / etching processes or by some other suitable selective etching and / or patterning processes. Etching in photolithography / etching processes can be performed, for example, by dry etching, wet etching, some other suitable type of etching, or any combination thereof.

[0086] like Figure 13 As shown in the cross-sectional view 1300, a conductive layer 1302 is deposited covering the reflector 106 and the pixel dielectric layer 114. Furthermore, a pad is deposited in the via opening 1202 and partially fills the conductive layer 1302. The conductive layer 1302 may be, for example, or include tantalum nitride (e.g., TaN), titanium nitride (e.g., TiN), ITO, platinum (e.g., Pt), gold (e.g., Au), some other suitable one or more metals and / or one or more conductive materials, or any combination thereof. In some embodiments, the conductive layer 1302 is or includes a noble metal and / or an inert metal. The conductive layer 1302 may be, for example, the same material as the bottom electrode 104 or a different material.

[0087] In some embodiments, the conductive layer 1302 is less reflective than the reflector 106 to radiation emitted by a subsequently formed light-emitting device. For example, the conductive layer 1302 may reflect a greater percentage of incident radiation from the light-emitting device than the reflector 106. In some embodiments, the conductive layer 1302 is less reactive with oxygen than the reflector 106. For example, the conductive layer 1302 may rely on more energy to react with oxygen than the reflector 106. In some embodiments, the conductive layer 1302 relies on more than about 5 eV, 6 eV, or some other suitable amount of energy to react with oxygen, and / or the reflector 106 relies on less than about 3 eV, 4 eV, or some other suitable amount of energy to react with oxygen. In some embodiments, the native oxide of the conductive layer 1302 is conductive and / or has a lower resistivity than the native oxide layer 106n of the reflector 106. In some embodiments, the conductive layer 1302 is transparent to radiation emitted by a subsequently formed light-emitting device.

[0088] In some embodiments, the thickness Tc of the conductive layer 1302 is about 50 to 1000 angstroms, about 50 to 500 angstroms, about 500 to 1000 angstroms, or some other suitable amount. If the thickness Tc is too small (e.g., less than about 50 angstroms), the resistance from the bottom electrode 104 to the subsequently formed light-emitting device may be high and the electrical performance may be poor. If the thickness Tc is too large (e.g., greater than about 1000 angstroms), it may waste material and may reduce production yield.

[0089] like Figure 14 The patterned conductive layer 1302 shown in the cross-sectional view 1400 (see example) Figure 13) to form a plurality of coupling structures 122. The coupling structures 122 provide electrical coupling to the subsequently formed light emitting devices and extend from the bottom electrodes 104, respectively, through the via openings 1202 to the top surface of the reflectors 106, respectively. In addition, the coupling structures 122 partially cover the reflectors 106 and include individual coupling layers 1221 and individual coupling vias 122v. The coupling vias 122v are portions of the respective coupling layers 1221 that have a top recess and extend through the pixel dielectric layer 114. In an optional embodiment, the coupling layers 1221 completely cover the respective reflectors 106. For example, when the display pixels are formed in accordance with the embodiment of FIG. 1, such an optional embodiment can be produced. Figures 3C to 3E Such an optional embodiment can be produced, for example, when the display pixels are formed in accordance with the embodiment of FIG. 1.

[0090] The patterning can be performed, for example, by a lithography / etching process or by some other suitable selective etching and / or patterning process. The etching of the lithography / etching process can be performed, for example, by dry etching, wet etching, some other suitable type of etching, or any combination of the foregoing.

[0091] As shown in the cross-sectional view 1500 of FIG. 1, a plurality of light emitting devices 118 and a plurality of top electrodes 120 are formed. The light emitting devices 118 are disposed on top of the reflectors 106, respectively, and have a bottom surface, respectively, and directly contact the coupling structures 122. As such, the coupling structures 122 electrically couple the bottom surfaces to the bottom electrodes 104, respectively. The top electrodes 120 are disposed on top of the light emitting devices, respectively. Figure 15

[0092] The top electrodes 120 are transparent and can be, for example, or include gold (e.g., Au), silver (e.g., Ag), indium tin oxide (ITO), some other suitable conductive material, or any combination of the foregoing. The light emitting devices 118 can be, for example, micro-LEDs, OLEDs, LEDs, or some other suitable devices. A preferred dielectric layer can be formed on the pixel dielectric layer 114 and fill the openings of the coupling vias 122v.

[0093] The electrical coupling from the bottom surfaces to the interconnect structure 108 is through the bottom electrodes 104 and the coupling structures 122 and not through the reflectors 106 because the bottom electrodes 104 and the reflectors 106 are separated and because the coupling structures 122 extend from the bottom electrodes 104 to the bottom surfaces of the light emitting devices 118. As such, the materials of the reflectors 106, the bottom electrodes 104, and the coupling structures 122 can be selected, respectively, to obtain good optical performance and to prevent oxidation-induced electrical disconnection from the bottom electrodes 104 to the bottom surfaces of the light emitting devices 118.

[0094] ​The material of the reflector 106 can be selected so that it has a high reflectivity, even though it can also have a high reactivity with oxygen and even though it can be oxidized to form a dielectric natural oxide. The high reflectivity can facilitate good optical performance. The material of the bottom electrode 104 and the coupling structure 122 can be selected so that the material has a low reactivity with oxygen and is oxidized to form a conductive natural oxide, even though the material can have a low reflectivity. The low reactivity and the conductive natural oxide can prevent electrical disconnection from the bottom electrode 104 to the bottom surface of the light emitting device 118 caused by the natural oxide, so that the yield of mass production can be high. In addition, it should be noted that metals having a low reactivity with oxygen and / or being oxidized to form a conductive natural oxide tend to have a low reflectivity.

[0095] Although various embodiments of methods are described with reference to the elements of the method, Figures 5 to 15 it should be understood that Figures 5 to 15 the structures shown are not limited to the method, but can be used independently of the method. Although the Figures 5 to 15 is described as a series of acts, it will be understood that the order of acts can be changed in other embodiments. Although Figures 5 to 15 is shown and described as a set of particular acts, some of the acts shown and / or described can be omitted in other embodiments. Additionally, acts shown and / or described can be included in other embodiments.

[0096] With reference to Figure 16 , a block diagram 1600 of some embodiments of a method of Figures 5 to 15 is provided.

[0097] At 1602, a semiconductor device is formed disposed on top of and inserted into a semiconductor substrate. See, e.g., FIG. 1. Figure 5 .

[0098] At 1604, an interconnect structure is formed covering the semiconductor device, wherein the interconnect structure includes a bottom electrode via at a top of the interconnect structure and the bottom electrode via is electrically coupled to the semiconductor device. See, e.g., FIG. 2. Figure 5 .

[0099] At 1606, a bottom electrode and a bottom electrode barrier are formed stacked disposed on top of and electrically coupled to the bottom electrode via. See, e.g., FIG. 3. Figure 6 .

[0100] At 1608, a pixel dielectric layer is deposited covering the bottom electrode and the interconnect structure. See, e.g., FIG. 4. Figure 7 .

[0101] At 1610, planarization is performed on the pixel dielectric layer to smooth a top surface of the pixel dielectric layer. See, e.g., FIG. 5.Figure 8 .

[0102] At 1612, the pixel dielectric layer is patterned to form a reflector opening positioned on top of the semiconductor device. See, for example... Figure 9 .

[0103] At position 1614, a reflector layer is deposited that covers the pixel dielectric layer and fills the reflector opening. See example. Figure 10 .

[0104] At position 1616, planarization is performed on the reflector layer to form a reflector confined to the reflector opening. See example. Figure 11 .

[0105] At 1618, a patterned pixel dielectric layer is formed to create a via opening that sits above the bottom electrode and exposes the bottom electrode. See, for example... Figure 12 .

[0106] At 1620, a coupling structure is formed that extends from the bottom electrode to the top surface of the reflector through the through-hole opening. See, for example... Figure 13 and Figure 14 The formation of the coupling structure may, for example, include: depositing a conductive layer covering the reflector and padding the via openings (see, for example...). Figure 13 ); and patterned conductive layers (see, for example) Figure 14 ).

[0107] At position 1622, a light-emitting device is formed above the reflector and coupling structure, wherein the bottom surface of the light-emitting device is electrically coupled to a bottom electrode via the coupling structure and a bottom electrode. See example Figure 15 .

[0108] At position 1624, a top electrode is formed, positioned above the light-emitting device. See example. Figure 15 .

[0109] Although in this article, Figure 16 The block diagram 1600 illustrates and describes a series of actions or events, but it will be understood that the order in which such actions or events are shown should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events in addition to those shown and / or described herein. Furthermore, not all of the actions shown may be required to implement one or more aspects or embodiments described herein, and one or more actions described herein may be performed in one or more separate actions and / or phases.

[0110] refer to Figures 17 to 21 Provided Figures 5 to 15A series of cross-sectional views 1700 to 2100 of some alternative embodiments of the method, wherein the coupling via 122v completely fills the via opening 1202. Alternative embodiments may, for example, form as... Figure 3E The display pixels in the image.

[0111] In an optional embodiment, regarding Figures 5 to 12 The described actions remain unchanged. Therefore, according to the optional embodiment, as shown and described above, the following is performed: Figures 5 to 12 The described action. Afterwards, as... Figure 17 As shown in the cross-sectional diagram 1700, the execution regarding... Figure 13 The described action, in addition to depositing a conductive layer 1302 that completely fills the via opening 1202 (see example...), Figure 12 ).

[0112] like Figure 18 As shown in the cross-sectional view 1800, planarization is performed on the conductive layer 1302 to confine the conductive layer 1302 within the via opening 1202. Furthermore, planarization forms a plurality of coupling vias 122v from the portion confined within the via opening 1202. The coupling vias 122v are independent of the via opening 1202 and each fills the via opening 1202. Planarization can be performed, for example, by CMP or by some other suitable planarization process.

[0113] like Figure 19 As shown in the cross-sectional view 1900, an additional conductive layer 1902 is deposited covering the reflector 106 and the coupling via 122V. The additional conductive layer 1902 is related to... Figure 13 The conductive layer 1302 described is the same. However, in some embodiments, the additional conductive layer 1902 is also transparent to the radiation emitted by the subsequently formed light-emitting device. For example, the additional conductive layer 1902 may be, for example, ITO, gold (e.g., Au), silver (e.g., Ag), or some other suitable conductive material, and / or the conductive layer 1302 may be, for example, titanium nitride (e.g., TiN), tantalum nitride (e.g., TaN), or some other suitable conductive material. It will be understood that the transparency of the additional conductive layer 1902 allows the radiation to be reflected by the reflector 106.

[0114] like Figure 20 The cross-sectional view of 2000 shows a patterned additional conductive layer (see, for example...). Figure 19) to form a plurality of coupling layers 1221. The coupling layers 1221 cover the reflectors 106 and the coupling vias 122v, respectively. Further, each coupling layer 1221 extends along a top surface of the corresponding reflector 106 from a first sidewall of the corresponding reflector 106 to a second sidewall of the corresponding reflector 106 opposite the first sidewall. The patterning can be performed, for example, by a lithography / etching process or by some other suitable selective etching and / or patterning process.

[0115] The coupling layers 1221 and the coupling vias 122v define coupling structures 122. Each coupling structure 122 includes a corresponding one of the coupling layers 1221 and a corresponding one of the coupling vias 122v. As described above, the coupling structures 122 provide electrical coupling to light emitting devices formed subsequently, and extend from the bottom electrodes 104, respectively, through the via openings 1202 (see, e.g., FIG. 19B), respectively, to the top surfaces of the reflectors 106 Figure 12

[0116] As shown in cross-sectional view 1900, as described and illustrated above, the actions described with respect to FIGS. 19A-19B are performed. Figure 19 Figure 15

[0117] While the method is described with reference to a particular order of acts, it should be understood that this order is merely exemplary and that other acts can be performed between or during the acts shown and described in other embodiments. Additionally or alternatively, the acts shown and described can be performed in an order different from that shown and described. Figures 17 to 21 While the structures shown in the figures are described with reference to a particular method, it should be understood that the structures are not limited to that method, but can be used independently of that method. Although the structures are described as a series of acts, it should be understood that the order of acts can be changed in other embodiments. Although the structures are illustrated and described as a particular set of acts, some of the acts shown and / or described can be omitted in other embodiments. Additionally, acts not shown and / or described can be included in other embodiments. Figure 17 Figure 21 Figures 17 to 21 Figures 17 to 21

[0118] ​​​​​​​In some embodiments, the present invention provides an IC chip comprising a display pixel, wherein the display pixel comprises: a bottom electrode; a reflector interfacing the bottom electrode; a light emitting device disposed above the reflector; a top electrode disposed above the light emitting device; and a coupling structure extending from the bottom electrode along a side of the reflector to an interface between the light emitting device and the reflector to electrically couple the bottom electrode to the light emitting device. In some embodiments, a native oxide of the coupling structure has a smaller electrical resistance than a native oxide of the reflector. In some embodiments, the reflector partially covers the bottom electrode. In some embodiments, the reflector has a first sidewall and a second sidewall located on opposite sides of the reflector, respectively, wherein the bottom electrode extends along a bottom surface of the reflector from the first sidewall to the second sidewall. In some embodiments, the reflector has a first sidewall and a second sidewall located on opposite sides of the reflector, respectively, wherein the coupling structure extends along a top surface of the reflector from the first sidewall to the second sidewall. In some embodiments, the coupling structure comprises: a coupling via extending from the bottom electrode to a top of the reflector along a side of the reflector; and a coupling layer disposed above the reflector and below the light emitting device, wherein the coupling layer extends laterally from the coupling via to the interface. In some embodiments, the IC chip further comprises: a semiconductor substrate; and a semiconductor device disposed above the semiconductor and inserted into the semiconductor substrate; and an alternating stack of wires and vias disposed above the semiconductor device; wherein the display pixel is disposed above the alternating stack, and wherein the alternating stack defines a conductive path from the semiconductor device to the bottom electrode.

[0119] In some embodiments, the present invention provides another IC chip comprising: a semiconductor device; and a bottom electrode disposed on top of the semiconductor device; an interconnect structure between and electrically coupled to the bottom electrode and the semiconductor device; a reflector on top of the interconnect structure and abutting the bottom electrode; a light emitting device disposed on top of the reflector; a coupling via disposed on top of the bottom electrode and electrically coupled to the bottom electrode, wherein the coupling via extends from a top to a bottom along a side of the reflector; and a coupling layer laterally extending from a bottom surface of the light emitting device to the coupling via. In some embodiments, the coupling via, the coupling layer, and the reflector are electrically conductive, wherein the coupling via and the coupling layer are more energy dependent to be oxidized than the reflector. In some embodiments, the reflector comprises a metal layer and a native oxide layer on top of the metal layer, wherein the coupling layer is disposed on top of and directly contacts a top surface of the native oxide layer. In some embodiments, the coupling via is a portion of the coupling layer having a top recess. In some embodiments, the coupling via is continuous from a first side of the coupling via to a second side of the coupling via opposite the first side at a height about flush with a top surface of the reflector. In some embodiments, the coupling via is different from and of a different type of material than the coupling layer. In some embodiments, the coupling layer and the reflector collectively have a rectangular top geometry, wherein the reflector has a triangular top geometry at a corner of the rectangular top geometry. In some embodiments, the coupling via directly contacts a sidewall of the reflector. In some embodiments, the reflector has a greater reflectivity than the coupling layer and / or the coupling via.

[0120] In some embodiments, the present invention provides a method for forming an IC chip, the method comprising: forming a bottom electrode disposed on top of a semiconductor device and electrically coupled to the semiconductor device by an interconnect structure; and depositing a pixel dielectric layer covering the bottom electrode; forming a reflector inserted into the pixel dielectric layer, wherein the reflector comprises a first metal and is adjacent to the bottom electrode; performing a selective etch of the pixel dielectric layer to form a via opening disposed on top of the bottom electrode and exposing the bottom electrode; forming a coupling structure disposed on top of the reflector and extending from the reflector to the bottom electrode through the via opening, wherein the coupling structure comprises a second metal; and forming a light emitting device disposed on top of the coupling structure and the reflector. In some embodiments, a native oxide of the reflector is a dielectric, whereas a native oxide of the coupling structure is electrically conductive. In some embodiments, forming the coupling structure comprises: depositing a conductive layer covering the reflector and further lining the via opening; and patterning the conductive layer. In some embodiments, forming the coupling structure comprises: depositing a first conductive layer filling the via opening; planarizing a top surface of the first conductive layer to form a via in the via opening; depositing a second conductive layer covering the reflector and the via; and patterning the second conductive layer.

[0121] The foregoing summary of the features of several embodiments has been presented with sufficient particularity by way of representative example to convey the spirit and scope of the application to those who are skilled in this art. This detailed description is not intended to limit the scope of the application to the particular embodiments described. Numerous variations, substitutions, and changes can be made by those skilled in the art without departing from the spirit and scope of the application.

Claims

1. An integrated circuit (IC) chip comprising display pixels, wherein, The display pixel includes: a bottom electrode; a reflector interfacing the bottom electrode; a light emitting device disposed above the reflector; a top electrode disposed above the light emitting device; and a coupling structure extending from the bottom electrode along a side of the reflector to an interface between the light emitting device and the reflector to electrically couple the bottom electrode to the light emitting device, wherein the coupling structure is on a single side of the reflector and is recessed to a bottom of the light emitting device such that the light emitting device wraps a top corner of the coupling structure from a sidewall of the coupling structure to a top surface of the coupling structure.

2. The integrated circuit chip of claim 1, wherein, A native oxide of the coupling structure has a smaller electrical resistance than a native oxide of the reflector.

3. The integrated circuit chip of claim 1, wherein, The coupling structure includes a via extending from the bottom electrode to a top of the reflector, and wherein the via is spaced apart from the reflector.

4. The integrated circuit chip of claim 1, wherein, The reflector has a first sidewall and a second sidewall on opposite sides of the reflector, respectively, wherein the bottom electrode extends along a bottom surface of the reflector from the first sidewall to the second sidewall.

5. The integrated circuit chip of claim 1, wherein, The reflector has a first sidewall and a second sidewall on opposite sides of the reflector, respectively, and wherein the coupling structure extends along a top surface of the reflector from the first sidewall to the second sidewall.

6. The integrated circuit chip of claim 1, wherein, The coupling structure includes: a coupling via extending from the bottom electrode to a top of the reflector along a side of the reflector; and a coupling layer disposed above the reflector and below the light emitting device, wherein the coupling layer extends laterally from the coupling via to the interface.

7. The integrated circuit chip of claim 1, further comprising: a semiconductor substrate; a semiconductor device disposed above the semiconductor and inserted into the semiconductor substrate; and an alternating stack of wires and vias disposed above the semiconductor device; wherein the display pixel is disposed above the alternating stack, and wherein the alternating stack defines a conductive path from the semiconductor device to the bottom electrode.

8. An integrated circuit (IC) chip, comprising: a semiconductor device; a bottom electrode disposed above the semiconductor device; an interconnect structure between and electrically coupled to the bottom electrode and the semiconductor device; a reflector above the interconnect structure and interfacing the bottom electrode; a light emitting device disposed above the reflector; a coupling via disposed above and electrically coupled to the bottom electrode, wherein the coupling via extends from a top to a bottom along a side of the reflector; a coupling layer extending laterally from a bottom surface of the light emitting device to the coupling via; and a dielectric layer above the bottom electrode, wherein the coupling via has a first sidewall facing the reflector and a second sidewall facing away from the reflector and on an opposite side of the coupling via from the first sidewall, and wherein the dielectric layer directly contacts the second sidewall from a top of the second sidewall to a bottom of the second sidewall. ​ 9. The integrated circuit chip of claim 8, wherein, The coupling via, the coupling layer, and the reflector are electrically conductive, and wherein the coupling via and the coupling layer are more energy dependent to be oxidized than the reflector.

10. The integrated circuit chip of claim 8, wherein, The reflector includes a metal layer and a native oxide layer on top of the metal layer, wherein the coupling layer is disposed on and directly contacts a top surface of the native oxide layer.

11. The integrated circuit chip of claim 8, wherein, The coupling via is a portion of the coupling layer having a top recess.

12. The integrated circuit chip of claim 8, wherein, The coupling via is continuous from a first side of the coupling via to a second side of the coupling via opposite the first side at a level flush with a top surface of the reflector.

13. The integrated circuit chip of claim 8, wherein, The coupling via is different from the coupling layer and is a different type of material than the coupling layer.

14. The integrated circuit chip of claim 8, wherein, The coupling layer and the reflector collectively have a rectangular top geometry, and wherein the coupling layer has a triangular top geometry at a corner of the rectangular top geometry.

15. The integrated circuit chip of claim 8, wherein, The coupling via directly contacts a sidewall of the reflector.

16. The integrated circuit chip of claim 8, wherein, The dielectric layer also directly contacts the first sidewall from a top of the first sidewall to a bottom of the first sidewall at a location between the coupling via and the reflector.

17. A method for forming an integrated circuit (IC) chip, comprising: forming a bottom electrode disposed on a semiconductor device and electrically coupled to the semiconductor device by an interconnect structure; depositing a pixel dielectric layer covering the bottom electrode; forming a reflector inserted into the pixel dielectric layer, wherein the reflector includes a first metal and is adjacent to the bottom electrode; performing a selective etch of the pixel dielectric layer to form a via opening disposed on the bottom electrode and exposing the bottom electrode; forming a coupling structure disposed on the reflector and extending from the reflector through the via opening to the bottom electrode, wherein the coupling structure includes a second metal; and forming a light emitting device disposed on the coupling structure and the reflector.

18. The method of claim 17, wherein, A native oxide of the reflector is a dielectric, whereas a native oxide of the coupling structure is electrically conductive.

19. The method of claim 17, wherein, Forming the coupling structure includes: depositing a conductive layer covering the reflector and further lining the via opening; and patterning the conductive layer.

20. The method of claim 17, wherein, Forming the coupling structure includes: depositing a first conductive layer filling the via opening; planarizing a top surface of the first conductive layer to form a via in the via opening; depositing a second conductive layer covering the reflector and the via; and patterning the second conductive layer.

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