Voltage Comparator and Its Current Limit Control Circuit

Abstract

The present application provides a voltage comparator and a current limit control circuit. Among them, the non-inverting input terminal and the inverting input terminal of the voltage comparator are respectively connected to a first triode and a second triode. A first current mirror provides a constant current power supply and is connected to the bases of the first triode and the second triode. The collector of the first triode is connected to a second current mirror. A third current mirror is a constant current power supply and is respectively connected to the emitters of the first triode and the second triode. The output terminal of the second current mirror and the output terminal of the third current mirror are connected to an inverter. The output terminal of the inverter is the output terminal of the voltage comparator. When the voltage of the non-inverting input terminal is greater than the voltage of the inverting input terminal, the current flowing through the first diode and the current at the output terminal of the second current mirror are greater than the current at the output terminal of the third current mirror, such that a high level is output from the output terminal of the second current mirror to the inverter. After the inverting action of the inverter, a low level is output from the output terminal of the voltage comparator.

Description

Technical Field

[0001] The present invention relates to the field of electricity, and more specifically, to a voltage comparator and its current limit control circuit. Background Art

[0002] A comparator, also known as a voltage comparator, has two input terminals and one output terminal. The input terminals are the non-inverting input terminal (+) and the inverting input terminal (-) respectively. Usually, the non-inverting input terminal of the voltage comparator is connected to the sampled voltage (Vcs), and the inverting input terminal is connected to the reference voltage (Vref). When the voltage at the non-inverting terminal is less than or equal to the voltage at the inverting terminal, the output terminal outputs a high level, and the power transistor connected to the output terminal of the voltage comparator remains in the conducting state; when the voltage at the non-inverting terminal is greater than the voltage at the inverting terminal, the voltage comparator jumps, and the output terminal outputs a low level, and the power transistor connected to the output terminal of the voltage comparator is controlled to turn off.

[0003] Voltage comparators are widely used. For example, in the current limit control circuit of a switching power supply system, in order to ensure the stability of the output voltage, a voltage comparator is usually connected to a power transistor. As the current of the power transistor increases and the sampled voltage rises to the reference voltage, the voltage comparator jumps and outputs a low level, causing the power transistor to turn off. In the prior art, for example, in Chinese Patent 202120952652.0, a line voltage compensation circuit is also designed at the inverting input terminal of the voltage comparator to ensure constant peak power and solve the problem that the system delay under different line voltages affects the peak current.

[0004] However, the voltage comparators in the prior art have a large offset voltage, high power consumption, and high requirements for the input voltage. Summary of the Invention

[0005] The purpose of the present invention is to provide a voltage comparator and a current limit control circuit, which can reduce the offset voltage, have low power consumption, and reduce the input voltage of the voltage comparator; and when the voltage comparator is applied to the current limit control circuit, it can adjust the bias voltage.

[0006] In the first aspect of the present application, a voltage comparator is provided, which includes a first current mirror, a second current mirror, a first triode, a second triode, and a third current mirror. The non-inverting input terminal of the voltage comparator is connected to the base of the first triode, and the inverting input terminal of the voltage comparator is connected to the base of the second triode. The first current mirror provides a constant current source and is connected to the bases of the first triode and the second triode. The collector of the first triode is connected to the second current mirror. The third current mirror is a constant current source and is connected to the emitters of the first triode and the second triode. The output terminals of the second current mirror and the third current mirror are both connected to an inverter, and the output terminal of the inverter is the output terminal (OCP_n) of the voltage comparator. When the voltage at the non-inverting input terminal is greater than the voltage at the inverting input terminal, the current flowing through the first triode and the current at the output terminal of the second current mirror are greater than the current at the output terminal of the third current mirror, such that the output terminal of the second current mirror outputs a high level to the inverter. After the inversion of the inverter, the output terminals of the inverter and the voltage comparator output a low level.

[0007] In some embodiments, the non-inverting input terminal of the voltage comparator is connected to a MOS transistor, which is then connected to the base of the first triode. This MOS transistor is a PMOS transistor; the inverting input terminal of the voltage comparator is connected to a MOS transistor, which is then connected to the base of the second triode. This MOS transistor is a PMOS transistor; these two MOS transistors can reduce the input voltage of the voltage comparator.

[0008] Further, the non-inverting input terminal of the voltage comparator is connected to the gate of MOS transistor M1. The source of MOS transistor M1 is connected to the first current mirror and the base of the first triode. The drain of MOS transistor M1 is connected to the ground wire (GND). The inverting input terminal of the voltage comparator is connected to the gate of MOS transistor M2. The source of MOS transistor M2 is connected to the first current mirror and the base of the second triode. The drain of MOS transistor M2 is connected to the ground wire (GND).

[0009] In some embodiments, the second current mirror is composed of two MOS transistors. The width-to-length ratios of the two MOS transistors are 1:1. These two MOS transistors are both PMOS transistors. One of the MOS transistors is connected to the collector of the first triode as a load. The gates of the two MOS transistors are connected to each other, and the output terminal of the other MOS transistor is connected to the inverter.

[0010] Further, the collector of the first triode is connected to the drain of MOS transistor M8. The drain of MOS transistor M8 is connected to the gate of MOS transistor M8. The source of MOS transistor M8 is connected to the power supply (VCC). The gate of MOS transistor M8 is connected to the gate of MOS transistor M13. The drain of MOS transistor M13 is connected to the inverter. The source of MOS transistor M13 is connected to the power supply (VCC).

[0011] In some embodiments, the third current mirror is composed of MOS transistor M5, MOS transistor M6, and MOS transistor M14. The output terminal of MOS transistor M14 is connected to an inverter. Switching transistor M7 is connected to MOS transistor M6 and to the emitter of the first triode. MOS transistor M5 is connected to the emitter of the second triode. MOS transistor M5, MOS transistor M6, and switching transistor M7 form a tail current source, and the current flowing through MOS transistor M14 is constant.

[0012] Furthermore, MOS transistor M5, MOS transistor M6, switching transistor M7, and MOS transistor M14 are all NMOS transistors. The gates of MOS transistor M6, MOS transistor M5, and MOS transistor M14 are connected in sequence. The width-to-length ratio of MOS transistor M6 is greater than that of MOS transistor M5. MOS transistor M5 provides a small current source, and MOS transistor M6 provides a current source larger than that of MOS transistor M5. The digital control signal TON_p is connected to switching transistor M7.

[0013] Furthermore, the width-to-length ratio W / L of MOS transistor M6 is 10 / 1, and the width-to-length ratio W / L of MOS transistor M5 is 1 / 1.

[0014] Furthermore, when the digital control signal TON_p is at a high level (the power transistor is turned on), switching transistor M7 is turned on, and the tail current source is the sum of the currents of MOS transistor M5 and MOS transistor M6, increasing the current of the tail current source. When the digital control signal TON_p is at a low level (the power transistor is turned off), switching transistor M7 is turned off, and MOS transistor M5 of the tail current source provides a small current to the voltage comparator, enabling the voltage comparator to operate at a determined DC operating point.

[0015] Furthermore, the drain of switching transistor M7 is connected to the emitter of the first triode, the gate is connected to the digital control signal TON_p, and the source is connected to the drain of MOS transistor M6. The gates of MOS transistor M6, MOS transistor M5, and MOS transistor M14 are connected in sequence. The drain of MOS transistor M5 is connected to the emitter of the second triode. The drain of MOS transistor M14 is connected to the drain of MOS transistor M13 and to the inverter. The sources of MOS transistor M6, MOS transistor M5, and MOS transistor M14 are all connected to ground (GND).

[0016] In some embodiments, the first current mirror includes MOS transistor M9 and MOS transistor M10. MOS transistor M9 is connected to MOS transistor M1 and the base of the first triode. MOS transistor M10 is connected to MOS transistor M2 and the second triode. MOS transistor M9 and MOS transistor M10 are both PMOS transistors.

[0017] Further, the gates of MOS transistor M9 and MOS transistor M10 are connected; the drain of MOS transistor M9 is connected to the source of MOS transistor M1; the drain of MOS transistor M10 is connected to the source of MOS transistor M2; the sources of MOS transistor M9 and MOS transistor M10 are both connected to the power supply (VCC).

[0018] Further, the first current mirror further includes MOS transistor M11 and MOS transistor M12. MOS transistor M11 and switching transistor M3 are connected to form a branch and are connected to the base of the first triode; MOS transistor M12 and switching transistor M4 are connected to form a branch and are connected to the base of the second triode. MOS transistor M11, MOS transistor M12, switching transistor M3, and switching transistor M4 are all PMOS transistors, and the digital control signal TON_n is connected to switching transistor M3 and switching transistor M4.

[0019] Further, when the digital control signal TON_p is at a low level (the power transistor is conducting), switching transistor M3 and switching transistor M4 are conducting, and the current of MOS transistor M11 flows through MOS transistor M1 to ensure that the DC operating point of the first triode remains unchanged (that is, the DC operating point of the first triode will not change due to the conduction of the power transistor); when the digital control signal TON_p is at a high level, switching transistor M3 and switching transistor M4 are turned off.

[0020] Further, the gates of MOS transistor M9, MOS transistor M11, MOS transistor M12, and MOS transistor M10 are connected in sequence. The drain of MOS transistor M11 is connected to the source of switching transistor M3. The gates of switching transistor M3 and switching transistor M4 are both connected to the digital control signal TON_n. The drain of switching transistor M3 is connected to the base of the first triode. The drain of MOS transistor M12 is connected to the source of switching transistor M4. The drain of switching transistor M4 is connected to the base of the second triode. The sources of MOS transistor M11 and MOS transistor M12 are both connected to the power supply (VCC); when the tail current source of the comparator increases, the current flowing through MOS transistor M1 and the voltage of the base of the first triode Q1 increase accordingly.

[0021] Further, when the power transistor is turned off, TON_p = 0, switch M7 is turned off, TON_n = 1, switch M3 is turned off, and the tail current source is MOS transistor M5. The current flowing through MOS transistor M1 is current source MOS transistor M9. When the power transistor is turned on, TON_p = 1, switch M7 is turned on, TON_n = 0, switch M3 is turned on, and the tail current sources are MOS transistors M5 and M6. The current flowing through MOS transistor M1 is current source MOS transistor M9 and current source MOS transistor M11. Therefore, when the tail current source of the comparator increases, the current flowing through the first triode Q1 increases accordingly, the base voltage of the first triode Q1 increases accordingly, and at the same time the current flowing through MOS transistor M1 also increases accordingly. Therefore, the VSG of MOS transistor M1 increases with the increase of the current, that is, the base voltage of the first triode Q1 becomes larger, matching the increase of the base voltage of the first triode Q1 when the tail current source of the comparator increases when the power transistor is turned on.

[0022] In a second aspect of the present application, a current limit control circuit with a voltage comparator is provided, including the above voltage comparator. The in-phase terminal of the voltage comparator is connected to a sampling circuit, the anti-phase terminal of the voltage comparator is connected to a current source, a line voltage compensation circuit, and a resistor R. The current source, the line voltage compensation circuit, and the resistor R form a reference voltage. The current source can adjust the output bias current I1 through an external circuit. The output terminal of the voltage comparator is connected to the gate of the power transistor, and the output signal controls the on / off of the power transistor.

[0023] In some embodiments, the bias current I1 output by the current source is adjusted through a bypass capacitor detection circuit. The current source includes: a constant current source current mirror, a fourth current mirror, and a tail power supply MOS transistor M20. The constant current source current mirror is connected to the first current mirror of the voltage comparator. MOS transistor M20 is connected to the third current source of the voltage comparator. The fourth current mirror is connected to the constant current source current mirror. The bias current I1 is the difference between the current at the output terminal of the constant current source current mirror and the current at the output terminal of the fourth current mirror. The constant current source current mirror includes two branches controlled by switch transistors. The signals CAP_H and CAP_L output by the bypass capacitor detection circuit respectively control the on / off of the two switch transistors, changing the current at the output terminal of the constant current source current mirror, thereby adjusting the output bias current I1 and realizing the function of adjusting the full-load current limit point.

[0024] Further, the gates of MOS transistors M17, M18, M19, M21, and M24 of the constant-current source current mirror are connected in sequence, and all are PMOS transistors. The source of MOS transistor M17 is connected to the drain of switch transistor M15, and the drain is connected to the gate. The gate of switch transistor M15 is connected to the input signal CAP_H, and the source of switch transistor M15 is connected to the power supply (VCC); the source of MOS transistor M18 is connected to the drain of switch transistor M16, and the drain is connected to the gate. The gate of switch transistor M16 is connected to the input signal CAP_L, and the source of switch transistor M16 is connected to the power supply VCC; the drain of MOS transistor M19 is connected to the gate and the drain of MOS transistor M20, and the source is connected to the power supply VCC. The source of MOS transistor M20 is grounded; the fourth current mirror is composed of MOS transistors M22 and M23. The gate of MOS transistor M22 is connected to the gate of MOS transistor M23, the drain is connected to the gate and the drain of MOS transistor M21, the drain of MOS transistor M23 is connected to the drain of MOS transistor M24, the sources of MOS transistors M21 and M24 are both connected to the power supply VCC, the sources of MOS transistors M22 and M23 are grounded, and MOS transistors M20, M22, and M23 are all NMOS transistors.

[0025] Further, the signals CAP_H and CAP_L control the on / off of switch transistors M15 and M16, thereby changing the operating current flowing through MOS transistor M19. The current of MOS transistor M19 is: , where I M20 , I M17 and I M18 are the currents of MOS transistors M20, M17, and M18 respectively. The width-to-length ratio of MOS transistor M17 is greater than that of MOS transistor M18. The bias current I1 is: (S1)

[0026] Where, (W / L) 24 , (W / L) 19 , (W / L) 23 , (W / L) 22 and (W / L) 21 represent the width-to-length ratios of MOS transistors M24, M19, M23, M22, and M21 respectively. The bias voltage can be changed by adjusting the width-to-length ratios of MOS transistors M19, M21, M22, and M24, and by adjusting the magnitude of the current I M19 of MOS transistor M19.

[0027] In some embodiments, the sampling circuit is composed of a sampling transistor M31 and a sampling resistor Rs. One end of the sampling resistor Rs is connected to the source of the sampling transistor M31, and the other end is grounded. The source of the sampling transistor M31 is connected to the non-inverting input terminal of the voltage comparator.

[0028] In some embodiments, the compensation current Icm output by the line voltage compensation circuit is converted into a compensation voltage Vcm through a resistor R, where Vcm = Icm * R. The bias current I1 output by the current source is converted into a bias voltage V1 through the resistor R, where V1 = I1 * R. The reference voltage VREF = V1 + Vcm. The compensation current Icm is proportional to the conduction time of the power transistor. The smaller the line voltage, the longer the conduction time of the power transistor, and the larger the compensation current Icm. The larger the reference voltage VREF, the larger the sampling voltage VCS when the voltage comparator flips, thus achieving a constant peak power.

[0029] Compared with the prior art, the present application has the following advantages:

[0030] 1. The voltage comparator of the present application uses two bipolar transistors as input pair transistors instead of MOS transistors in the prior art, which can reduce the offset voltage. The principle is that the offset voltage is caused by device mismatch. There are three factors affecting the offset voltage of the MOS transistor differential pair: mismatch of the load resistors, mismatch of W / L, and mismatch of VTH. The bipolar transistor does not have the corresponding VTH mismatch of the MOSFET. The offset voltage depends on the mismatch of the load resistors and the mismatch of the emitter junction areas. Since the transconductance of the bipolar transistor is greater than that of the MOSFET, the offset voltage caused by the mismatch of the load resistors of the bipolar transistor is less than the offset voltage caused by the mismatch of the load resistors of the MOSFET.

[0031] 2. The voltage comparator of the present application adds MOS transistors M1 and M2, which can reduce the input voltage of the voltage comparator. The principle is that before adding, the input voltage is VIN, and after adding, the input voltage is VIN - VGS1, reducing the input voltage of the voltage comparator by one VGS, approximately 0.9V.

[0032] 3. The voltage comparator of the present application uses a single MOS transistor M8 as the load instead of a current mirror and a current source as the load in the prior art, which can further reduce the offset voltage. The principle is that both the current mirror structure and the current source structure as loads will generate offset voltages due to the mismatch of W / L and VTH. However, when using a single MOS transistor M8, there is no need to consider the problem of offset voltage generated by mismatch.

[0033] 4. The voltage comparator of the present application has a tail current source design that can reduce the power consumption of the voltage comparator. The principle is that when the power transistor is turned on, the voltage comparator operates. At this time, MOS transistors M5 - M7 are turned on, and when it is detected that the current of the power transistor rises to the peak value, the voltage comparator flips, thereby turning off the power transistor. When the power transistor is turned off, there is no current on the power transistor, and there is no need for the voltage comparator to operate. To reduce power consumption, the current source M6 stops working by turning off the switching transistor M7, and only the small - sized MOS transistor M5 is used to provide a tiny current to maintain the DC operating point of the voltage comparator.

[0034] 5. The voltage comparator of the present application has two control branches in its constant - current source design, namely the M11, M3 branch and the M12, M4 branch. When the tail current source of the comparator increases, the current flowing through MOS transistor M1 and the voltage at the base of the first triode Q1 increase accordingly.

[0035] 6. When the voltage comparator of the present application is applied to a current - limit control circuit, it can ensure the stability of the voltage output by the switching power supply. Moreover, the current source of this current - limit control circuit can adjust the output bias current I1 through a bypass - capacitor detection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] When reading in conjunction with the following attached Figure 1 drawings, the above and other features of the present application will be more fully described. It can be understood that these drawings only depict several embodiments of the present application, so they should not be considered as limiting the scope of the present application. By using the drawings, the present application will be more clearly and detailedly explained.

[0037] Figure 1 is the circuit diagram of the voltage comparator of the present application.

[0038] Figure 2 is the circuit diagram of the current - limit control circuit of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0039] The following embodiments are described to assist in understanding the present application. The embodiments are not and should not be construed in any way as limiting the scope of protection of the present application.

[0040] In the following description, those skilled in the art will recognize that throughout this discussion, components may be described as separate functional units (which may include sub - units), but those skilled in the art will recognize that various components or parts thereof may be divided into separate components or integrated together (including being integrated within a single system or component).

[0041] At the same time, the connections between components or systems are not intended to be limited to direct connections. Instead, the data between these components can be modified, reformatted, or otherwise changed by intermediate components. Additionally, additional or fewer connections may be used. It should also be noted that the terms "coupled", "connected", or "input" should be understood to include direct connections, indirect connections through one or more intermediate devices, and wireless connections. Embodiment

[0042] A voltage comparator, such as Figure 1 shown, includes a first current mirror, a second current mirror, a first triode Q1, a second triode Q2, and a third current mirror. The non-inverting input terminal of the voltage comparator is connected to the base of the first triode Q1, and the inverting input terminal of the voltage comparator is connected to the base of the second triode Q2. The first current mirror provides a constant current source and is connected to the bases of the first triode Q1 and the second triode Q2. The collector of the first triode Q1 is connected to the second current mirror. The third current mirror is a constant current source and is connected to the emitters of the first triode Q1 and the second triode Q2. The output terminals of the second current mirror and the third current mirror are both connected to an inverter. The output terminal of the inverter is the output terminal (OCP_n) of the voltage comparator. When the voltage at the non-inverting input terminal is greater than the voltage at the inverting input terminal, the current flowing through the first triode and the current at the output terminal of the second current mirror are greater than the current at the output terminal of the third current mirror, causing the output terminal of the second current mirror to output a high level to the inverter. After the inversion by the inverter, the output terminals of the inverter and the voltage comparator output a low level. Using two triodes as input pair transistors instead of MOS transistors in the prior art can reduce the offset voltage. The principle is that the offset voltage is caused by device mismatches. There are three factors affecting the offset voltage of a MOS transistor differential pair: mismatch of load resistors, mismatch of W / L, and mismatch of VTH. Bipolar transistors do not have the corresponding VTH mismatch of MOSFETs. The offset voltage depends on the mismatch of load resistors and the mismatch of emitter junction areas. Since the transconductance of bipolar transistors is greater than that of MOSFETs, the offset voltage caused by the mismatch of load resistors of bipolar transistors is less than the offset voltage caused by the mismatch of load resistors of MOSFETs.

[0043] The non-inverting input terminal of the voltage comparator is connected to MOS transistor M1, and MOS transistor M1 is further connected to the base of the first triode Q1. The inverting input terminal of the voltage comparator is connected to MOS transistor M2, and MOS transistor M2 is further connected to the base of the second triode Q2. MOS transistors M1 and M2 can reduce the input voltage of the voltage comparator, and both MOS transistors M1 and M2 are PMOS transistors. The non-inverting input terminal of the voltage comparator is connected to the gate of MOS transistor M1, the source of MOS transistor M1 is connected to the first current mirror and the base of the first triode Q1, and the drain of MOS transistor M1 is connected to the ground wire (GND). The inverting input terminal of the voltage comparator is connected to the gate of MOS transistor M2, the source of MOS transistor M2 is connected to the first current mirror and the base of the second triode Q2, and the drain of MOS transistor M2 is connected to the ground wire (GND). The addition of MOS transistors M1 and M2 can reduce the input voltage of the voltage comparator. The principle is that before the addition, the input voltage is VIN, and after the addition, the input voltage is VIN - VGS1, reducing the input voltage of the voltage comparator by one VGS, approximately 0.9V.

[0044] The second current mirror is composed of MOS transistor M8 and MOS transistor M13. Both MOS transistor M8 and MOS transistor M13 are PMOS transistors. The width-to-length ratio of MOS transistor M8 to MOS transistor M13 is 1:1. MOS transistor M8 is connected to the first triode Q1 and serves as a load, and the output terminal of MOS transistor M13 is connected to an inverter. The collector of the first triode Q1 is connected to the drain of MOS transistor M8. The drain of MOS transistor M8 is connected to the gate of MOS transistor M8. The source of MOS transistor M8 is connected to the power supply (VCC). The gate of MOS transistor M8 is connected to the gate of MOS transistor M13. The drain of MOS transistor M13 is connected to the inverter, and the source of MOS transistor M13 is connected to the power supply (VCC). Using a single MOS transistor M8 as the load instead of the current mirror and current source in the prior art as the load can further reduce the offset voltage. The principle is that using the current mirror structure and current source structure as the load will generate offset voltage due to the mismatch of W / L and VTH, but using a single MOS transistor M8, there is no need to consider the problem of offset voltage generated by mismatch.

[0045] The third current mirror is composed of MOS transistor M5, MOS transistor M6, and MOS transistor M14. The output terminal of MOS transistor M14 is connected to an inverter. Switching transistor M7 is connected to MOS transistor M6 and is also connected to the emitter of the first triode Q1. MOS transistor M5 is connected to the emitter of the second triode Q2. MOS transistor M5, MOS transistor M6, and switching transistor M7 form a tail current source, and the current flowing through MOS transistor M14 is constant. MOS transistor M5, MOS transistor M6, switching transistor M7, and MOS transistor M14 are all NMOS transistors. The gates of MOS transistor M6, MOS transistor M5, and MOS transistor M14 are connected in sequence. The width-to-length ratio of MOS transistor M6 is greater than that of MOS transistor M5. MOS transistor M5 provides a small current source, and MOS transistor M6 provides a larger current source than MOS transistor M5. The digital control signal TON_p is connected to switching transistor M7. The width-to-length ratio W / L of MOS transistor M6 is 10 / 1, and the width-to-length ratio W / L of MOS transistor M5 is 1 / 1. When the digital control signal TON_p is at a high level (the power transistor is conducting), switching transistor M7 conducts, and the tail current source is the sum of the currents of MOS transistor M5 and MOS transistor M6, increasing the current of the tail current source. When the digital control signal TON_p is at a low level (the power transistor is cutoff), switching transistor M7 turns off, and the tail current source MOS transistor M5 provides a small current for the voltage comparator, enabling the voltage comparator to operate at a determined DC operating point. The drain of switching transistor M7 is connected to the emitter of the first triode Q1, the gate is connected to the digital control signal TON_p, and the source is connected to the drain of MOS transistor M6. The gates of MOS transistor M6, MOS transistor M5, and MOS transistor M14 are connected in sequence. The drain of MOS transistor M5 is connected to the emitter of the second triode Q2. The drain of MOS transistor M14 is connected to the drain of MOS transistor M13 and the inverter. The sources of MOS transistor M6, MOS transistor M5, and MOS transistor M14 are all connected to the ground wire (GND). The design of the tail current source can reduce the power consumption of the voltage comparator. The principle is that when the power transistor conducts, the voltage comparator operates. At this time, MOS transistors M5 - M7 conduct. When the current of the power transistor rises to the peak value, the voltage comparator flips, thereby turning off the power transistor. When the power transistor is cutoff, there is no current on the power transistor, and there is no need for the voltage comparator to operate. To reduce power consumption, the current source M6 stops working by turning off switching transistor M7, and only the small-sized MOS transistor M5 is used to provide a tiny current to maintain the DC operating point of the voltage comparator.

[0046] The first current mirror includes MOS transistor M9 and MOS transistor M10. MOS transistor M9 is connected to MOS transistor M1 and the first triode Q1, and MOS transistor M10 is connected to MOS transistor M2 and the second triode Q2. Both MOS transistor M9 and MOS transistor M10 are PMOS transistors. The gates of MOS transistor M9 and MOS transistor M10 are connected. The drain of MOS transistor M9 is connected to the source of MOS transistor M1, and the drain of MOS transistor M10 is connected to the source of MOS transistor M2. The sources of MOS transistor M9 and MOS transistor M10 are both connected to the power supply (VCC). The first current mirror further includes MOS transistor M11 and MOS transistor M12. MOS transistor M11 and the switching transistor M3 are connected to form a branch and are connected to the base of the first triode Q1. MOS transistor M12 and the switching transistor M4 are connected to form a branch and are connected to the base of the second triode Q2. MOS transistor M11, MOS transistor M12, switching transistor M3, and switching transistor M4 are all PMOS transistors. The digital control signal TON_n is connected to the switching transistor M3 and the switching transistor M4. When the digital control signal TON_p is at a low level (the power transistor is conducting), the switching transistor M3 and the switching transistor M4 are conducting, and the current of MOS transistor M11 flows through MOS transistor M1 to ensure that the DC operating point of the first triode Q1 remains unchanged (that is, the DC operating point of the first triode Q1 will not change due to the conduction of the power transistor). When the digital control signal TON_p is at a high level, the switching transistor M3 and the switching transistor M4 are turned off. The gates of MOS transistor M9, MOS transistor M11, MOS transistor M12, and MOS transistor M10 are connected in sequence. The drain of MOS transistor M11 is connected to the source of the switching transistor M3. The gates of the switching transistor M3 and the switching transistor M4 are both connected to the digital control signal TON_n. The drain of the switching transistor M3 is connected to the base of the first triode Q1. The drain of MOS transistor M12 is connected to the source of the switching transistor M4. The drain of the switching transistor M4 is connected to the base of the second triode Q2. The sources of MOS transistor M11 and MOS transistor M12 are both connected to the power supply (VCC). The constant current source is designed with two control branches, namely the M11, M3 branch and the M12, M4 branch. When the tail current source of the comparator increases, the current flowing through MOS transistor M1 and the voltage at the base of the first triode Q1 increase accordingly.When the power transistor is turned off, TON_p = 0, switch M7 is turned off, TON_n = 1, switch M3 is turned off, the tail current source is MOS transistor M5, and the current flowing through MOS transistor M1 is current source MOS transistor M9; when the power transistor is turned on, TON_p = 1, switch M7 is turned on, TON_n = 0, switch M3 is turned on, the tail current sources are MOS transistors M5 and M6, and the current flowing through MOS transistor M1 is current source MOS transistor M9 and current source MOS transistor M11. Therefore, when the tail current source of the comparator increases, the current flowing through the first triode Q1 increases accordingly, the base voltage of the first triode Q1 increases accordingly, and at the same time the current flowing through MOS transistor M1 also increases accordingly. Therefore, the VSG of MOS transistor M1 increases with the increase of the current, that is, the base voltage of the first triode Q1 becomes larger, matching the increase of the base voltage of the first triode Q1 when the tail current source of the comparator increases when the power transistor is turned on. Embodiment

[0047] A current limit control circuit with a voltage comparator, as Figure 2 described, Figure 1 The voltage comparator is applied to the current limit control circuit. The in-phase terminal of the voltage comparator is connected to the sampling circuit, the anti-phase terminal of the voltage comparator is connected to the current source, the line voltage compensation circuit and the resistor R. The current source, the line voltage compensation circuit and the resistor R form a reference voltage. The current source can adjust the output bias current I1 through an external circuit. The output terminal of the voltage comparator is connected to the gate of the power transistor, and the output signal controls the on / off of the power transistor. The bias current I1 output by the current source is adjusted through the bypass capacitor detection circuit. The current source includes: a constant current source current mirror, a fourth current mirror and a tail power MOS transistor M20. The constant current source current mirror is connected to the first current mirror of the voltage comparator. MOS transistor M20 is connected to the third current source of the voltage comparator. The fourth current mirror is connected to the constant current source current mirror. The bias current I1 is the difference between the currents at the output terminals of the constant current source current mirror and the fourth current mirror. The constant current source current mirror includes two branches controlled by switch transistors. The signals CAP_H and CAP_L output by the bypass capacitor detection circuit respectively control the on / off of the two switch transistors, changing the current at the output terminal of the constant current source current mirror, thereby adjusting the output bias current I1 and realizing the function of adjusting the full-load current limit point.

[0048] The gates of MOS transistors M17, M18, M19, M21, and M24 of the constant current source current mirror are connected in sequence, and all are PMOS transistors. The source of MOS transistor M17 is connected to the drain of switch transistor M15, and the drain is connected to the gate. The gate of switch transistor M15 is connected to the input signal CAP_H, and the source of switch transistor M15 is connected to the power supply (VCC); the source of MOS transistor M18 is connected to the drain of switch transistor M16, and the drain is connected to the gate. The gate of switch transistor M16 is connected to the input signal CAP_L, and the source of switch transistor M16 is connected to the power supply VCC; the drain of MOS transistor M19 is connected to the gate and the drain of MOS transistor M20, and the source is connected to the power supply VCC. The source of MOS transistor M20 is grounded; the fourth current mirror is composed of MOS transistors M22 and M23. The gate of MOS transistor M22 is connected to the gate of MOS transistor M23, the drain is connected to the gate and the drain of MOS transistor M21, the drain of MOS transistor M23 is connected to the drain of MOS transistor M24, the sources of MOS transistors M21 and M24 are both connected to the power supply VCC, and the sources of MOS transistors M22 and M23 are grounded. MOS transistors M20, M22, and M23 are all NMOS transistors. The signals CAP_H and CAP_L control the on / off of switch transistors M15 and M16, thereby changing the operating current flowing through MOS transistor M19. The current of MOS transistor M19 is: , where, I M20 , I M17 and I M18 are the currents of MOS transistors M20, M17, and M18 respectively. The width-to-length ratio of MOS transistor M17 is greater than that of MOS transistor M18. The bias current I1 is: (S1)

[0049] where, (W / L) 24 , (W / L) 19 , (W / L) 23 , (W / L) 22 and (W / L) 21 represent the width-to-length ratios of MOS transistors M24, M19, M23, M22, and M21 respectively. The bias voltage can be changed by adjusting the width-to-length ratios of MOS transistors M19, M21, M22, and M24, and by adjusting the magnitude of the current I M19 of MOS transistor M19.

[0050] The sampling circuit consists of a sampling transistor M31 and a sampling resistor Rs. One end of the sampling resistor Rs is connected to the source electrode of the sampling transistor M31, and the other end is grounded. The source electrode of the sampling transistor M31 is connected to the non-inverting input terminal of the voltage comparator. The compensation current Icm output by the line voltage compensation circuit is converted into a compensation voltage Vcm through a resistor R, where Vcm = Icm * R. The bias current I1 output by the current source is converted into a bias voltage V1 through a resistor R, where V1 = I1 * R. The reference voltage VREF = V1 + Vcm. The compensation current Icm is proportional to the conduction time of the power transistor. The smaller the line voltage, the longer the conduction time of the power transistor, and the larger the compensation current Icm. The larger the reference voltage VREF, the larger the sampling voltage VCS when the voltage comparator flips, thereby achieving a constant peak power.

[0051] Although the present application has disclosed multiple aspects and embodiments, other aspects and embodiments will be obvious to those skilled in the art. Without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. The multiple aspects and embodiments disclosed in the present application are only for illustrative purposes and are not intended to limit the present application. The actual protection scope of the present application is subject to the claims.

Claims

1. A voltage comparator, characterized in that, It includes a first current mirror, a second current mirror, a first triode, a second triode and a third current mirror. The non-inverting input terminal of the voltage comparator is connected to the base of the first triode, and the inverting input terminal of the voltage comparator is connected to the base of the second triode. The first current mirror provides a constant current source and is connected to the bases of the first triode and the second triode. The collector of the first triode is connected to the second current mirror. The third current mirror is a constant current source and is connected to the emitters of the first triode and the second triode. The output terminals of the second current mirror and the third current mirror are both connected to an inverter. The output terminal of the inverter is the output terminal (OCP_n) of the voltage comparator. When the voltage at the non-inverting input terminal is greater than the voltage at the inverting input terminal, the current flowing through the first triode and the current at the output terminal of the second current mirror are greater than the current at the output terminal of the third current mirror, causing the output terminal of the second current mirror to output a high level to the inverter. After the inversion of the inverter, the output terminals of the inverter and the voltage comparator output a low level. The non-inverting input terminal of the voltage comparator is connected to a MOS transistor, and this MOS transistor is then connected to the base of the first triode. This MOS transistor is a PMOS transistor. The inverting input terminal of the voltage comparator is connected to a MOS transistor, and this MOS transistor is then connected to the base of the second triode. This MOS transistor is a PMOS transistor. These two MOS transistors can reduce the input voltage of the voltage comparator. The second current mirror consists of two MOS transistors, and the aspect ratios of the two MOS transistors are 1:

1. Both of these MOS transistors are PMOS transistors. One of the MOS transistors is connected to the collector of the first triode as a load, and the gates of the two MOS transistors are connected to each other. The output terminal of the other MOS transistor is connected to the inverter. The non-inverting input terminal of the voltage comparator is connected to the gate of MOS transistor M1. The source of MOS transistor M1 is connected to the first current mirror and the base of the first triode. The drain of MOS transistor M1 is connected to the ground wire GND. The inverting input terminal of the voltage comparator is connected to the gate of MOS transistor M2. The source of MOS transistor M2 is connected to the first current mirror and the base of the second triode. The drain of MOS transistor M2 is connected to the ground wire GND;The collector of the first triode is connected to the drain of MOS transistor M8. The drain of MOS transistor M8 is connected to the gate of MOS transistor M8. The source of MOS transistor M8 is connected to power supply VCC. The gate of MOS transistor M8 is connected to the gate of MOS transistor M13. The drain of MOS transistor M13 is connected to an inverter. The source of MOS transistor M13 is connected to power supply VCC. The third current mirror is composed of MOS transistors M5, M6, and M14. The output terminal of MOS transistor M14 is connected to the inverter. Switching transistor M7 is connected to MOS transistor M6 and is also connected to the emitter of the first triode. MOS transistor M5 is connected to the emitter of the second triode. MOS transistors M5, M6, and switching transistor M7 form a tail current source. The current flowing through MOS transistor M14 is constant. The first current mirror includes MOS transistors M9 and M10. MOS transistor M9 is connected to MOS transistor M1 and the base of the first triode. MOS transistor M10 is connected to MOS transistor M2 and the second triode. Both MOS transistors M9 and M10 are PMOS transistors. The first current mirror further includes MOS transistors M11 and M12. MOS transistor M11 is connected to switching transistor M3 to form a branch and is also connected to the base of the first triode. MOS transistor M12 is connected to switching transistor M4 to form a branch and is also connected to the base of the second triode. MOS transistors M11, M12, switching transistors M3, and M4 are all PMOS transistors. The digital control signal TON_n is connected to switching transistors M3 and M4.

2. The voltage comparator according to claim 1, wherein MOS transistors M5, M6, switching transistor M7, and MOS transistor M14 are all NMOS transistors. The gates of MOS transistor M6, MOS transistor M5, and MOS transistor M14 are connected in sequence. The width-to-length ratio of MOS transistor M6 is greater than that of MOS transistor M5. MOS transistor M5 provides a small current source, and MOS transistor M6 provides a larger current source than MOS transistor M5. The digital control signal TON_p is connected to switching transistor M7. When the digital control signal TON_p is at a high level, switching transistor M7 conducts, and the tail current source is the sum of the currents of MOS transistor M5 and MOS transistor M6, increasing the current of the tail current source. When the digital control signal TON_p is at a low level, switching transistor M7 turns off, and the tail current source MOS transistor M5 provides a small current to the voltage comparator, enabling the voltage comparator to operate at a determined DC operating point.

3. The voltage comparator according to claim 1, characterized in that, When the digital control signal TON_p is at a low level, switching transistors M3 and M4 conduct, and the current of MOS transistor M11 flows through MOS transistor M1, ensuring that the DC operating point of the first triode remains unchanged. When the digital control signal TON_p is at a high level, switching transistors M3 and M4 turn off. When the tail current source of the comparator increases, the current flowing through MOS transistor M1 and the voltage at the base of the first triode Q1 increase accordingly.

4. A current limit control circuit with a voltage comparator, characterized in that, It includes the voltage comparator according to any one of claims 1 - 3. The non-inverting terminal of the voltage comparator is connected to a sampling circuit, and the inverting terminal of the voltage comparator is connected to a current source, a line voltage compensation circuit, and a resistor R. The current source, the line voltage compensation circuit, and the resistor R form a reference voltage. The current source can adjust the output bias current I1 through an external circuit. The output terminal of the voltage comparator is connected to the gate of a power transistor, and the output signal controls the on / off of the power transistor.

5. The current limit control circuit with a voltage comparator as claimed in claim 4, wherein The bias current I1 output by the current source is adjusted through a bypass capacitor detection circuit. The current source includes: a constant current source current mirror, a fourth current mirror, and tail power supply MOS transistor M20. The constant current source current mirror is connected to the first current mirror of the voltage comparator. MOS transistor M20 is connected to the third current source of the voltage comparator. The fourth current mirror is connected to the constant current source current mirror. The bias current I1 is the difference between the currents at the output terminals of the constant current source current mirror and the fourth current mirror. The constant current source current mirror includes two branches controlled by switching transistors. The signals CAP_H and CAP_L output by the bypass capacitor detection circuit respectively control the on / off of the two switching transistors, changing the current at the output terminal of the constant current source current mirror, thereby adjusting the output bias current I1 and realizing the function of adjusting the full-load current limit point.

6. The current limit control circuit with a voltage comparator as claimed in claim 5, wherein The gates of MOS transistors M17, M18, M19, M21, and M24 of the constant-current source current mirror are connected in sequence and are all PMOS transistors. The source of MOS transistor M17 is connected to the drain of switch transistor M15, and the drain is connected to the gate. The gate of switch transistor M15 is connected to the input signal CAP_H, and the source of switch transistor M15 is connected to the power supply VCC; the source of MOS transistor M18 is connected to the drain of switch transistor M16, and the drain is connected to the gate. The gate of switch transistor M16 is connected to the input signal CAP_L, and the source of switch transistor M16 is connected to the power supply VCC; the drain of MOS transistor M19 is connected to the gate and the drain of MOS transistor M20, and the source is connected to the power supply VCC. The source of MOS transistor M20 is grounded; the fourth current mirror is composed of MOS transistors M22 and M23. The gate of MOS transistor M22 is connected to the gate of MOS transistor M23, and the drain is connected to the gate and the drain of MOS transistor M21. The drain of MOS transistor M23 is connected to the drain of MOS transistor M24. The sources of MOS transistors M21 and M24 are both connected to the power supply VCC, and the sources of MOS transistors M22 and M23 are grounded. MOS transistors M20, M22, and M23 are all NMOS transistors; the signals CAP_H and CAP_L control the on / off of switch transistors M15 and M16, thereby changing the operating current flowing through MOS transistor M19. The current of MOS transistor M19 is: wherein, I M20 , I M17 and I M18 are the currents of MOS transistors M20, M17, and M18 respectively. The width-to-length ratio of MOS transistor M17 is greater than that of MOS transistor M18. The bias current I1 is: (S1) Among them, (W / L) 24 , (W / L) 19 , (W / L) 23 , (W / L) 22 and (W / L) 21 respectively represent the aspect ratios of MOS transistors M24, M19, M23, M22, and M21. The bias voltage can be changed by adjusting the aspect ratios of MOS transistors M19, M21, M22, and M24, and by adjusting the magnitude of the current I M19 of MOS transistor M19.

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