Voltage converter and class-d amplifier

Abstract

A voltage converter and a class-D amplifier. The voltage converter includes an output circuit, an error amplifier, and a charge control circuit. The output circuit includes an output capacitor. The charge control circuit includes a detection circuit to detect an output voltage of the output capacitor to generate a detection signal, and a power limiting circuit to clamp an output voltage of the error amplifier to a specific range according to the detection signal. The charge circuit generates a charge signal to the output circuit according to the output voltage of the error amplifier to charge the output capacitor.

Description

Technical Field

[0001] This invention relates to voltage converters and Class D amplifiers, and particularly to voltage converters and Class D amplifiers that can compensate for leakage current of the output capacitor without causing loop malfunctions. Background Technology

[0002] Known voltage converters may include an output circuit (bootstrap circuit) with an output capacitor. However, during operation, the voltage across the output capacitor may drop due to the consumption of the pre-driver. This can cause the output circuit to malfunction, for example, resulting in a loop anomaly. Summary of the Invention

[0003] Therefore, one objective of this invention is to provide a voltage converter that does not cause circuit abnormalities when compensating for leakage current of the output capacitor.

[0004] Another objective of this invention is to provide a Class D amplifier that does not cause circuit abnormalities when compensating for leakage current of the output capacitor.

[0005] One embodiment of the present invention discloses a voltage converter, comprising an output circuit, an error amplifier, and a charging control circuit. The output circuit includes an output capacitor. The charging control circuit includes: a detection circuit for detecting an output voltage of the output capacitor to generate a detection signal; and a power limiting circuit for clamping an output voltage of the error amplifier within a specific range based on the detection signal. The charging circuit generates a charging signal to the output circuit based on the output voltage of the error amplifier to charge the output capacitor.

[0006] One embodiment of the present invention discloses a Class D amplifier, comprising an output circuit, an error amplifier, and a charging control circuit. The output circuit includes an output capacitor. The charging control circuit includes: a detection circuit for detecting an output voltage of the output capacitor to generate a detection signal; and a power limiting circuit for clamping an output voltage of the error amplifier within a specific range based on the detection signal. The charging circuit generates a charging signal to the output circuit based on the output voltage of the error amplifier to charge the output capacitor.

[0007] According to the foregoing embodiments, the voltage converter provided by the present invention can compensate for leakage current problems without directly pulling down the output voltage, thereby compensating for leakage current of the output capacitor while avoiding circuit abnormalities. Attached Figure Description

[0008] Figure 1 A block diagram of a voltage converter according to an embodiment of the present invention is shown.

[0009] Figure 2 An illustration is provided according to an embodiment of the present invention. Figure 1 The circuit diagram shows the detailed structure of the voltage converter.

[0010] Figure 3 An illustration is provided according to an embodiment of the present invention. Figure 1 and Figure 2 The circuit diagram shown is a detailed representation of the output circuit.

[0011] Figure 4 An illustration is provided according to an embodiment of the present invention. Figure 1 and Figure 2 The circuit diagram shows the detailed structure of the detection circuit.

[0012] Figure 5 and Figure 6 An illustration is provided according to an embodiment of the present invention. Figure 1 and Figure 2 The circuit shown is a schematic diagram of its operation.

[0013] [Symbol Explanation]

[0014] 100 Voltage Converter

[0015] 101 Error Amplifier

[0016] 103 Charging Control Circuit

[0017] 105 Charging Circuit

[0018] 107 Detection Circuit

[0019] 109 Power Limiting Circuit

[0020] 401 Logic Circuit

[0021] BC_1 and BC_2 bootstrap circuits

[0022] C_1 Output capacitor

[0023] Capacitors C_1a and C_2a

[0024] CC_1, CC_2 conversion circuit

[0025] CM_1, CM_2 comparators

[0026] DA_1, DA_2 differential amplifiers

[0027] Resistors R_1i, R_2i, R_1f, R_2f

[0028] OP_1 operational amplifier

[0029] SD Schottky diode

[0030] Pr_1a, Pr_1b, Pr_1c, Pr_2a, Pr_2b Pre-drivers

[0031] SW_1, SW_2 switches Detailed Implementation

[0032] The present invention will be described below with reference to several embodiments. Please note that the terms "first," "second," and similar descriptions used in the following description are only used to define different elements, parameters, data, signals, or steps, and are not intended to limit their order.

[0033] Figure 1 A block diagram of a voltage converter according to an embodiment of the present invention is shown. Figure 1 As shown, the voltage converter 100 includes an error amplifier 101, a charging control circuit 103, a charging circuit 105, and bootstrap circuits BC_1 and BC_2. The charging control circuit 103 also includes a detection circuit 107 and a power limiting circuit 109. Note that in the following embodiment, the voltage converter 100 is a differential input / output circuit, and therefore has two bootstrap circuits BC_1 and BC_2. However, the voltage converter 100 can be a single input / output circuit. In this case, the voltage converter 100 can have only one bootstrap circuit, and other circuit structures can be changed accordingly. Furthermore, in the following description, for ease of explanation, only the operation of one path of the voltage converter 100 is illustrated.

[0034] The bootstrap circuit BC_1 includes an output capacitor ( Figure 1 (Not shown in the diagram). Detection circuit 107 detects the output voltage V_c1 of the output capacitor to generate a detection signal DS. Power limiting circuit 103 clamps the output voltage V_e1 of error amplifier 101 to a specific range based on the detection signal DS. In one embodiment, the specific range is a specific voltage level. Charging circuit 105 generates a charging signal CS_1 based on the output voltage V_e1 to charge the output capacitor. In one embodiment, power limiting circuit 109 clamps the output voltage V_e1 to a specific range, causing charging circuit 105 to increase the frequency of charging the output capacitor, thereby increasing the voltage of the output capacitor.

[0035] In one embodiment, the voltage converter 100 can be used as a Class D amplifier. In this case, the boot circuit BC_1 can be considered as an output circuit.

[0036] The following description depicts the detailed circuitry of the voltage converter 100. It should also be understood that these circuits are merely illustrative and do not constitute a limitation on the scope of the invention. Any circuit with the same function should also fall within the scope of this invention.

[0037] Figure 2 An illustration is provided according to an embodiment of the present invention. Figure 1 The circuit diagram shows the detailed structure of the voltage converter. (See attached diagram.) Figure 2 As shown, the error amplifier 101 includes resistors R_1i and R_2i, capacitors C_1a and C_2a, and operational amplifier OP_1. Furthermore, the charging circuit 105 is a PWM circuit including comparators CM_1 and CM_2, which respectively include a negative input terminal for receiving the triangular wave signal Tr and a positive input terminal for receiving the output from the output voltage V_e1. Additionally, the power limiting circuit 109 includes a differential amplifier DA_1, which includes: a first input terminal for receiving the output voltage V_e1; a second input terminal for receiving a reference voltage RV (i.e., the aforementioned specific voltage level); a first output terminal for generating a first power limiting signal P_1 based on the output voltage V_e1 and the reference voltage RV; and a second output terminal for generating a second power limiting signal P_2 based on the output voltage V_e1 and the reference voltage RV. The error amplifier 101 receives the first power limiting signal P_1 and the second power limiting signal P_2 to generate the output voltage V_e1. In one embodiment, the negative input terminal of operational amplifier OP_1 receives a second power limit signal P_2, and the positive input terminal of operational amplifier OP_1 receives a first power limit signal P_1.

[0038] Figure 3 An illustration is provided according to an embodiment of the present invention. Figure 1 and Figure 2 The circuit diagram shows the detailed structure of the output circuit. Additionally, Figure 4 An illustration is provided according to an embodiment of the present invention. Figure 1 and Figure 2 The circuit diagram showing the detailed structure of the detection circuit is illustrated. For a clearer understanding of the invention, please also refer to... Figure 2 and Figure 3 or Figure 4 .

[0039] like Figure 3 As shown, the bootstrap circuit BC_1 includes an output capacitor C_1 (i.e., the aforementioned output capacitor), switches SW_1 and SW_2, pre-drivers Pr_1a, Pr_1b, Pr_1c, Pr_2a, Pr_2b, and a Schottky diode SD. The bootstrap circuit BC_1 operates at the operating voltage V_op and receives a charging signal CS_1 to control switches SW_1 and SW_2 to be turned on (i.e., conducting) or off (i.e., not conducting). Switch SW_1 and pre-drivers Pr_1a, Pr_1b, and Pr_1c form the upper bridge path. Furthermore, switch SW_2 and pre-drivers Pr_2a and Pr_2b form the lower bridge path. As mentioned above, the charging signal CS_1 can be a PWM signal. Therefore, in Figure 3 In this embodiment, if the charging signal CS_1 has a low logic value, the lower bridge path is enabled (i.e., switch SW_2 is enabled) and the upper bridge path is disabled (i.e., switch SW_1 is disabled) to charge the output capacitor C_1. Conversely, if the charging signal CS_1 has a high logic value, the upper bridge path is enabled and the lower bridge path is disabled, causing the output capacitor C_1 to not be charged and Vp_1 to be boosted. When the output capacitor C_1 is charging, it may leak current, so its voltage may drop.

[0040] Please refer to Figure 4 The detection circuit 107 includes a comparator CM_d, which is used to compare the voltage across the output capacitor C_1 (i.e., Figure 3 The output voltages V_c1 and V_p1 in the comparator, and the difference threshold voltage V_dt. Furthermore, the detection circuit 107 includes logic circuitry 401 (e.g., an OR gate) for generating a detection signal DS based on the output of the comparator CM_d. More specifically, Figure 4 The detection circuit 107 includes a conversion circuit CC_1, which converts the voltage difference across the output capacitor C_1 into a current. The resistor R_x then generates a voltage difference based on the current. It should also be understood that the detection circuit 107 is not limited to comparing the voltage across the output capacitor C_1 to detect leakage. For example, the detection circuit 107 can compare the output voltage V_c1 with a standard voltage, and determine that the output capacitor C_1 has leakage when the output voltage V_c1 is less than the standard voltage.

[0041] Figure 5 and Figure 6 An illustration is provided according to an embodiment of the present invention. Figure 1 and Figure 2 The circuit shown is a schematic diagram of its operation. Figure 5 The diagram illustrates the relationship between the voltage V_c1 across capacitor C_1, the charging signal CS_1, and the charging current I_c. (Example) Figure 5As shown, when the voltage V_c1 across capacitor C_1 is greater than the threshold voltage V_th and the output capacitor C_1 is not charged, the voltage converter 100 operates in normal mode. Additionally, the charging signal CS_1, which is the PWM signal, has a high duty cycle (100% in this case) in normal mode. Furthermore, when the voltage V_c1 across capacitor C_1 is less than the threshold voltage V_th, the voltage converter 100 enters compensation mode. In compensation mode, the charging signal CS_1 has a low duty cycle. When the charging signal CS_1 has a low logic value, the output capacitor C_1 is charged with a charging current I_c. Therefore, the voltage V_c1 across capacitor C_1 gradually increases in compensation mode until it exceeds the threshold voltage V_th. In one embodiment, the threshold voltage V_th is set to 0.5*V_op.

[0042] Figure 6 The diagram illustrates the relationship between the voltage V_c1 across capacitor C_1, the charging signal CS_1, the detection signal DS, and the output voltage V_e1 of error amplifier 101. (For example...) Figure 6 As shown, in normal mode, the voltage V_c1 across capacitor C_1 is greater than the threshold voltage V_th, therefore the duty cycle of the charging signal CS_1 is high, while the logic value of the detection signal DS is low. Furthermore, in normal mode, the output voltage V_e1 of the error amplifier 101 is not suppressed. However, if the voltage V_c1 across capacitor C_1 is less than the threshold voltage V_th, the voltage converter 100 enters compensation mode. In compensation mode, the charging signal CS_1 has a lower duty cycle, while the detection signal DS has a high logic value. Moreover, in compensation mode, the output voltage V_e1 of the error amplifier 101 is suppressed to a specific voltage level V_sp to reduce the duty cycle of the charging signal CS_1.

[0043] In one embodiment, a specific voltage level V_sp is determined by the following formula:

[0044]

[0045] V_Ltri is the bottom voltage of the triangular wave signal Tr, which the charging circuit 105 uses to generate the PWM signal. Additionally, V_Htri is the upper voltage of the triangular wave signal Tr. Furthermore, in compensation mode, the duty cycle of the charging signal CS is reduced to less than D_max.

[0046] In one embodiment, D_max is

[0047] I_c is the charging current of output capacitor C_1 when it is charging. In one embodiment, I_c is equal to Figure 3 The forward current of the Schottky diode SD in the circuit. Additionally, I_d is the discharge current when the output capacitor is not charged. In one embodiment, I_d may be the leakage current of the Schottky diode SD, the switching loss current of the pre-drivers Pr_1a, Pr_1b, and Pr_1c during the switching period, or... Figure 3 The leakage current at the junction of node V_p1 in the diagram.

[0048] According to the foregoing embodiments, the voltage converter provided by the present invention can compensate for leakage current problems without directly pulling down the output voltage, thereby compensating for leakage current of the output capacitor while avoiding circuit abnormalities.

[0049] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.

Claims

1. A voltage converter, comprising: Output circuit, including output capacitor; Error amplifier; The charging control circuit includes: A detection circuit is used to generate a detection signal by detecting the output voltage of the output capacitor, the detection signal being used to indicate whether the output voltage of the output capacitor is less than a threshold voltage. as well as A power limiting circuit is used to clamp the output voltage of the error amplifier to a specific voltage level when the detection signal indicates that the output voltage of the output capacitor is less than the threshold voltage. as well as A charging circuit is used to generate a charging signal to the output circuit based on the output voltage of the error amplifier, so as to charge the output capacitor. Specifically, this particular voltage level causes the duty cycle of the charging signal to decrease to less than the maximum permissible duty cycle for charging the output capacitor.

2. The voltage converter of claim 1, wherein the power limiting circuit clamps the output voltage of the error amplifier to the specific voltage level, thereby increasing the frequency of charging the output capacitor by the charging circuit.

3. The voltage converter as claimed in claim 1, wherein the charging circuit is a PWM circuit and the charging signal is a PWM signal.

4. The voltage converter as claimed in claim 1, wherein, The maximum allowable duty cycle is Where I_c is the charging current when the output capacitor is charged, and I_d is the discharging current when the output capacitor is not charged.

5. The voltage converter as described in claim 3, The output circuit includes an upper bridge path and a lower bridge path; If the charging signal has a low logic value, the lower bridge path is turned on to charge the output capacitor, but the upper bridge path is turned off. If the charging signal has a high logic value, the upper bridge path is open but the lower bridge path is closed.

6. The voltage converter of claim 1, wherein the power limiting circuit comprises: Differential amplifier, comprising: The first input terminal is used to receive the output voltage of the error amplifier; The second input terminal is used to receive the reference voltage; The first output terminal is used to generate a first power limiting signal based on the output voltage of the error amplifier and the reference voltage; The second output terminal is used to generate a second power limiting signal based on the output voltage of the error amplifier and the reference voltage. The error amplifier receives the first power limiting signal and the second power limiting signal to generate the output voltage of the error amplifier.

7. The voltage converter of claim 6, wherein the charging circuit is a PWM circuit including at least one comparator, wherein the comparator receives the output voltage of the error amplifier and a triangular wave signal to generate the charging signal.

8. The voltage converter of claim 1, wherein the detection circuit comprises: A comparator is used to compare the voltage across the output capacitor with a threshold voltage difference; and A logic circuit is used to generate the detection signal based on the output of the comparator.

9. A Class D amplifier, comprising: Output circuit, including output capacitor; Error amplifier; The charging control circuit includes: A detection circuit is used to generate a detection signal by detecting the output voltage of the output capacitor, the detection signal being used to indicate whether the output voltage of the output capacitor is less than a threshold voltage. as well as A power limiting circuit is used to clamp the output voltage of the error amplifier to a specific voltage level when the detection signal indicates that the output voltage of the output capacitor is less than the threshold voltage. as well as A charging circuit is used to generate a charging signal to the output circuit based on the output voltage of the error amplifier, so as to charge the output capacitor. Specifically, this particular voltage level causes the duty cycle of the charging signal to decrease to less than the maximum permissible duty cycle for charging the output capacitor.

10. The Class D amplifier of claim 9, wherein the power limiting circuit clamps the output voltage of the error amplifier to the specific voltage level, causing the charging circuit to increase the frequency of charging the output capacitor.

11. The Class D amplifier of claim 9, wherein the charging circuit is a PWM circuit and the charging signal is a PWM signal.

12. The Class D amplifier as claimed in claim 9, wherein, The maximum allowable duty cycle is Where I_c is the charging current when the output capacitor is charged, and I_d is the discharging current when the output capacitor is not charged.

13. The Class D amplifier as described in claim 11, The output circuit includes an upper bridge path and a lower bridge path; If the charging signal has a low logic value, the lower bridge path is turned on to charge the output capacitor, but the upper bridge path is turned off. If the charging signal has a high logic value, the upper bridge path is open but the lower bridge path is closed.

14. The Class D amplifier of claim 9, wherein the power limiting circuit comprises: Differential amplifier, comprising: The first input terminal is used to receive the output voltage of the error amplifier; The second input terminal is used to receive the reference voltage; The first output terminal is used to generate a first power limiting signal based on the output voltage of the error amplifier and the reference voltage; The second output terminal is used to generate a second power limiting signal based on the output voltage of the error amplifier and the reference voltage. The error amplifier receives the first power limiting signal and the second power limiting signal to generate the output voltage of the error amplifier.

15. The Class D amplifier of claim 14, wherein the charging circuit is a PWM circuit including at least one comparator, wherein the comparator receives the output voltage of the error amplifier and a triangular wave signal to generate the charging signal.

16. The Class D amplifier of claim 9, wherein the detection circuit comprises: A comparator is used to compare the voltage across the output capacitor with a threshold voltage difference; and A logic circuit is used to generate the detection signal based on the output of the comparator.

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