Image sensor, method for operating an image sensor

Abstract

The present invention provides an image sensor and an operation method thereof. The image sensor includes: at least one row of pixel units, a row driving circuit, and a row decoding and holding circuit. The row driving circuit corresponds to the row pixel units and is adapted to drive the photodiodes in the corresponding row pixel units to reset according to a reset row address. The row decoding and holding circuit is adapted to decode the row addresses of the pixel units and hold their states to control the row driving circuit, so as to simultaneously reset the photodiodes in multiple rows of pixel units. In the present invention, the photodiodes in multiple rows of the image sensor can be simultaneously reset. Compared with the traditional reset operation method, it greatly saves time and can significantly improve the frame rate of the image sensor.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and in particular, to an image sensor and an operation method thereof. Background Art

[0002] The general pixel unit structure is as Figure 1 shown. A pixel unit includes a photodiode D1, a transfer transistor MTX, a floating diffusion region FD, a reset transistor MRST, an amplifying transistor (source follower) MSF, and a strobe transistor MSEL. The signal TX drives the gate of the transfer transistor MTX, the signal RST drives the gate of the reset transistor MRST, and the signal SEL drives the gate of the strobe transistor MSEL.

[0003] The reset operation process of the photodiode D1 in the pixel unit is as follows: First, the signal RST changes from low to high, the reset transistor MRST is turned on, and the floating diffusion region FD is reset to VDD; then the signal RST becomes low, and the reset transistor MRST is turned off; then the signal TX changes from low to high, the transfer transistor MTX is turned on, and all the electrons accumulated in the photodiode D1 are transferred to the floating diffusion region FD; finally, the signal TX becomes low, and the transfer transistor MTX is turned off. In this way, the reset operation of the photodiode D1 in the pixel unit is completed.

[0004] Due to performance requirements, an image sensor needs to reset the photodiodes in multiple rows of pixel units.

[0005] In a conventional image sensor, the reset operations of the photodiodes in multiple rows of pixel units are performed in a time-sharing (serial) manner, that is, the photodiodes in multiple rows of pixel units are reset row by row in sequence. Figure 2 For the row operation timing diagram of a conventional image sensor, where ADDR<10:0> is the row address signal (taking an 11-bit row address code as an example), RSEL, RG, and TG are row input signals. RSEL is used to generate the signal SEL, RG is used to generate the signal RST, and TG is used to generate the signal TX; T1 is the time required to complete a single reset operation of the photodiode in the reset row of pixel units, T2 is the time required to complete the readout operation of the photodiode in row j of pixel units, and the reset operations of the photodiodes in the reset rows l, m, and n of pixel units are performed in a time-sharing (serial) manner. Taking the number of reset rows as 3 as an example, since the time required for the photodiode to complete one reset operation is T1, and the reset operations of the photodiodes in 3 rows of pixel units are performed in a time-sharing manner, the time required for the photodiodes in 3 rows of pixel units to complete the reset operation is 3T1.

[0006] Therefore, the time-sharing (serial) reset operation of the photodiodes in multiple rows of pixel units in a conventional image sensor will limit the improvement of the frame rate of the image sensor. Summary of the Invention

[0007] An object of the present invention is to provide an image sensor and an operation method thereof, which solve the technical problem that the conventional image sensor performs time-division (serial) reset operations on photodiodes in multiple rows of pixel units, which will limit the frame rate of the image sensor.

[0008] To solve the above technical problem, the technical solution of the present invention provides an image sensor, including: at least one row of pixel units, a row driving circuit, and a row decoding and holding circuit; the row driving circuit corresponds to the row pixel units and is adapted to drive the photodiodes in the corresponding row of pixel units to be reset according to the reset row address; the row decoding and holding circuit is adapted to decode the row address of the pixel units and hold its state to control the row driving circuit so that the photodiodes in multiple rows of pixel units are reset simultaneously.

[0009] Preferably, the row decoding and holding circuit includes a decoding unit and at least one state holding unit; the decoding unit is adapted to decode the reset row address; the state holding unit is adapted to be set according to the decoding result of the decoding unit to control the row driving circuit, so as to simultaneously reset the photodiodes in multiple rows of pixel units, save the multiple reset time, and improve the frame rate.

[0010] Preferably, the decoding unit includes a reset circuit, a decoding enable unit, and a decoding logic unit connected in series;

[0011] The reset circuit is adapted to reset the state of the state holding unit before decoding the target row address;

[0012] The decoding enable unit is adapted to provide an enable signal to the decoding logic unit;

[0013] The decoding logic unit is adapted to decode the row address code signal ADDR <n-1:0>Perform decoding and output the decoding result to the state holding unit;

[0014] The state holding unit is adapted to hold the decoding result of the decoding unit until the next reset circuit resets it.

[0015] One end of the decoding logic unit is grounded, and the other end is connected to the decoding enable unit. The decoding logic unit is n NMOS transistors connected in series, where n is a natural number. The gates of the n NMOS transistors connected in series are respectively connected to the row address code signal ADDR one by one. <n-1:0>。

[0016] Preferably, the decoding enable unit is an NMOS transistor N connected in series with the decoding logic unit n 。

[0017] Preferably, the decoding enable unit is connected to the first end of the reset circuit, the second end of the reset circuit is connected to VDD, the third end of the reset circuit is a control end, and the third end of the reset circuit receives a row address reset signal.

[0018] Preferably, the reset circuit is a PMOS transistor. The gate of the PMOS transistor is connected to the output end of the first inverter inv1, and the input end of the first inverter inv1 is connected to the row address reset signal clear.

[0019] Preferably, the state holding unit includes a capacitor, a second inverter inv2, and a level restoration circuit. The capacitor is adapted to hold the state output by the decoded middle row decoding circuit, and the level restoration circuit is adapted to restore the state output by the non-decoded middle row decoding unit.

[0020] Preferably, the level restoration circuit is a PMOS transistor. The gate of the level restoration circuit is connected to the output end of the second inverter inv2 and is also connected to the output signal REN of the row decoding holding circuit. The drain of the level restoration circuit is connected to the input end of the second inverter inv2, and the source of the level restoration circuit is connected to the power supply voltage VDD.

[0021] Preferably, the capacitor is a MOM capacitor, a MIM capacitor, a PIP capacitor, or a MOS capacitor; one end of the capacitor is grounded, and the other end is connected to the input end of the second inverter inv2.

[0022] Preferably, the row decoding holding circuit is an integrated module.

[0023] Preferably, the pixel unit includes:

[0024] A photodiode D1, a floating diffusion region FD, a transfer transistor MTX, a reset transistor MRST, a source follower MSF, and a strobe transistor MSEL;

[0025] The TX signal drives the gate of the transfer transistor MTX;

[0026] The RST signal drives the gate of the reset transistor MRST;

[0027] The SEL signal drives the gate of the strobe transistor MSEL.

[0028] Preferably, it includes: The reset circuit cooperates with the decoding enable unit and the decoding logic unit to accurately decode the target row and avoid decoding non-target rows.

[0029] Preferably, the rising edge / falling edge of the row address reset signal clear is staggered from the rising edge / falling edge of the row address enable signal gating.

[0030] The technical solution of the present invention also provides an operation method of an image sensor as described above, including:

[0031] Successively decode the reset row address signal and save the decoding result;

[0032] Output a row driving signal to enable the target row pixel units to perform a reset operation simultaneously.

[0033] Compared with the prior art, the image sensor and its operation method of the present invention have the following beneficial effects:

[0034] In the present invention, the photodiodes in multiple rows of the image sensor can be reset simultaneously. Compared with the traditional reset operation method, the new reset operation method greatly saves time and can significantly improve the frame rate of the image sensor. Description of the Drawings

[0035] Figure 1 It is a schematic diagram of a general pixel unit structure;

[0036] Figure 2 It is a timing diagram of row operations of a traditional image sensor;

[0037] Figures 3 to 4 It is a schematic diagram of the structure of the image sensor in the embodiment provided by the technical solution of the present invention;

[0038] Figure 5 It is a timing diagram of row operations of the image sensor in the embodiment provided by the technical solution of the present invention. Detailed Embodiments

[0039] Many specific details are set forth in the following description in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0040] Secondly, the present invention is described in detail using schematic diagrams. When detailing the embodiments of the present invention, for ease of explanation, the schematic diagrams are only examples and should not limit the scope of protection of the present invention herein.

[0041] To make the above objects, features, and advantages of the present invention more apparent and understandable, the image sensor and its operation method of the present invention will be described in detail below with reference to the accompanying drawings.

[0042] Combined with Figure 1 , referring to Figures 3 to 4 As shown in the figure, the present invention provides an image sensor, including: at least one row of pixel units, a row driving circuit, and a row decoding and holding circuit. The row driving circuit corresponds to the row pixel units and is adapted to drive the photodiodes in the corresponding row pixel units to be reset according to the reset row address. The row decoding and holding circuit is adapted to decode the row addresses of the pixel units and hold their states to control the row driving circuit, so that the photodiodes in multiple rows of pixel units are reset simultaneously.

[0043] Continue to refer to Figure 1 As shown in the figure, specifically, in this embodiment, the pixel unit of the image sensor includes: a photodiode D1, a transfer transistor MTX, a floating diffusion region FD, a reset transistor MRST, a source follower MSF, and a selection transistor MSEL. The TX signal drives the gate of the transfer transistor MTX, the RST signal drives the gate of the reset transistor MRST, and the SEL signal drives the gate of the selection transistor MSEL.

[0044] In this embodiment, the reset operation process of the photodiode D1 in the pixel unit is as follows:

[0045] First, the RST signal changes from low to high, the reset transistor MRST conducts, and the floating diffusion region FD is reset to VDD.

[0046] Then, the RST signal becomes low, and the reset transistor MRST turns off.

[0047] Next, the TX signal changes from low to high, the transfer transistor MTX conducts, and all the electrons accumulated in the photodiode D1 are transferred to the floating diffusion region FD.

[0048] Finally, the TX signal becomes low, and the transfer transistor MTX turns off.

[0049] In this way, the reset operation of the photodiode D1 in the pixel unit is completed. In general applications, due to the performance requirements of the image sensor, it is necessary to reset the photodiodes in multiple rows of pixel units.

[0050] Refer to Figure 3 As shown in the figure, Figure 3 is a schematic diagram of the row circuit structure provided by the technical solution of the present invention. Among them, the row circuit includes a row decoding and holding circuit and a row driving circuit. In this embodiment, the row decoding circuit and the row decoding and holding circuit are an integrated module.

[0051] Combined with Figure 4 , in this embodiment, the row decoding and holding circuit includes a decoding unit and at least one state holding unit. Among them, the decoding unit is adapted to decode the reset row address; the state holding unit is adapted to be set according to the decoding result of the decoding unit to control the row driving circuit, so as to reset the photodiodes in multiple rows of pixel units simultaneously, save the reset time of multiple rows, and improve the frame rate.

[0052] Specifically, in this embodiment, an 11-bit row address code is taken as an example. Figure 3 In, ADDR<10:0> at the input end of the row decoding and holding circuit is a row address signal, clear is a row address reset signal, and gating is a row address enable signal.

[0053] Figure 3 In, RSEL, RG, and TG at the input end of the row driving circuit are row input signals. Among them, RSEL is used to generate the row signal SEL, RG is used to generate the signal RST, and TG is used to generate the signal TX. SEL <l>, RST <l>, TX <l>is the row driving signal of the pixel unit of row l; SEL <n>, RST <n>, TX <n>It is the row driving signal for the row pixel units of row n. That is, in this embodiment, n is taken as 10 for example.

[0054] The row address signal ADDR<10:0>, the row address reset signal clear, and the row address enable signal gating are simultaneously input to the input terminal of the row decoding and holding circuit. The row decoding and holding circuit decodes the row address and holds its state. The row decoding and holding circuit outputs the REN signal. The REN, together with the row input signals RSEL, RG, and TG, is input to the input terminal of the row driving circuit to jointly control the output signals SEL, RST, and TX of the row driving circuit. The SEL signal drives the gate of the selection transistor MSEL, the RST signal drives the gate of the reset transistor MRST, and the TX signal drives the gate of the transmission transistor MTX.

[0055] Combined with reference Figure 4 as shown Figure 4 is the structure diagram of the row decoding and holding circuit provided in this embodiment. The row decoding and holding circuit includes a decoding unit and at least one state holding unit; the decoding unit is adapted to decode the reset row address; the state holding unit is adapted to be set according to the decoding result of the decoding unit to control the row driving circuit, so as to simultaneously reset the photodiodes in multiple rows of pixel units, save the reset time of multiple rows, and improve the frame rate.

[0056] Among them, the decoding unit includes a reset circuit, a decoding enable unit, and a decoding logic unit connected in series.

[0057] The reset circuit is adapted to reset the state of the state holding unit before decoding the target row address;

[0058] The decoding enable unit is adapted to provide an enable signal to the decoding logic unit;

[0059] The decoding logic unit is adapted to decode the row address code signal ADDR<10:0> and output the decoding result to the state holding unit;

[0060] The state holding unit is adapted to hold the decoding result of the decoding unit until the next reset circuit resets it.

[0061] The decoding logic unit is 11 NMOS transistors N0 to N10 connected in series, and one end of the decoding logic unit is grounded and the other end is connected to the decoding enable unit. Among them, the gates of the series-connected NMOS transistors N10 to N0 correspond to the connection of the row address code signal ADDR<10:0>, and the decoding enable unit is the NMOS transistor N11 connected in series with the decoding logic unit, and n is a natural number.

[0062] Figure 4 Among them, NMOS transistors N0 to N10 are connected in series in sequence to form a decoding logic unit, which decodes the row address code. The decoding enable unit is NMOS transistor N11.

[0063] In this embodiment, in the decoding logic unit, one end is connected to the ground terminal GND by the source of NMOS N10, and the other end is connected to the source of NMOS transistor N11 by the drain of NMOS N0. The drain of the NMOS transistor N11 is connected to the first end of the reset circuit P1, the second end of the reset circuit P1 is connected to VDD, the third end of the reset circuit P1 is the control end, and the third end receives the output after the row address reset signal clear passes through the first inverter inv1.

[0064] In this embodiment, the reset circuit P1 is a PMOS transistor. Specifically, in other embodiments, the reset circuit P1 can be other three-terminal devices, and the conduction or closing between the other two ends is controlled by controlling the third end.

[0065] Specifically, in this embodiment, the row address reset signal clear is inverted by the first inverter inv1 and then connected to the gate of the reset circuit P1.

[0066] In this embodiment, the state holding unit holds the output state of the decoding circuit. The state holding unit includes: a capacitor C0, a second inverter inv2, and a level restoration circuit P2; among them, the capacitor C0 is suitable for holding the state output by the row decoding circuit during decoding, and the level restoration circuit P2 is suitable for restoring the state output by the row decoding unit that has not been decoded.

[0067] Specifically, in this embodiment, the level restoration circuit P2 is a PMOS transistor. The gate of the level restoration circuit P2 is connected to the output end of the second inverter inv2 and is connected to the output signal REN of the row decoding holding circuit. The drain of the level restoration circuit is connected to the input end of the second inverter inv2, and the source of the level restoration circuit is connected to the power supply voltage VDD.

[0068] Specifically, in this embodiment, the capacitor C0 is a MOM capacitor, a MIM capacitor, a PIP capacitor, or a MOS capacitor. One end of the capacitor C0 is grounded, and the other end is connected to the input end of the second inverter inv2.

[0069] Specifically, in this embodiment, the row address reset signal clear is input to the gate terminal of the reset circuit P1 through the first inverter inv1. When the row address reset signal clear is high, the reset circuit P1 pulls the node A to the power supply VDD, and the output signal REN of the row decoding holding circuit is low and invalid, that is, the row address state held by the state holding unit is reset.

[0070] When the row address reset signal clear is low, the reset circuit P1 is turned off. When the row address enable signal gating is high, N11 is turned on. The row address code ADDR<10:0> causes all of N0 to N10 in a certain row to be turned on. Then, N0 to N10 form a path from node A to ground, pulling node A to ground. The capacitor C0 holds the voltage of node A at a low level, and the output signal REN is high and valid, that is, the row address is decoded.

[0071] When the row address is not decoded correctly, after node A is pulled to VDD and the reset circuit P1 is turned off, if gating and ADDR<10:0> act frequently, the conduction of some of the tubes N0 to N10 causes the redistribution of charges on the parasitic capacitors of node A and the signal path, resulting in a decrease in the voltage of node A. When it drops to a certain extent, the output REN may be misflipped to a high level, that is, the output REN of the un-decoded row is wrongly output as valid. P2 and inv2 form a positive feedback, which can suppress the decrease of node A due to charge redistribution. At the same time, P2 is a ratioed inverter, and its driving ability is much smaller than the series path of N0 to N11, avoiding pull-down errors during decoding.

[0072] An embodiment of the present invention also provides a method for simultaneously resetting multiple rows of photodiodes in an image sensor, including: before decoding the target row address, resetting the state of the state holding unit through the reset circuit P1, then enabling the decoding enable logic, decoding the reset row address by the decoding circuit, and outputting the decoding result to the state holding unit. The state holding unit holds the decoding result of the decoding unit until the next reset by the reset circuit.

[0073] Specifically, continuing to combine Figure 1 、 Figures 3 to 4 shown, referring to Figure 5 , Figure 5 which is a new timing diagram of the row operation of the image sensor, an embodiment of the present invention also provides an operation method of an image sensor, including:

[0074] Decoding the reset row address signal in sequence and saving the decoding result;

[0075] Outputting a row driving signal to make the target row pixel units perform a reset operation simultaneously.

[0076] The decoding unit decodes the reset row address in sequence, and the decoding result is output to the state holding unit. The state holding unit controls the row driving circuit, thereby realizing the operation of simultaneously resetting the reset row photodiodes, saving the reset time of multiple photodiodes, and improving the efficiency.

[0077] The reset circuit cooperates with the decoding enable unit and the decoding logic unit, and can accurately decode the target row, avoiding decoding non-target rows.

[0078] Figure 5 In the example, at time A, the row address reset signal clear is a narrow pulse signal, which resets the output REN of the row decoding and holding circuit. Then the row address enable signal gating is a narrow pulse, and the exposure row 1 is decoded. The capacitor C0 keeps the decoded row address code valid until the next narrow pulse of the row address reset signal clear appears to reset the row address. T3 (time A to time B) is the time when the exposure row 1 address is decoded.

[0079] Furthermore, in this embodiment, it can be seen that the rising edge / falling edge of the row address reset signal clear and the row address enable signal gating are staggered. This is because the rising edge / falling edge of the row address code signals of different bits cannot be completely aligned when they are input to the input end of the decoding logic unit. The staggering of the rising edge / falling edge of the row address reset signal clear and the row address enable signal gating can avoid decoding into non-target rows.

[0080] Furthermore, in this embodiment, the time from time B to time C is the time when the address of exposure row m is translated, and the process from time A to time B is repeated. At time C, a narrow pulse signal appears in gating, and exposure row n is translated. Because exposure rows l and m have been translated and remain valid, within T1 time, the row input signals RSEL, RG, and TG make the row drive circuits of reset rows l, m, and n simultaneously output the same row drive signals SEL, RST, and TX to the pixel array, so that reset rows l, m, and n perform reset operations simultaneously. T2 (from time D to time E) is the readout operation time of readout row j.

[0081] In general, the address translation time T3 is about 20-30ns, the reset operation time T1 is about 200ns-500ns, and the T3 time is much shorter than the T1 time. The above embodiment takes the simultaneous reset of three rows as an example to illustrate the operation method and principle of the present invention. Based on the above information, those skilled in the art can know that the above structure and method are applicable to the case of simultaneous reset of multiple rows.

[0082] When three rows are reset simultaneously, the new reset operation method saves 360ns to 940ns compared to the traditional reset operation method. If the number of rows reset simultaneously increases, the time saved is more significant.

[0083] Because the row address reset signal clear first resets the state holding unit when the row address changes, the row address enable signal is valid only after the row address is stable, and the decoder starts decoding. This avoids the situation where different bits of address codes arrive at the decoder at different times when the row address changes, resulting in incorrect row address codes being translated.

[0084] Although the present invention has been disclosed above in preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the technical solution of the present invention all fall within the protection scope of the technical solution of the present invention.< / n> < / n> < / n> < / l> < / l> < / l>

Claims

1. An image sensor, characterized in that, Comprising: At least one row of pixel units, a row driving circuit, and a row decoding and holding circuit; The row driving circuit corresponds to the row pixel units and is adapted to drive the photodiodes in the corresponding row pixel units to reset according to the reset row address; The row decoding and holding circuit is adapted to decode the row address of the pixel units and hold its state to control the row driving circuit, so that the photodiodes in multiple rows of pixel units are reset simultaneously; The row decoding and holding circuit includes a decoding unit and at least one state holding unit; The decoding unit is adapted to decode the reset row address; the state holding unit is adapted to be set according to the decoding result of the decoding unit to control the row driving circuit; The decoding unit includes a reset circuit, a decoding enable unit, and a decoding logic unit connected in series; The reset circuit is adapted to reset the state of the state holding unit before decoding the target row address; The decoding enable unit is adapted to control whether conduction is enabled among the reset circuit, the state holding unit, and the decoding logic unit, and the pending row address code signal ADDR <n-1:0>After the voltage is stabilized, the reset circuit, the state holding unit, and the decoding logic unit are conducted to avoid misdecoding the row address code due to different arrival times of different bit address codes at the decoder when the row address changes; The decoding logic unit is adapted to the row address code signal ADDR <n-1:0>Perform decoding and output the decoding result to the state holding unit; The state holding unit is adapted to hold the decoding result of the decoding unit until the next reset circuit resets it.

2. The image sensor according to claim 1, wherein One end of the decoding logic unit is grounded, and the other end is connected to the decoding enable unit. The decoding logic unit is composed of n NMOS transistors connected in series, where n is a natural number. The gates of the n NMOS transistors connected in series are respectively and correspondingly connected to the row address code signal ADDR <n-1:0> 。< / n-1:0> 3. The image sensor according to claim 2, wherein The decoding enable unit is an NMOS transistor Nn connected in series with the decoding logic unit.

4. The image sensor according to claim 2, wherein The decoding enable unit is connected to the first end of the reset circuit, the second end of the reset circuit is connected to VDD, the third end of the reset circuit is a control end, and the third end is connected to the row address reset signal.

5. The image sensor according to claim 4, wherein The reset circuit is a PMOS, the gate of the PMOS is connected to the output end of the first inverter inv1, and the input end of the first inverter inv1 is connected to the row address reset signal clear.

6. The image sensor according to claim 1, wherein The state holding unit includes a capacitor, a second inverter inv2, and a level restoration circuit. The capacitor is adapted to hold the state output by the decoded row decoding circuit, and the level restoration circuit is adapted to restore the state output by the non-decoded row decoding unit.

7. The image sensor according to claim 6, wherein The level restoration circuit is a PMOS transistor. The gate of the level restoration circuit is connected to the output end of the second inverter inv2 and is connected to the output signal REN of the row decoding and holding circuit. The drain of the level restoration circuit is connected to the input end of the second inverter inv2, and the source of the level restoration circuit is connected to the power supply voltage VDD.

8. The image sensor according to claim 6, wherein The capacitor is a MOM capacitor, a MIM capacitor, a PIP capacitor, or a MOS capacitor; one end of the capacitor is grounded, and the other end is connected to the input end of the second inverter inv2.

9. The image sensor according to claim 1, wherein the row decoding hold circuit is an integral module.

10. The image sensor according to claim 1, wherein the pixel unit comprises: a photodiode D1, a transfer transistor MTX, a floating diffusion region FD, a reset transistor MRST, a source follower MSF, and a select transistor MSEL; a TX signal drives the gate of the transfer transistor MTX; an RST signal drives the gate of the reset transistor MRST; a SEL signal drives the gate of the select transistor MSEL.

11. The image sensor according to claim 1, characterized in that, comprising: the reset circuit cooperates with the decoding enable unit and the decoding logic unit to accurately decode the target row and avoid decoding non-target rows.

12. An operation method of the image sensor according to claim 1, wherein comprising: successively decoding the reset row address signal and saving the decoding result; outputting a row driving signal to enable the pixel units of the target row to perform a reset operation simultaneously.

13. The method for operating an image sensor according to claim 12, wherein, comprising: the rising edge / falling edge of the row address reset signal clear is staggered from that of the row address enable signal gating.

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