Distributed Communication Unit and Communication Extension Device

Abstract

Embodiments of the present invention disclose a distributed communication unit and a communication extension device. The distributed communication unit includes a controller, a clock matrix synchronization chip, and a first PHY chip. The controller is connected to the clock matrix synchronization chip and is used to receive the clock signal output by the clock matrix synchronization chip. The controller is also connected to the first PHY chip and is used to control the low-latency transmission of communication data to the first PHY chip according to the clock signal, so that the first PHY chip is used to perform high-speed network communication with the connected remote unit according to the communication data. Embodiments of the present invention integrate various simple and low-cost components into an SoC circuit architecture, and can implement communication extension in the 5G communication process with only one controller, and complete the functions of data splitting, merging, and forwarding.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular, to a distributed communication unit and a communication extension device. Background Art

[0002] With the development of network communications and people's requirements for communication real-time performance, the construction of 5G networks has been developing rapidly. However, currently, there are two completely opposite experiences in connecting to 5G networks indoors and outdoors in some places. The 5G signal outdoors is continuously stable, while the 5G signal indoors sometimes appears intermittent. In fact, this is caused by the insufficient deep coverage ability of indoor signals. Therefore, it is necessary to expand 5G communications to achieve deep signal coverage.

[0003] In the prior art, the communication extension of 5G communications is usually achieved by using a CPU plus an FPGA. However, due to the high cost, high power consumption of the FPGA, and the need for complex programming work, it is difficult to meet the daily basic requirements. Therefore, how to design a distributed communication unit with a simple structure, low cost, and low power consumption to achieve communication extension is an urgent problem to be solved. Summary of the Invention

[0004] In a first aspect, the present invention provides a distributed communication unit, including: a controller, a clock matrix synchronization chip, and a first PHY chip;

[0005] The controller is connected to the clock matrix synchronization chip and is configured to receive a clock signal output by the clock matrix synchronization chip;

[0006] The controller is further connected to the first PHY chip and is configured to control the sending of communication data to the first PHY chip with low latency according to the clock signal, so that the first PHY chip is used to perform high-speed network communication with a connected remote unit according to the communication data.

[0007] In an optional embodiment, the clock matrix synchronization chip inputs an LVDS clock signal to the controller through a REF CLK interface;

[0008] The clock matrix synchronization chip further inputs an LVCMOS clock signal to the controller through a REN CLK interface;

[0009] The clock matrix synchronization chip is further connected to the SPI_CS interface of the controller to implement data communication between the clock matrix synchronization chip and the controller;

[0010] The clock matrix synchronization chip is further connected to the controller through a GPIO interface and is configured to receive an enable signal sent by the controller to control the operation or stop of the clock matrix synchronization chip.

[0011] In an alternative embodiment, the clock matrix synchronization chip is used to connect to a GPS module, receive the 1PPS signal output by the GPS module, and send the clock signal to the controller according to the 1PPS signal.

[0012] In an alternative embodiment, a second PHY chip is further included. The second PHY chip is connected to the controller and is used for network communication with the connected external device to configure parameters of the external device.

[0013] In an alternative embodiment, the controller is further used to connect to a first group of optical fiber interfaces to respectively connect to a plurality of the remote units through the first group of optical fiber interfaces, so as to implement network communication with the plurality of remote units.

[0014] In an alternative embodiment, the controller is further used to connect to a second group of optical fiber interfaces to respectively connect to a central unit and other distributed communication units through the second group of optical fiber interfaces, so as to implement network communication between the controller and the central unit and the other distributed communication units.

[0015] In a second aspect, the present invention provides a communication extension device, including: a power supply module, a synchronization module, and the distributed communication unit as described above;

[0016] The power supply module is respectively connected to the synchronization module and the distributed communication unit and is used to supply power to the synchronization module and the distributed communication unit;

[0017] The distributed communication unit is connected to the synchronization module through a communication interface and is used to transmit synchronization information to the synchronization module;

[0018] The synchronization module is used to connect to an electrical device through a POE interface, input synchronization information to the electrical device, and supply power to the electrical device.

[0019] In an alternative embodiment, a GPS module is further included. The GPS module is connected to the clock matrix synchronization chip in the distributed communication unit through a communication interface and is used to transmit a 1PPS signal to the clock matrix synchronization chip, so that the clock matrix synchronization chip inputs a clock signal to the controller according to the 1PPS signal;

[0020] The communication interface between the GPS module and the clock matrix synchronization chip is an SGMII interface.

[0021] In an alternative embodiment, the synchronization module is a switch with PSE function or a module including a PSE controller and a switch.

[0022] In an alternative embodiment, the GPS module is further configured to connect to a GPS antenna to receive satellite signals and input a clock signal to the clock matrix synchronization chip through the satellite signals;

[0023] The GPS module is connected to the controller through a UART interface and is configured to input TOD information to the controller through the satellite signals.

[0024] The present invention has the following beneficial effects:

[0025] An embodiment of the present invention provides a distributed communication unit, including a controller, a clock matrix synchronization chip, and a first PHY chip; the controller is connected to the clock matrix synchronization chip and is configured to receive a clock signal output by the clock matrix synchronization chip; the controller is further connected to the first PHY chip and is configured to control the transmission of communication data to the first PHY chip with low latency according to the clock signal, so that the first PHY chip is configured to perform high-speed network communication with a connected remote unit according to the communication data. In the embodiment of the present invention, simple and low-cost components are integrated into a SoC circuit architecture, and communication expansion in the 5G communication process can be achieved by only one controller, and functions of data splitting, merging, and forwarding can be completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the protection scope of the present invention. In each drawing, similar components are numbered similarly.

[0027] Figure 1 It is a schematic structural diagram of a 5G small base station system in an embodiment of the present invention;

[0028] Figure 2 It is a schematic structural diagram of a communication expansion device in an embodiment of the present invention;

[0029] Figure 3 It is another schematic structural diagram of a communication expansion device in an embodiment of the present invention;

[0030] Figure 4 It is a schematic circuit topology diagram of a PSE controller in an embodiment of the present invention;

[0031] Figure 5 It is a schematic structural diagram of a distributed communication unit in an embodiment of the present invention;

[0032] Figure 6 It is another schematic structural diagram of a distributed communication unit in an embodiment of the present invention.

[0033] Description of main component symbols: 10 - Communication extension device; 20 - Central unit; 30 - Remote unit; 11 - Distributed communication unit; 12 - Synchronization module; 13 - Power supply module; 121 - PSE controller; 122 - Switch; 14 - GPS module; 111 - Controller; 112 - Clock matrix synchronization chip; 113 - First PHY chip; 114 - Second PHY chip; 15 - GPS antenna. Detailed implementation manners

[0034] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments.

[0035] Generally, the components of the embodiments of the present invention described and illustrated herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0036] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present invention are only intended to represent specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be construed as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0037] In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0038] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the various embodiments of the present invention belong. The terms (such as those defined in a commonly used dictionary) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or being overly formal, unless clearly defined in the various embodiments of the present invention.

[0039] PSE (Power Sourcing Equipment), a POE power supply device, injects power into the Ethernet cable and implements power planning and management. Small network devices can directly obtain power from the Ethernet cable without laying separate power lines, so as to simplify the system wiring.

[0040] SPI flash (Serial Peripheral interface). The serial peripheral interface is mainly applied between EEPROM, FLASH, real-time clock, AD converter, digital signal processor and digital signal decoder. The SPI bus system is a synchronous serial peripheral interface, which enables the MCU to communicate with peripheral devices in a serial manner. SPI flash is the NOR FLASH of the serial communication interface.

[0041] DDR4 memory. It has a 16-bit prefetch mechanism (DDR3 has an 8-bit prefetch mechanism), is faster at the same core frequency, has a reliable transmission specification, further improves data reliability, and has a working voltage reduced to 1.2V, making it more energy-efficient.

[0042] eMMC (Embedded Multi Media Card) memory, which is the standard specification of the embedded memory. eMMC integrates a controller in the package, provides a standard interface and manages the flash memory.

[0043] SPI interface (Serial Peripheral Interface), the serial peripheral interface, is a synchronous peripheral interface, which enables the interconnected devices to communicate in a serial manner to exchange information.

[0044] GPIO interface refers to a group of pins on the computer motherboard or add-on card; these pins can send or receive electrical signals.

[0045] Serdes signal (Serializer-Deserializer signal), the deserialization serializer signal.

[0046] Embodiment

[0047] This embodiment provides a communication extension device 10, which is applicable to the 5G small cell system, such as Figure 1 As shown, the communication extension device 10 can be used to connect to the central unit 20 (CU) and the remote unit 30 (RU) respectively. The distributed communication function of 5G communication is realized through the CU, the communication extension device 10 and the RU.

[0048] Among them, the CU is responsible for the operation and maintenance function of the base station, the L2 / L3 protocol stack processing and the high-layer baseband processing function, so as to send corresponding communication data to the communication extension device 10.

[0049] The communication extension device 10 can be used to realize the communication extension, data splitting, merging and data forwarding functions of 5G communication, and perform data distribution processing on the communication data sent by the CU through the 5G communication protocol, so as to distribute the communication data to multiple connected RUs.

[0050] The RU is used to complete the transceiver of the underlying baseband, radio frequency processing, and wireless signals according to the communication data.

[0051] Exemplarily, as Figure 2 and Figure 3 shown, the communication extension device 10 includes a power supply module 13, a synchronization module 12, and a distributed communication unit 11 (DU).

[0052] The power supply module 13 is respectively connected to the distributed communication unit 11 and the synchronization module 12, and is used to convert the AC power into DC power available to the distributed communication unit 11 and the synchronization module 12, and supply power to the distributed communication unit 11 and the synchronization module 12.

[0053] In a feasible implementation manner, the communication extension device 10 further includes a GPS module 14. The GPS module 14 is connected to the distributed communication unit 11. The GPS module 14 is used to connect to a GPS antenna 15 to obtain satellite signals. The GPS module 14 transmits synchronization information to the distributed communication unit 11 through the satellite signals. The synchronization information includes a 1PPS signal and TOD information.

[0054] The distributed communication unit 11 is connected to the synchronization module 12 through a communication interface, and is used to transmit synchronization information to the synchronization module 12. The distributed communication unit 11 is also used to connect to multiple RUs through a fiber optic interface, so as to perform data communication with the RUs. Optionally, the communication interface between the distributed communication unit 11 and the synchronization module 12 can be selected as an SGMII interface.

[0055] Exemplarily, the synchronization module 12 can be a switch 122 with PSE function or a module including a PSE controller 121 and a switch 122. Wherein, when the synchronization module 12 is a switch 122 with PSE function, the switch 122 can be used to connect external devices, for example, multiple RUs or other power-consuming devices, to transmit synchronization information to multiple RUs or other power-consuming devices, and supply power to multiple RUs or other power-consuming devices.

[0056] The following part takes the synchronization module 12 including the switch 122 and the PSE controller 121 as an example for description. The PSE controller 121 is used to connect power-consuming devices. For example, the external device can be multiple RUs or other power-consuming devices. The PSE controller 121 is equivalent to a POE network port power supply device. The synchronization module 12 converts the power output by the power supply module 13 according to the POE power supply protocol to directly supply power to the connected RUs or other power-consuming devices through a network cable / network port.

[0057] The switch 122 is used to obtain synchronization information from the distributed communication unit 11 through a communication interface and broadcast the synchronization information to the connected RUs in the switch 122 network according to the IEEE 1588 protocol.

[0058] Among them, multiple PSE controllers 121 can be selected for the synchronization module 12. For example, the PSE controller 121 can select a PSE controller 121 (PSE chip) of model BCM59122, and its circuit topology is as Figure 4 shown. The synchronization module 12 can include at least two PSE controllers 121. In this embodiment, taking the inclusion of two PSE controllers 121 as an example for illustration, the two PSE controllers 121 can provide a total of 8 PSE power supply interfaces. In this embodiment, only 3 RJ-45 PSE interfaces are listed, and a total of 3 devices can be externally connected. Each POE interface can be correspondingly connected to a remote unit 30 (RU).

[0059] For example, in scenarios where cameras are deployed at locations such as highways and camera monitoring is required, the synchronization module 12 including the PSE controller 121 can supply power to the cameras through network ports and at the same time provide a video data transmission path for the cameras. That is, through two PSE controllers 121, 8 POE power outputs are provided, and the maximum output power of each POE interface reaches 60W. That is, each POE power supply network port can provide 60W of power supply, so as to meet the power consumption requirements of cameras or other devices corresponding to video monitoring and speeding capture.

[0060] Optionally, the switch 122 can select a switching chip. For example, a switching chip of model 88E6393X. The switching chip of 88E6393X has rich functional characteristics, high scalability, high cost performance and other characteristics, and can provide a very attractive switch 122 solution applicable to multiple industries for users, thus facilitating use.

[0061] The PSE controller 121 of the synchronization module 12 can transmit data signals to some IP-based terminals (such as IP telephones, wireless LAN access points AP, network cameras, etc.) and at the same time provide DC power supply for such devices without any modification to the existing Ethernet Cat.5 wiring infrastructure, that is, the POE power supply technology.

[0062] The POE power supply technology can ensure the normal operation of the existing network while ensuring the safety of the existing structured cabling, and minimize costs. The POE power supply technology can have the following advantages: 1. Flexible cabling, the positions of terminal devices can be flexibly set or installed at various remote locations, and their position settings are not restricted; 2. Cost savings, power supply through the network port can reduce the power supply lines required for power supply and various devices used in conjunction with the power supply lines, such as sockets, pipelines, voltage conversion devices, etc., thereby saving the time cost, labor cost, and maintenance cost of power supply cabling; 3. Safe and reliable, centralized power supply can be carried out, and backup is convenient. The PSE controller 121 can also be connected to the UPS power supply. Once the power input is interrupted, the UPS power supply can also ensure the normal operation of the system.

[0063] Therefore, the communication extension device 10 provided in this embodiment has a simple structure, low cost, and supports the PSE function. The small base station can supply power to external devices through the POE power supply method in the communication extension device 10, eliminating the power supply cabling project and saving human and material resources.

[0064] Based on the structure of the communication extension device 10 described above, an embodiment of the present application also proposes a distributed communication unit 11. Exemplarily, as Figure 5 and Figure 6 shown, the distributed communication unit 11 includes a controller 111 (CPU), a clock matrix synchronization chip 112 (IDT), and a first PHY chip 113. For example, a CPU of model CN95XXO can be selected, a clock matrix synchronization chip 112 of 8A34001 can be selected, and a first PHY chip 113 of model 88X6142P can be selected.

[0065] The controller 111 (CPU) is respectively connected to the first PHY chip 113 and the clock matrix synchronization chip 112, and is used to receive the clock signal from the clock matrix synchronization chip 112, and control the low-latency transmission of communication data to the first PHY chip 113 according to the clock signal, or perform other processing.

[0066] The first PHY chip 113 is used to perform high-speed network communication with the connected external device, perform protocol conversion processing on the communication data, and then send it to the connected external device. Among them, the first PHY chip 113 is a high-speed PHY chip to provide high-rate network communication services. For example, the first PHY chip 113 is connected to the RU and performs network communication with the connected RU at a high communication rate of 25 Gbps. The first PHY chip 113 performs corresponding processing on the communication data according to the 5G communication protocol and sends it to the connected RU in the form of network packets.

[0067] In a feasible implementation, the distributed communication unit 11 further includes a second PHY chip 114. The second PHY chip 114 is connected to the controller 111 through a communication interface and is used to perform network communication with the connected external devices for parameter configuration and management of the external devices. For example, the second PHY chip 114 can be connected to devices such as a computer and a mobile terminal to perform network communication at a communication rate of 1 Gbps, so as to configure network node information, allocate parameters such as network ports, and manage the connected computer, mobile terminal, and other devices. Optionally, the communication interface between the second PHY chip 114 and the controller 111 can be an SGMII interface.

[0068] Exemplarily, the clock matrix synchronization chip 112 is used to connect to the GPS module 14 to receive the 1PPS signal sent by the GPS module 14, and adjust the clock edge of the output clock signal according to the 1PPS signal to output a more accurate clock signal to the controller 111.

[0069] Among them, the clock matrix synchronization chip 112 inputs a 156.25 MHz LVDS clock signal to the controller 111 through the REF CLK interface (such as the REF CLK2 interface in Figure 6 of the controller 111), and inputs a 30.72 MHz LVCMOS clock signal to the controller 111 through the REN CLK interface of the controller 111. The controller 111 performs different clock synchronization processes according to different clock signals to improve the accuracy of the internal time.

[0070] The clock matrix synchronization chip 112 is connected to the controller 111 through an SPI interface. For example, it is connected to the SPI_CS interface (such as the SPI_CS1 interface in Figure 6 of the controller 111) through the SPI interface to achieve data communication; the clock matrix synchronization chip 112 is also connected to the controller 111 through a GPIO interface to receive the enable signal sent by the controller 111 to control the operation or stop of the clock matrix synchronization chip 112.

[0071] Optionally, the clock matrix synchronization chip 112 is configured with a 49.125 MHz crystal and a 20 MHz oven-controlled crystal oscillator (OCXO device). By means of the configured OCXO device, the accuracy and stability of the internal clock can be guaranteed to improve the accuracy and stability of the output clock signal.

[0072] Optionally, the controller 111 is further used to connect to the GPS module 14 through a UART interface (such as the UART2 interface in Figure 6 ) to receive TOD information, so that the computer or mobile terminal connected to the communication extension device 10 automatically aligns the time according to the TOD information, realizing automatic calibration of the local clock.

[0073] Optionally, the controller 111 is further configured to connect to the first set of optical fiber interfaces, and respectively connect to multiple RUs through the first set of optical fiber interfaces to implement network communication with the multiple RUs. The first set of optical fiber interfaces includes multiple optical fiber interfaces, and the specific number of settings thereof is not limited herein and can be set accordingly according to actual requirements. For example, the GSERC0-GSERC3 units of the controller 111 are correspondingly connected to the first PHY chip 113 through 4 groups of 2*25G rate SGMII interfaces to input communication data to the first PHY chip 113, and the first PHY chip 113 outputs 8 pairs of 25G rate serdes signals to the first set of optical fiber interfaces. Thus, the first set of optical fiber interfaces includes 8 optical fiber interfaces (8*1cage), and the communication rate of each optical fiber interface is 25 Gbps. The 8 optical fiber interfaces are respectively connected to 8 RUs to implement data communication between the communication expansion device 10 and the RUs. The twsi2 unit of the controller 111 is configured to connect to the first set of optical fiber interfaces through IIC to configure parameters of each optical fiber interface in the first set of optical fiber interfaces.

[0074] Optionally, the controller 111 is further configured to connect to the second set of optical fiber interfaces, and respectively connect to the CU and other DUs through the second set of optical fiber interfaces to implement network communication with the CU and other DUs. The second set of optical fiber interfaces includes multiple optical fiber interfaces, and the specific number of settings thereof is not limited herein and can be set accordingly according to actual requirements. For example, the GSERC0 unit of the controller 111 is connected to the second set of optical fiber interfaces to input 2*25G rate serdes signals to the second set of optical fiber interfaces to implement network communication; the second set of optical fiber interfaces includes 2 optical fiber interfaces, and the communication rate of each optical fiber interface is 25 Gbps; one of the 2 optical fiber interfaces is connected to the CU, and the other optical fiber interface is connected to other DUs. The twsi3 unit of the controller 111 is configured to connect to the second set of optical fiber interfaces through the IIC interface to configure parameters of the second set of optical fiber interfaces.

[0075] Optionally, the controller 111 is further configured to configure the connected computer or terminal to work with SPI flash, 8GB of DDR4, and 32GB of EMMC, that is, the controller 111 can correspondingly configure basic parameters of connected devices such as terminals.

[0076] Based on the distributed communication unit 11 provided in this embodiment, the controller 111, the clock matrix synchronization chip 112, and the high-speed PHY chip are integrated into an SoC circuit architecture. It can realize the communication expansion in the 5G communication process with only one controller 111, and complete the functions of data splitting, merging, and forwarding, thus achieving deep coverage of network signals in the 5G communication process, improving the network communication quality and user experience; moreover, the components in the distributed communication unit 11 are simple, low in cost, small in power consumption, and do not require complex programming work, saving human and material resources.

[0077] In several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and structure diagrams in the drawings show the possible architectures, functions, and operations of devices, methods, and computer program products according to multiple embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the part of the module, program segment, or code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the blocks may occur in a different order from that marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the structure diagram and / or flowchart, as well as the combination of blocks in the structure diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0078] In addition, each functional module or unit in various embodiments of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0079] When the above-mentioned functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs.

[0080] The above is only a specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered by the protection scope of the present invention.

Claims

1. A distributed communication unit, characterized in that, Including: A controller, a clock matrix synchronization chip, and a first PHY chip; The clock matrix synchronization chip is used to connect to a GPS module, receive the 1PPS signal output by the GPS module, and send a clock signal to the controller according to the 1PPS signal; The controller is connected to the clock matrix synchronization chip and is used to receive the clock signal; the clock signal includes an LVDS clock signal and an LVCMOS clock signal; The controller is further connected to the first PHY chip and is used to send communication data to the first PHY chip with low latency according to the clock signal, so that the first PHY chip is used to perform high-speed network communication with the connected remote unit according to the communication data; The controller is further used to connect to a first group of optical fiber interfaces and respectively connect to a plurality of the remote units through the first group of optical fiber interfaces to realize network communication with the plurality of remote units.

2. The distributed communication unit according to claim 1, wherein The clock matrix synchronization chip inputs the LVDS clock signal to the controller through the REF CLK interface; The clock matrix synchronization chip further inputs the LVCMOS clock signal to the controller through the REN CLK interface; The clock matrix synchronization chip is further connected to the SPI_CS interface of the controller to realize data communication between the clock matrix synchronization chip and the controller; The clock matrix synchronization chip is further connected to the controller through the GPIO interface and is used to receive the enable signal sent by the controller to control the operation or stop of the clock matrix synchronization chip.

3. The distributed communication unit according to claim 1, characterized in that, It further includes a second PHY chip, and the second PHY chip is connected to the controller and is used to perform network communication with the connected external device to configure parameters of the external device.

4. The distributed communication unit according to claim 1, characterized in that The controller is further used to connect to a second group of optical fiber interfaces and respectively connect to a central unit and other distributed communication units through the second group of optical fiber interfaces to realize network communication with the central unit and the other distributed communication units.

5. A communication extension device, characterized in that, Including: A power supply module, a synchronization module, and the distributed communication unit according to any one of claims 1-4; The power supply module is respectively connected to the synchronization module and the distributed communication unit and is used to supply power to the synchronization module and the distributed communication unit; The distributed communication unit is connected to the synchronization module through a communication interface and is used to transmit synchronization information to the synchronization module; The synchronization module is used to connect to an electrical device through a POE interface, input synchronization information to the electrical device, and supply power to the electrical device.

6. The communication expansion device according to claim 5, characterized in that It further includes a GPS module, and the GPS module is connected to the clock matrix synchronization chip in the distributed communication unit through a communication interface and is used to transmit a 1PPS signal to the clock matrix synchronization chip, so that the clock matrix synchronization chip inputs a clock signal to the controller according to the 1PPS signal; The communication interface between the GPS module and the clock matrix synchronization chip is an SGMII interface.

7. The communication expansion device according to claim 5, characterized in that, The synchronization module is a switch with PSE function or a module including a PSE controller and a switch.

8. The communication expansion device according to claim 6, wherein, The GPS module is also used to connect to a GPS antenna to receive satellite signals and input clock signals to the clock matrix synchronization chip through the satellite signals; The GPS module is connected to the controller through a UART interface and is used to input TOD information to the controller through the satellite signals.

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