Method for starting up a system on chip without a read-only memory, a system on chip without a read-only memory, and a headset

Abstract

A method for starting a system on chip (SoC) without a read-only memory (ROM), comprising the following steps: receiving (S1) a reset signal by a processor (10) included in the SoC, monitoring (S2) a connection (12) between the processor and at least a non-volatile memory (11) by a monitoring component included in the SoC, both the processor and the non-volatile memory being included in the SoC, when the processor first reads (S3) the non-volatile memory through the connection, checking (S4) by the monitoring component whether a data value (DV1) returned in response to the first read access through the connection meets a preset value, and if the returned data value is different from the preset value, stopping (55) the operation of the processor by the monitoring component.

Description

Technical Field

[0001] The present disclosure relates to the field of system on chip (SoC). In particular, it relates to the field of SoC without read-only memory (ROM), also known as ROM-less SoC. More specifically, the present application relates to a method for booting a ROM-less SoC, a ROM-less SoC, and a headset. Background Art

[0002] As integrated circuit technology advances, the number of functions that can be integrated onto an integrated circuit chip increases. An integrated circuit chip on which a processor, on-chip memory, and other components are disposed is referred to as a system-on-chip (SoC) device. An SoC device may generally refer to any chip that includes an integrated circuit chip or chip arrangement enclosed in a package and on which at least one processor and on-chip memory are disposed. On-chip memory refers to a memory device installed in the same chip as the processor and possibly other components.

[0003] In the prior art, there are different types of SoCs. On the one hand, there are SoCs with on-chip ROM and flash memory. On the other hand, there are ROMless SoCs, which only have flash memory. In the original SoCs (i.e. directly after their production but before the content of the flash memory is tested), the flash memory may be in an unprogrammed and therefore undefined state. Potentially executing such uninitialized program code in the flash memory may lead to undesirable behavior, which in the worst case may prohibit programming the flash memory during the first test after production. A known solution to this problem is to start the processor of the SoC from the on-chip boot ROM, for example by implementing a boot loader in the ROM, which verifies the validity of the content of the flash memory before executing the processor to use the instructions stored in the flash memory. However, such a solution is not suitable for ROMless SoCs. Summary of the invention

[0004] Therefore, it can be seen that an object of the present disclosure is to provide a method for booting a SoC without a ROM and a SoC without a ROM, and a headset, which avoids the execution of an uninitialized program code stored in a flash memory of the SoC.

[0005] This object is achieved by the subject matter of the independent claims. Embodiments and developments are defined in the dependent claims.

[0006] In one embodiment, a method for booting a SoC without a ROM includes the following steps:

[0007] The processor included in the SoC receives a reset signal,

[0008] Monitoring a connection between a processor and at least one non-volatile memory by a monitoring component included in the SoC, wherein both the processor and the non-volatile memory are included in the SoC,

[0009] When the processor accesses the non-volatile memory through the connection for the first time, the monitoring component checks whether the data value returned in response to the first read access through the connection meets the preset value, and

[0010] If the returned data value is different from the preset value, the operation of the processor is stopped through the monitoring component.

[0011] Once the processor receives a reset signal from the outside, the monitoring component starts operating and observes the connection between the processor and the non-volatile memory. When the monitoring component detects that the processor reads and accesses the memory for the first time, the monitoring component checks whether the data value returned in response to the first read access matches the preset value. In the case where the returned value is different from the preset value, that is, the expected value, the monitoring component stops the processor operation.

[0012] Determining that the data value returned in response to the first read access is different from the preset value indicates that uninitialized code exists in the non-volatile memory. Therefore, by stopping the processor operation after such determination, the execution of uninitialized code stored in the non-volatile memory, such as flash memory, by the processor of the SoC is avoided. Thus, the advantages of a ROMless SoC with reduced chip area, shortened system startup time, and shortened test time due to the elimination of ROM can be fully utilized.

[0013] Unless stated otherwise, the definitions of terms provided above also apply in the following text.

[0014] Non-volatile memory can also be called persistent memory. Even if non-volatile memory is powered off, it still retains its stored contents.

[0015] The processor of the SoC may also be referred to as a microprocessor or a central processing unit (CPU). The processor may be implemented, for example, by an ARM processor. Here, the concept of startup refers to the first operation of the SoC without ROM (i.e., ROMless SoC) directly after its production.

[0016] In one refinement, stopping the processor operation, by the monitoring component, includes discarding, by the monitoring component, the returned data value, and providing, by the monitoring component, the processor with machine executable instructions that cause the processor to stop operation.

[0017] In the event that invalid memory content has been detected during the first read access, the returned data value is replaced by an instruction to halt the processor, thereby ensuring that invalid code of the non-volatile memory is inhibited from being executed on the processor.

[0018] In one refinement, the first read access by the processor is addressed to address zero in the non-volatile memory.

[0019] The first read access is therefore recognized by being directed to address zero in the non-volatile memory and is clearly identified by the monitoring component.

[0020] In one embodiment, the preset value represents an initial stack pointer value used by the processor.

[0021] For SoCs, it is common practice that the data value returned in response to the processor's first read access in normal operation is the initialization value of the stack pointer.

[0022] In an improved solution, the initial stack pointer value is equal to the address of the last word of the volatile memory included in the SoC. In particular, the initial stack pointer value is equal to 0x2001FFFC.

[0023] As known to those skilled in the art, each SoC and the SoC has a volatile memory, such as a random access memory (RAM), which has a known size, such as 128kB. In one embodiment, the RAM is mapped to a defined address of the processor's memory. The stack pointer points to the last word in the RAM memory built into the SoC. In an exemplary design, the default stack pointer initialization value is 0x2001FFFC.

[0024] In an improved solution, the method further comprises:

[0025] If the returned value is consistent with the preset value, the processor operation continues.

[0026] In the event that the returned value is the correct initial stack pointer value, the processor continues operation.

[0027] The method ensures that when the SoC is first started after its production, the processor is prohibited from executing uninitialized, i.e. undefined random code that may be in the non-volatile memory of the SoC. This applies not only to erased memory cells with value F, but more importantly, also to random values.

[0028] In one embodiment, a SoC without ROM includes a processor, a non-volatile memory, a connection, and a monitoring component. The connection is configured to connect the processor and at least the non-volatile memory. The processor is configured to receive a reset signal and implement at least one read access to the non-volatile memory through the connection. The monitoring component is configured to monitor the connection between the processor and the non-volatile memory, and when the processor first reads the non-volatile memory, check whether the data value returned in response to the first read access through the connection meets the preset value, and if the returned data value is different from the preset value, stop the processor operation.

[0029] After receiving a reset signal from outside the SoC, the processor performs a first read access to the non-volatile memory using the connection. The monitoring component monitors the connection and detects the first read access. It then checks whether the data value returned in response to the first read access matches a preset value. If it determines that the returned value is different from the preset value, the monitoring component stops the processor operation.

[0030] The monitoring component thus identifies invalid code in the non-volatile memory during the first read access of the processor of the ROM-free SoC after its production. In such a case, the processor is stopped from further operation. The execution of invalid and uninitialized code in the non-volatile memory is thus prohibited.

[0031] The above-described method may be implemented in the claimed SoC.

[0032] In a refinement, the connection is implemented as a bus connection between an instruction port of the processor and the non-volatile memory.

[0033] The bus connection may be a point-to-point connection. The bus may thus be implemented in a basic manner, with only one slave and one master, without arbitration and encoding / decoding. In the case of a processor of a SoC implemented with an ARM processor, for example an Advanced High Performance Bus (AHB) may be used as a bus connection. Optionally, the bus has more than one slave and / or more than one master.

[0034] In one refinement, the non-volatile memory is implemented as a flash memory.

[0035] The flash memory is built into the SoC and is programmed with the firmware image during the first boot of the SoC after its manufacture when the monitoring component determines that the returned value matches the preset value and the processor operation continues.

[0036] In one refinement, the monitoring unit includes a finite state machine and a multiplexer component. The finite state machine is configured to start operation when a reset signal occurs, control the multiplexer component, at least receive a returned data value from a connection, evaluate the returned data value received from the connection, and thereby determine whether a first read access of the processor to the non-volatile memory has occurred and whether the returned data value matches a preset value, and if it is determined that the first read access has occurred and the returned data value does not match the preset value, the finite state machine is configured to provide a replacement value to the multiplexer component. The multiplexer component is configured to receive the replacement value and receive the data value from the connection, and under the control of the finite state machine, provide the processor through the connection with either the returned data value received from the connection or the replacement value.

[0037] In the case where the returned data value does not match the preset value for the expected initial value of the stack pointer, a replacement value is provided to the processor through the finite state machine and multiplexer components. Conversely, if the returned data value is the expected initial stack pointer value, the returned data value is provided to the processor.

[0038] In one refinement, the replacement value includes a machine executable instruction that causes the processor to halt.

[0039] Thus, in response to a first read access that would provide invalid code, the processor receives an instruction to stop processor operation. The machine executable instructions may put the processor to sleep (eg, via a wait event instruction).

[0040] In one refinement, the processor is configured to perform calculations for audio processing, in particular noise cancellation.

[0041] Thus, the SoC is designed for use in audio applications and can therefore be used for audio processing, especially noise cancellation.

[0042] In one embodiment, a headset has a SoC as described above.

[0043] In addition to prior art components known to those skilled in the art, such as speakers, feedforward microphones and error microphones, the headphones also utilize a ROMless SoC as described above, for example, for implementing noise cancellation. The headphones thus have the advantages of a ROMless SoC, namely reduced chip area, test time and system boot time, and at the same time avoid the execution of firmware on a processor built into the SoC when the firmware image is invalid. Noise cancellation is also called active noise reduction or ambient noise reduction, both of which are abbreviated as ANC. ANC generally utilizes a recording of ambient noise, for example, processed by a processor of the SoC to generate an anti-noise signal, which is then combined with the useful audio signal to be played on the speakers of the headphones.

[0044] In a further development, the earphone is embodied as one of an in-ear earphone, a supra-aural earphone or an over-ear earphone. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Hereinafter, with reference to the accompanying drawings, the proposed method for booting a SoC without a ROM, the proposed SoC without a ROM, and the proposed earphone are explained in detail using exemplary embodiments. Functionally identical components and circuit elements or having the same effect have the same reference numerals. When circuit components or components functionally correspond to each other, they will not be repeatedly described in each of the following drawings.

[0046] in:

[0047] Figure 1 An embodiment of the proposed method for booting a SoC without a ROM is shown;

[0048] Figure 2 shows a first embodiment of the proposed SoC without ROM,

[0049] Figure 3 A second embodiment of the proposed SoC without ROM is shown,

[0050] Figure 4 Another embodiment of the proposed method for booting a SoC without ROM is shown,

[0051] Figure 5 An embodiment of the proposed headset is shown. DETAILED DESCRIPTION

[0052] Figure 1 An embodiment of the proposed method for booting a SoC without ROM is shown. The method comprises the following steps:

[0053] In step S1, a reset signal is received by a processor included in the SoC.

[0054] In step S2, a connection between a processor and a non-volatile memory is monitored by a monitoring component included in the SoC, wherein both the processor and the non-volatile memory are included in the SoC.

[0055] If the monitoring component does detect in step S3 the first read access of the processor to the non-volatile memory through the connection, in step S4, the monitoring component checks whether the data value returned in response to the first read access through the connection meets the preset value, and

[0056] If the returned data value is different from the preset value, in step S5, the processor operation is stopped by the monitoring component.

[0057] Through Figure 1 The proposed method described avoids the execution of invalid code stored in the non-volatile memory of a ROM-less SoC during the first boot of the SoC that has just been manufactured and powered on for the first time by a reset signal. The monitoring component monitors the connection extending between the processor and at least the non-volatile memory of the SoC for the first read access to the processor, and invades the connection to check again whether the returned data value meets the preset value. In the case that the returned data value does not match the preset value, the processor operation is stopped by the monitoring component to prevent the execution of invalid code.

[0058] Optionally, the method further comprises step S6, in which, when the returned data value is consistent with a preset value, the processor continues to operate.

[0059] Figure 2 A first embodiment of the proposed SoC without ROM is shown. The SoC 100 includes a processor 10, a non-volatile memory 11, a connection 12 configured to connect the processor 10 and at least the non-volatile memory 11, and a monitoring component 13. The processor 10 is configured to receive a reset signal SR and implement at least one read access to the non-volatile memory 11 through the connection 12. The monitoring component 13 is configured to monitor the connection 12 between the processor 10 and the non-volatile memory 11. In detail, when the first read access of the processor 10 to the non-volatile memory 11 occurs, the monitoring component 13 is configured to detect whether the data value returned in response to the first read access through the connection 12 meets the preset value. If the returned data value is different from the preset value, the monitoring component 13 is configured to stop the operation of the processor 10.

[0060] In one implementation example, connection 12 is implemented as a bus connection connecting an instruction port of processor 10 with non-volatile memory 11, which is implemented as a flash memory and represents the instruction memory of the SoC. Connection 12 can therefore be called an instruction bus of processor 10.

[0061] In an exemplary embodiment, the instruction bus may be operated according to the AHB protocol. The determination of the first read access to the processor 10 is implemented either by counting read accesses on the instruction bus or by checking the addresses involved. In the case where the processor 10 is implemented using an ARM processor, the first instruction bus access occurs from the zero address. In most applications using ARM processors, the preset value that meets the expected value returned by the system loaded from the flash memory points to the last word of the volatile memory, RAM memory, which is also built into the SoC. In an exemplary design, the RAM is mapped to address 0x20000000 according to the recommended memory map of the processor vendor and has a size of 128kB. Therefore, the preset value for the expected value for the stack pointer initialization is 0x2001FFFC. The monitoring component 13 checks the value returned from the zero address. If the value is different from the expected initialization value of the stack pointer, the monitoring component 13 stops further operation of the processor, thereby avoiding the execution of invalid code that happens to be contained in the flash memory 11.

[0062] Figure 3 A second embodiment of the proposed SoC without ROM is shown. Figure 3 Examples and Figure 2 The embodiment of the present invention is consistent with that of the present invention, and shows the feasible components of the monitoring component 13 in more detail. The monitoring component 13 includes a finite state machine 131 and a multiplexer component 132. The finite state machine 131 is configured to start operation when a reset signal SR occurs. It is also operable to control the multiplexer component 132 through a control signal SP. The finite state machine 131 is also operable to receive at least the returned data value DV1 from the connection 12 to evaluate the returned data value DV1 and thereby determine whether the first read access of the processor 10 to the non-volatile memory 11 has occurred, and whether the returned data value DV1 meets the preset value. If it is determined in the finite state machine 131 that the first read access has occurred and the returned data value DV1 does not meet the preset value, the finite state machine 131 is operable to provide the replacement value DV2 to the multiplexer component 132. The multiplexer component 132 is configured to receive the replacement value DV2 from the finite state machine 131 and receive the returned data value DV1 from the connection 12. In accordance with a control signal SP provided by the finite state machine 131 , the multiplexer component 132 provides either the returned data value DV1 or the replacement value DV2 to the processor 10 using the connection 12 .

[0063] Thus, if the finite state machine 131 detects that the returned data value DV1 does not match the preset value, the finite state machine 131 provides the replacement value DV2 to the multiplexer component 132 and instructs the multiplexer component 132 to provide the replacement value DV2 to the processor 10 through the control signal SP. The replacement value DV2 includes, for example, a machine executable instruction to set the processor 10 to sleep. In one embodiment, the monitoring component 13 replaces the subsequent vector acquisition with 0x00010001 in this manner, where the trailing 1 indicates a certain code in a given SoC processor, and replaces the instruction acquisition from address 0x00010000 with an instruction to halt the processor, such as a wait event instruction.

[0064] Figure 4 Another embodiment of the proposed method for starting a SoC without a ROM is shown. Figure 1 The embodiments described are consistent with and may be considered as previously referred to Figure 3 An embodiment of the finite state machine described. In step S1, upon receiving a reset signal, a state variable called FlashValid is initialized to "not set", i.e., the flash memory is valid and has a value of "not set". The FlashValid variable indicates whether the first read access has occurred and whether the returned data value meets the preset value. As known to those skilled in the art, this can be implemented using two bits indicating.

[0065] In step S2, a connection between the processor and the non-volatile memory is monitored, thereby waiting for a read operation or a read access to occur on said connection.

[0066] In step S3, when such a read operation occurs, the value of the flash valid variable is checked to determine whether the read operation is actually the first read access of the processor to the non-volatile memory. In the case where the value of the flash valid variable is "not set", the read operation is actually the first read access, and then step S4 is performed. In step S4, it is checked whether the data value referred to as the "return value" herein as the data value returned in response to the first read access through the connection meets the preset value. If the result of this check is "yes", the processor operation continues. Here, in step S61, the flash valid variable is set to "yes", and in step S62, the data value read from the flash memory is transmitted to the processor, because the value has been determined to be valid. The result of the check in step S4 is "no", that is, the "return value" returned in response to the first read access is different from the preset value, and the method stops the processor operation. In detail, in step S51, the flash valid variable is set to "no", and in step S52, the replacement value is provided to the processor, which stops the processor operation.

[0067] Moreover, in the case where the value of the flash valid variable is determined to be "yes" in step S3, the method directly proceeds to step S62 to send the value read from the flash memory to the processor, because the previous read operation is not the first read access and the content of the flash memory has been approved in the previous iteration of the method.

[0068] In the event that the value of the flash valid variable is determined to be "no" in step S3, the current read operation is not the first read access and the contents of the flash memory have been evaluated to be invalid. The method continues with step S52 where further operation of the processor is stopped.

[0069] Figure 5 An embodiment of the proposed headset is shown. The headset 200 comprises a SoC 100. The SoC 100 corresponds to one of the above-described embodiments, wherein the processor 10 is specifically configured to perform calculations for audio processing. In particular, the audio processing relates to noise cancellation.

[0070] The earphone 200 can thus be implemented in various forms as one of an in-ear earphone (also called an in-ear headset), a supra-aural earphone (also called an on-ear headset), or an over-ear headset (also called a circum-aural headset). An in-ear headset is worn like an earplug. A supra-aural headset has a cushion against the ear, while an over-ear headset has a round or oval ear cushion that wraps around the ear.

[0071] It is to be understood that any feature described with respect to any embodiment may be used alone or in combination with other described features, and may also be used in combination with one or more features of any other embodiment or any combination of any other embodiments, unless described as an alternative. Furthermore, equivalents and modifications not described above may also be utilized without departing from the scope of the method for booting a SoC without ROM and the SoC without ROM as defined in the appended claims.

[0072] Reference numerals

[0073] 10 Processor

[0074] 11 Non-volatile memory

[0075] 12. Connect

[0076] 13 Monitoring Components

[0077] 131 Finite State Machine

[0078] 132 Multiplexer Components

[0079] 100 SoC without ROM

[0080] 200 Headphones

[0081] SR, SP signals

[0082] DV1, DV2 values

[0083] Steps S1, S2, ...S6

Claims

1. A method for starting a system on chip (SoC) without a read-only memory (ROM), comprising the following steps: Receiving a reset signal through a processor included in the SoC, monitoring, by a monitoring component included in the SoC, a connection between the processor and at least a non-volatile memory, both of which are included in the SoC, When the processor accesses the non-volatile memory for the first time through the connection, the monitoring component checks whether the data value returned in response to the first read access through the connection meets the preset value, and If the returned data value is different from the preset value, the operation of the processor is stopped by the monitoring component, wherein the first read access is the first read access of the processor directly after SoC production.

2. The method according to claim 1, in, Stopping the operation of the processor, by the monitoring component, includes discarding the returned data value by the monitoring component and providing the processor with machine executable instructions, by the monitoring component, that cause the processor to stop operating.

3. The method according to claim 1 or 2, in, A first read access by the processor is addressed to address zero in the non-volatile memory.

4. The method according to claim 1 or 2, in, The preset value represents an initial stack pointer value used by the processor.

5. The method according to claim 4, in, The initial stack pointer value is equal to the address of the last word of the volatile memory included in the SoC.

6. The method according to claim 1 or 2, further comprising If the returned data value is consistent with the preset value, the operation of the processor continues.

7. The method according to claim 5, in, The initial stack pointer value is equal to 0x2001FFFC.

8. A system on chip SoC without a read-only memory ROM, comprising processor, Non-volatile memory, a connection configured to connect the processor and at least the non-volatile memory, and Monitoring components, in, The processor is configured to receive a reset signal and to perform at least one read access to the non-volatile memory via the connection, and The monitoring component is configured to monitor the connection between the processor and the non-volatile memory, and when the processor reads and accesses the non-volatile memory for the first time, check whether the data value returned in response to the first read access through the connection meets the preset value, and if the returned data value is different from the preset value, stop the processor operation, wherein the first read access is the first read access of the processor directly after the SoC is produced.

9. The SoC according to claim 8, in, The connection is implemented as a bus connection between an instruction port of the processor and the non-volatile memory.

10. The SoC according to claim 8 or 9, in, The non-volatile memory is implemented as a flash memory.

11. The SoC according to claim 8 or 9, in, The monitoring component includes a finite state machine and a multiplexer component, wherein the finite state machine is configured to initiate operation upon occurrence of the reset signal, control the multiplexer component, at least receive the returned data value from the connection, evaluate the returned data value received from the connection, and thereby determine whether a first read access of the processor to the non-volatile memory has occurred and whether the returned data value matches the preset value, and if it is determined that a first read access has occurred and the returned data value does not match the preset value, the finite state machine is configured to provide a replacement value to the multiplexer component, and The multiplexer component is configured to receive the replacement value and the returned data value from the connection, and under control of the finite state machine, provide either the returned data value received from the connection or the replacement value to the processor via the connection.

12. The SoC according to claim 11, in, The replacement values ​​include machine executable instructions that cause the processor to halt.

13. The SoC according to claim 8 or 9, in, The processor is configured to perform calculations for audio processing.

14. The SoC according to claim 13, in, The processor is configured to perform calculations for noise cancellation.

15. An earphone having the SoC according to claim 13.

16. The headset according to claim 15, in, The earphone is implemented as one of an in-ear earphone, a supra-aural earphone or an over-ear earphone.

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