Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device (100) is described, comprising: a carrier (1); at least one semiconductor chip (2) disposed on the carrier (1) and having at least one first electrical contact (11) on a main surface of the semiconductor chip (2) opposite to the carrier (1). The semiconductor device includes an electrically insulating layer (3) disposed on the carrier (1) and at least one electrically connecting layer (4), the at least one electrically connecting layer being guided through the electrically insulating layer (3) to the first electrical contact (11), wherein the electrically insulating layer (3) has a photostructureable material. Furthermore, a method for manufacturing the semiconductor device (100) is described.

Description

Technical Field

[0001] This application relates to a semiconductor device and a method for manufacturing the same. The semiconductor device may in particular be an optoelectronic semiconductor device, such as an LED or an LED display.

[0002] This patent application claims priority to German Patent Application No. 10 2019 220 378.7, the disclosure of which is incorporated herein by reference. Background Technology

[0003] JPH11191642A discloses a semiconductor light-emitting element, a semiconductor light-emitting module, and a method for manufacturing the same. US2010276722A discloses an optoelectronic semiconductor chip, an optoelectronic component, and a method for manufacturing the optoelectronic component. US2012104450A1 discloses a light-emitting diode light emitter with a transparent electrical connector. US2010032707A1 discloses a mounting structure for an electronic component and a method for manufacturing the same. All of these documents achieve semiconductor side insulation. Summary of the Invention

[0004] The task to be addressed is to describe a semiconductor device and a method for manufacturing the same, wherein the semiconductor device is characterized by high reliability and the method is characterized by low manufacturing cost.

[0005] These tasks are accomplished by the semiconductor device and the method for manufacturing the semiconductor device according to this application.

[0006] According to at least one embodiment, the semiconductor device includes a carrier and at least one semiconductor chip disposed on the carrier. The semiconductor device may in particular be an optoelectronic device, such as an LED, an LED module, or an LED display. The at least one semiconductor chip may in particular be a light-emitting diode chip. In a preferred design, multiple semiconductor chips are disposed on the carrier.

[0007] The at least one semiconductor chip has a first electrical contact on a main surface facing away from the carrier. A second electrical contact of the semiconductor chip may, for example, be disposed on the main surface of the semiconductor chip facing the carrier. Alternatively, both the first and second electrical contacts of the semiconductor chip may be disposed on the main surface of the semiconductor chip facing away from the carrier.

[0008] According to at least one embodiment, the semiconductor device includes an electrically insulating layer disposed on the carrier. The phrase "above" or "on" another layer or element can, here and hereinafter, mean that the layer or element is disposed directly on the other layer or element in direct mechanical and / or electrical contact. Furthermore, it can also mean that the layer or element is disposed indirectly on or above the other layer or element. Thus, additional layers and / or elements can be disposed between the layer and the other layer or between the element and the other element.

[0009] The electrically insulating layer may, in particular, cover the side surface of the at least one semiconductor chip. The thickness of the electrically insulating layer is preferably substantially the same as the height of the at least one semiconductor chip, for example, with a tolerance of up to 5% or 10%. The electrically insulating layer may, in particular, terminate substantially flush with the main surface of the semiconductor chip facing away from the carrier, on which a first electrical contact is arranged. The electrically insulating layer preferably comprises a plastic material.

[0010] According to at least one embodiment, the semiconductor device includes at least one electrical connection layer that is guided to the first electrical contact through the electrical insulating layer. The electrical insulating layer insulates the electrical connection layer, particularly from the sides of the semiconductor chip, and thus prevents short circuits. Preferably, the electrical connection layer is applied to the electrical insulating layer using a coating method such as electroplating. The electrical connection layer is, for example, made of a metal (particularly copper) or a metal alloy.

[0011] According to at least one embodiment, the electrical insulating layer has a photostructureable material.

[0012] This allows for the creation of openings in the electrically insulating layer, such as through-holes, using photolithography—that is, by exposing and subsequently removing exposed or unexposed areas of the electrically insulating layer. The electrically insulating layer can be fabricated with, for example, a high positioning accuracy of less than ±10 μm using photolithography.

[0013] An optically structurable electrically insulating layer can be selectively applied to a predetermined area of ​​the carrier, for example, to insulate the sides of a semiconductor chip and enable the application of an electrical connection layer to create a wireless contact. The semiconductor device, in particular, does not have bonding wires; instead, it contacts at least one semiconductor chip on a main surface opposite to the carrier via the electrical connection layer. This contact is characterized by its low height and is also known as a planar contact.

[0014] Using photostructureable layers as electrical insulating layers has the particular advantage of avoiding the need for molding methods, especially film-assisted molding (FAM), in the semiconductor device. When using molding methods, there is a risk of unintentional electrical insulating material reaching the semiconductor chip surface. This can lead to light loss or even disconnection of electrical contacts. In the case of molding methods, unintentionally generated material residues (e.g., burrs) usually must be removed in an additional process (deflashing). However, this process carries the risk of damaging the semiconductor chip surface. In the case of the semiconductor chip described herein, by using photostructureable materials and avoiding molding, the aforementioned process-related risks associated with the molding process are advantageously avoided.

[0015] According to at least one embodiment, the photostructureable material is a flowable material. The advantage of this is that the electrically insulating layer can be applied in a simple manner, for example, by spray coating, and subsequently structured by photolithography. The height difference between semiconductor chips is not a problem when applying the electrically insulating layer, compared to manufacturing it by molding.

[0016] According to at least one embodiment, the at least one electrical connection layer is guided from the plane of the carrier to the first electrical contact through the electrical insulation layer. For example, the first electrical contact is connected to a connection contact on the plane of the carrier via the electrical connection layer. For example, the carrier may have at least one printed conductor, wherein the at least one electrical connection layer is guided from the printed conductor to the first electrical contact through the electrical insulation layer. The electrical insulation layer may be in the form of a ramp that overcomes the height difference between the plane of the carrier and the plane of the first electrical contact.

[0017] According to at least one embodiment, an opening is formed in the electrically insulating layer, wherein a portion of the electrical connection layer is guided through the sidewall of the opening. The opening can, in particular, be guided from a carrier plane to a first electrical contact plane. The semiconductor device can, in particular, have a first contact plane at the height of the first electrical contact of at least one semiconductor chip and a second contact plane at the height of the carrier. In this case, the electrical connection layer guided through the sidewall of the opening can form a through contact between the first and second contact planes.

[0018] According to at least one embodiment, the opening has a width of at least 10 μm, preferably at least 50 μm, and particularly preferably at least 100 μm. The width of the opening is, for example, between 10 μm and 200 μm. An opening with a diameter of at least 10 μm, preferably at least 50 μm, and particularly preferably at least 100 μm is advantageous for the application of the electrical connection layer. The application of the electrical connection layer is preferably performed using an electroplating method.

[0019] According to at least one embodiment, the sidewalls of the opening extend obliquely, such that the cross-section of the opening increases from the carrier. This further simplifies the application of the electrical connection layer.

[0020] According to at least one embodiment, a plurality of semiconductor chips are arranged on the carrier, wherein the electrically insulating layer at least partially fills the gaps between the semiconductor chips. This advantageously allows a first contact plane to be formed at a height of the semiconductor chips away from the main surface of the carrier. A second contact plane may be arranged at the height of the carrier and, for example, included in printed wires on the carrier. The electrically insulating layer may advantageously at least partially planarize the gaps between the semiconductor chips.

[0021] According to at least one embodiment, the at least one semiconductor chip is a photoelectric semiconductor chip. In this case, the semiconductor device is a photoelectric semiconductor device. The at least one semiconductor chip may in particular be a light-emitting diode (LED) chip. The main surface of the semiconductor chip facing away from the carrier may in particular be the radiation-emitting surface of the LED chip. Multiple LED chips may be arranged on the carrier. In this case, the semiconductor device is, for example, an LED module or an LED display.

[0022] A method for manufacturing a semiconductor device is also described. According to at least one embodiment, in this method a carrier is provided and at least one semiconductor chip is disposed on the carrier, wherein at least one first electrical contact of the semiconductor chip is disposed on a main surface facing away from the carrier. For example, the carrier has at least one printed conductor, wherein a second electrical contact of the semiconductor chip facing the carrier is connected to the printed conductor via a conductive connection such as a solder layer or conductive adhesive.

[0023] According to at least one embodiment of the method, an electrically insulating layer is then applied to the carrier, wherein the electrically insulating layer has a photostructured material. For example, the electrically insulating layer may have a photoresist.

[0024] The electrically insulating layer is then photolithographically structured. In the case of positive photoresist, the area of ​​photoresist to be removed is exposed. Alternatively, in the case of negative photoresist, the area to be obtained is exposed. The electrically insulating layer can, for example, be structured such that it forms a ramp from the carrier plane to at least one semiconductor chip's main surface plane facing away from the carrier. Alternatively or additionally, one or more openings can be formed in the electrically insulating layer, the openings extending substantially vertically through the electrically insulating layer, for example.

[0025] According to at least one embodiment, in a further step, at least one electrical connection layer is applied to the electrical insulating layer, wherein the electrical connection layer is guided to the first electrical contact through the electrical insulating layer. For example, the carrier has at least one printed conductor, wherein the at least one electrical connection layer is guided from the printed conductor to the first electrical contact through the electrical insulating layer.

[0026] According to at least one embodiment of the method, the electrically insulating layer is applied using a spraying method. The electrically insulating layer is, in particular, a flowable layer. For example, the electrically insulating layer can be a photoresist that can be applied using a spraying method. Application using a spraying method has the advantage that, for example, in the case of multiple semiconductor chips with different heights arranged on the carrier, different topographic heights can be easily compensated for.

[0027] According to at least one embodiment, the application of the electrically insulating layer includes the application and photolithographic structuring of a first sublayer of the electrically insulating layer, followed by the application and photolithographic structuring of a second sublayer of the electrically insulating layer. Therefore, the application of the electrically insulating layer is performed in two steps. In this case, the main portion of the material of the electrically insulating layer can be applied when the first sublayer is applied. When the second sublayer is applied, a smaller portion of the electrically insulating layer material is applied onto the first sublayer. In this case, the total thickness of the electrically insulating layer can be adjusted very precisely when the relatively thin second sublayer is applied.

[0028] According to at least one embodiment, during the application of the first sublayer and photolithographic structuring, a gap no wider than 20 μm is created between the sidewall of the semiconductor chip and the first sublayer, wherein the gap is filled with a second sublayer.

[0029] With this design, the coverage area of ​​the semiconductor chip edge can be adjusted very precisely. In particular, it advantageously reduces the risk of curling edges formed on the chip edge. Such curling edges are detrimental to the subsequent application of electrical interconnect layers.

[0030] According to at least one embodiment, an opening is formed in the electrically insulating layer, wherein a portion of the electrically connecting layer is applied to the sidewall of the opening. The opening is advantageously formed by photolithography. Alternatively, the opening can be fabricated, for example, by laser beam drilling.

[0031] According to at least one embodiment, the electrical connection layer is manufactured by electroplating. The electrical connection layer is, for example, a copper layer.

[0032] Other advantageous improvements to the method are derived from the description of semiconductor devices, and vice versa. Attached Figure Description

[0033] The following is based on examples and... Figures 1 to 4 The invention will be explained in more detail below.

[0034] Figure 1 A schematic diagram of a cross-section of an example semiconductor device is shown.

[0035] Figure 2 A schematic perspective view showing another example of a semiconductor device is shown.

[0036] Figure 3 A schematic diagram of a cross-section of another example of a semiconductor device is shown, and

[0037] Figure 4 A schematic diagram of a cross-section of another example of a semiconductor device is shown.

[0038] Components that are identical or have the same function are given the same reference numerals in the figure. The size relationships between the components shown and the components described thereto should not be considered to be proportional. Detailed Implementation

[0039] exist Figure 1 The image shows a first example of a semiconductor device 100. In this example, the semiconductor device 100 is an optoelectronic device, particularly an LED device. The semiconductor device 100 has a semiconductor chip 2, which is a light-emitting diode chip. The semiconductor chip 2 has a semiconductor layer sequence 20, which includes, for example, an n-type semiconductor region 21, a p-type semiconductor region 23, and an active layer 22 disposed between the n-type semiconductor region 21 and the p-type semiconductor region 23.

[0040] The active layer 22 may in particular be an active layer that emits radiation. The active layer 22 may be constructed, for example, as a pn junction, a double heterostructure, a single quantum well structure, or a multiple quantum well structure. The term "quantum well structure" herein includes any structure in which charge carriers undergo quantization of their energy states through confinement. In particular, the term "quantum well structure" does not include any description of the quantization dimension. Therefore, the term specifically includes quantum wells, quantum wires, and quantum dots, as well as any combination of these structures.

[0041] The n-type semiconductor region 21, the p-type semiconductor region 23, and the active layer 22 may each include one or more semiconductor layers. The n-type semiconductor region 21 includes one or more n-type doped semiconductor layers, while the p-type semiconductor region 23 includes one or more p-type doped semiconductor layers. The n-type semiconductor region 21 and / or the p-type semiconductor region 23 may also include one or more undoped semiconductor layers.

[0042] In the illustrated example, the n-type semiconductor region 21 faces the carrier 1. However, reverse polarity is also possible.

[0043] The semiconductor layer sequence 20 of the semiconductor chip is preferably based on a III-V compound semiconductor material, particularly a nitrogen compound, phosphorus compound, or arsenic compound semiconductor material. For example, the semiconductor layer sequence may include In... x Al y Ga 1-x-y N、In x Al y Ga 1-x-y P or In x Al y Ga 1-x-y As, where 0≤x≤1, 0≤y≤1, and x+y≤1, respectively. Here, III-V compound semiconductor materials do not necessarily have to have a mathematically precise composition according to one of the above formulas. Instead, they can have one or more dopants and additional components. However, for simplicity, the above formulas only include the major components of the lattice, even if these components can be partially replaced by small amounts of other substances.

[0044] The semiconductor chip 2 has a first electrical contact 11 on the side facing away from the carrier. A second electrical contact 12 may be arranged on the side of the semiconductor chip 2 facing the carrier 1 and connected, for example, to printed wires on the carrier 1.

[0045] Semiconductor device 100 has a photostructureable electrically insulating layer 3 disposed on a carrier 1 and particularly adjacent to the side of a semiconductor chip 2. In manufacturing the semiconductor device, the electrically insulating layer 3 is advantageously applied using a spraying method. The electrically insulating layer 3 is, in particular, a flowable layer. For example, the electrically insulating layer 3 is a photoresist layer. The photostructureable electrically insulating layer 3 can be structured by exposure and subsequent development. In this way, for example, one or more openings can be formed in the electrically insulating layer 3, particularly for contact vias.

[0046] The first electrical contact 11 on the side of the semiconductor chip 2 facing away from the carrier 1 is contacted by the electrical connection layer 4, which is guided by the electrical insulating layer 3. In other words, the semiconductor chip 2 has a so-called planar contact without bonding lines.

[0047] The electrical insulating layer 3 may be in the form of a ramp that compensates for the height difference between the contact plane (e.g., the printed conductor 13 on the carrier 1) at the height of the carrier 1 and the main surface of the semiconductor chip 2 facing away from the carrier 1. The electrical insulating layer 3 specifically prevents short circuits on the sides of the semiconductor chip 2. A portion of the electrical insulating layer 3 may cover a portion of the main surface of the semiconductor chip 2 facing away from the carrier 1, particularly at the edge of the semiconductor chip 2. This prevents the electrical connection layer 4 from being directly guided through the chip edge of the semiconductor chip 2.

[0048] exist Figure 2 Another example of a semiconductor device 100 is shown. This is a semiconductor device having a plurality of semiconductor chips 2. In the example shown, specifically four semiconductor chips 2 are arranged on a common carrier 1. The semiconductor device 100 may in particular be an RGB light-emitting diode device, wherein the semiconductor chips 2 each have at least one semiconductor chip 2 for emitting red, green, and blue light. For example, an additional semiconductor chip 2 emitting green light or white light may be provided as a fourth semiconductor chip 2. The semiconductor chips 2 may form pixels of an LED display.

[0049] In this example, each semiconductor chip 2 is provided with a connection contact 14 at the height of the carrier 1. The connection contact 14 is connected to a first electrical contact on the main surface of the semiconductor chip 2 facing away from the carrier via an electrical connection layer 4, which is guided by an electrical insulating layer 3. In this case, the electrical insulating layer 3 is designed as a ramp to compensate for the height difference between the connection contact 14 and the upper side of the semiconductor chip 2. As in the previous example, the electrical insulating layer 3 is applied during manufacturing by a spraying method and subsequently structured by photolithography.

[0050] exist Figure 3Another example of a semiconductor device 100 is shown. The semiconductor device 100 has a semiconductor chip 2, for example, a light-emitting diode chip. The semiconductor chip 2 has a first electrical contact 11 on a main surface facing away from the carrier 1 and a second electrical contact 12 on a main surface facing the carrier 1. The second electrical contact 12 is connected, for example, to printed conductors 13 disposed on the carrier 1. The first electrical contact 11 is connected to an electrical connection layer 4, which is guided by electrically insulating layers 3A and 3B. In this example, the electrically insulating layers 3A and 3B have a first sublayer 3A and a second sublayer 3B disposed above the first sublayer. Advantageously, both the first sublayer 3A and the second sublayer 3B are photostructureable layers.

[0051] The two electrically insulating layers 3A and 3B are advantageously manufactured in a two-stage process in the method for manufacturing the semiconductor device 100. In the first step, the first sublayer 3A is preferably applied using a spraying method. The first sublayer 3A is then structured by photolithography. In this case, a gap is created between the sidewall of the semiconductor chip 2 and the first sublayer 3A. The gap preferably has a width between 5 μm and 20 μm.

[0052] Then, in the second step, a second sublayer 3B is applied over the first sublayer 3A, wherein the second sublayer 3B specifically fills the gap between the sidewalls of the semiconductor chip 2 and the first sublayer 3A. Like the first sublayer 3A, the second sublayer 3B is preferably applied using a spraying method. The second sublayer 3B can be structured by photolithography. A portion of the second sublayer 3B can cover a portion of the main surface of the semiconductor chip 2 facing away from the carrier. In particular, a portion of the second sublayer 3B can cover the upper edge of the semiconductor chip 2 to specifically avoid contact between the surface of the semiconductor chip 2 and the electrical connection layer 4 at the chip edge.

[0053] The two-stage process used in this example to manufacture the two electrical insulating layers 3A and 3B has the particular advantage that only a small amount of electrical insulating material needs to be applied when manufacturing the second sub-layer 3B. The amount of material to be applied is particularly small because only the narrow gap between the first sub-layer 3A and the sidewalls of the semiconductor chip 2 needs to be filled, where this gap is preferably only 5 μm to 20 μm wide. Since only a small amount of material is applied with the second sub-layer, the risk of curling of the electrical insulating material at the chip edges can be advantageously reduced. Such curling is disadvantageous for the subsequent application of the electrical connection layer 4.

[0054] In a further step, a capping layer 5 may be applied to the electrical connection layer 4 and / or the electrical insulating layers 3A, 3B. The capping layer 5 is preferably an electrical insulating layer. The capping layer 5 may, for example, be used to protect the electrical connection layer 4 from corrosion. Alternatively or additionally, if the semiconductor chip 2 is, for example, a light-emitting diode (LED) chip, the capping layer 5 may be used to increase contrast. In this case, the capping layer 5 may be, for example, a black varnish layer. In this case, the optoelectronic device region next to the radiating surface of the LED chip appears black and has a high contrast compared to the radiating surface that emits light during semiconductor device operation.

[0055] Figure 4 A cross-sectional view of another example of the semiconductor device 100 is shown. In this case, the semiconductor device 100 is an LED display, particularly an RGB-LED display. In the semiconductor device 100, groups of semiconductor chips 2A, 2B, and 2C are arranged on a carrier 1. Each group specifically includes a red-emitting semiconductor chip 2A, a green-emitting semiconductor chip 2B, and a blue-emitting semiconductor chip 2C. For example, the semiconductor chip groups respectively form pixels of the LED display.

[0056] Semiconductor chips 2A, 2B, and 2C each have a first electrical contact 11 on a main surface facing away from the carrier 1 and a second electrical contact 12 on a main surface facing the carrier 1. For example, the second electrical contact 12 is connected to the printed conductors 13 on the carrier 1 using a conductive adhesive 6 or alternatively using a solder layer. The carrier 1 may have one or more through contacts 7 to connect the printed conductors 13 on the upper side of the carrier 1 to the printed conductors 8 on the lower side of the carrier 1.

[0057] Electrically insulating layers 3A and 3B are disposed on the carrier 1. As in the previous example, the electrically insulating layers 3A and 3B have a first sublayer 3A and a second sublayer 3B. The first sublayer 3A of the electrically insulating layer preferably has a height substantially consistent with the height of the semiconductor chip 2. The first sublayer 3A can terminate flush with the main surface of the semiconductor chip 2 facing away from the carrier 1. The first sublayer 3A fills the gap between adjacent semiconductor chips 2. The second sublayer 3B is applied to the first sublayer 3A, and the second sublayer 3B can cover the chip edge of the semiconductor chip 2. The first sublayer 3A and the second sublayer 3B of the electrically insulating layers 3A and 3B are photostructured layers, and they are both photolithographically structured during the fabrication of the semiconductor device 100. Furthermore, the first sublayer 3A and the second sublayer 3B are advantageously flowable layers that can be applied using a spraying method.

[0058] The first electrical contact 11 of the semiconductor chip 2 is connected to the electrical connection layer 4, which is guided by the electrical insulating layers 3A and 3B. The electrical insulating layers 3A and 3B have openings 30. The electrical connection layer 4 is guided to the printed conductors 13 on the carrier 1 through the sidewalls of the openings. In this way, a conductive connection is created between the contact plane at the upper height of the semiconductor chip 2 and another contact plane at the height of the carrier 1.

[0059] The opening 30 in the electrical insulating layer preferably has a width between 50 μm and 200 μm, for example, about 100 μm. This roughly corresponds to the height of the semiconductor chip 2. The opening 30 preferably has an aspect ratio (height-to-width ratio) of no more than 2, and more preferably no more than 1. The opening 30 is advantageously manufactured by photolithography. Alternatively, the opening 30 in the electrical insulating layers 3A and 3B can be manufactured by laser beam drilling.

[0060] Advantageously, the opening 30 has sidewalls that extend at an angle, such that the cross-section of the opening 30 increases from the carrier. This facilitates the fabrication of the electrical connection layer 4 on the sidewalls of the opening 30. The opening 30 with such angled sidewalls can be fabricated by photolithography with appropriate exposure or by laser beam drilling.

[0061] The electrical connection layer 4 is preferably manufactured by electroplating. During manufacturing, for example, a growth layer (seed layer) is first applied, and then the electrical connection layer 4 is deposited by electroplating. For example, the electrical connection layer 4 may be made of copper or gold. These materials are characterized, in particular, by their good electrical conductivity. The electrical connection layer 4 can be structured using methods known per se.

[0062] A cover layer 5 can be applied to the areas of the electrical connection layer 4 and / or the electrical insulation layers 3A, 3B. This cover layer serves, for example, to prevent corrosion and / or improve contrast. The cover layer 5 is, for example, a black protective varnish. Furthermore, a transparent package 9, such as a silicon casting, can be applied to the semiconductor device. The transparent package 9 is particularly used as a protective layer for the semiconductor device 100.

[0063] This invention is not limited to the description based on the embodiments. Rather, the invention includes every new feature and every combination of features, particularly every combination of features in the claims, even if the feature or combination itself is not expressly described in the claims or embodiments.

[0064] List of reference numerals

[0065] 1. Carrier

[0066] 2 Semiconductor chips

[0067] 3 Electrical insulation layer

[0068] 4 Electrical connection layer

[0069] 5. Covering layer

[0070] 6. Conductive adhesives

[0071] 7. Through-contact section

[0072] 8 Printed wires

[0073] 9-pack

[0074] 11 First electrical contact

[0075] 12 Second electrical contact

[0076] 13 Printed wires

[0077] 14 Contact Department

[0078] 20 Semiconductor Layer Sequence

[0079] 21 n-type semiconductor region

[0080] 22 Active layer

[0081] 23 p-type semiconductor region

[0082] 30 Opening

[0083] 100 Semiconductor devices.

Claims

1. A semiconductor device, comprising - a carrier (1), - at least one semiconductor chip (2) arranged on the carrier (1) and having at least one first electrical contact (11) on a main surface of the semiconductor chip (2) facing away from the carrier (1), - an electrically insulating layer (3) arranged on the carrier (1), and - at least one electrically connecting layer (4) guided through the electrically insulating layer (3) to the first electrical contact (11), wherein the electrically insulating layer (3) has a photostructurable material, wherein the electrically insulating layer (3) has a first sublayer (3A) and a second sublayer (3B) arranged above the first sublayer, both the first sublayer and the second sublayer being photostructurable layers.

2. The semiconductor device of claim 1, wherein, The photostructurable material is a flowable material.

3. The semiconductor device of any one of claims 1-2, wherein, The at least one electrically connecting layer (4) is guided through the electrically insulating layer (3) from a plane of the carrier (1) to the first electrical contact (11).

4. The semiconductor device according to any one of claims 1 to 2, wherein An opening (30) is formed in the electrically insulating layer (3), and wherein a portion of the electrically connecting layer (4) is guided through a sidewall of the opening (30).

5. The semiconductor device of claim 4, wherein, The opening (30) has a width of at least 10 pm.

6. The semiconductor device of claim 4, wherein, The sidewall of the opening (30) extends obliquely such that a cross section of the opening (30) increases starting from the carrier (1).

7. The semiconductor device of any one of claims 1 to 2, wherein, A plurality of semiconductor chips (2A, 2B, 2C) is arranged on the carrier (1), and wherein the electrically insulating layer (3) at least partially fills a gap between the semiconductor chips (2).

8. The semiconductor device of any one of claims 1 to 2, wherein, The at least one semiconductor chip (2) is an optoelectronic semiconductor chip.

9. A method for manufacturing a semiconductor device, comprising the steps of - arranging at least one semiconductor chip (2) on a carrier (1), wherein at least one first electrical contact (11) of the semiconductor chip is arranged on a main surface of the semiconductor chip (2) facing away from the carrier (1), - applying an electrically insulating layer (3) to the carrier, wherein the electrically insulating layer (3) has a photostructurable material, - photostructuring the electrically insulating layer (3), and - applying at least one electrically connecting layer (4) to the electrically insulating layer (3), wherein the electrically connecting layer (4) is guided through the electrically insulating layer (3) to the first electrical contact (11), wherein the applying of the electrically insulating layer (3) comprises an applying and a lithographically structuring of a first sublayer (3A) and a subsequent applying and a lithographically structuring of a second sublayer (3B).

10. The method of claim 9, wherein, The carrier (1) has at least one printed conductor (13), and wherein the at least one electrically connecting layer (4) is guided through the electrically insulating layer (3) from the printed conductor (13) to the first electrical contact (11).

11. The method of claim 9 or 10, wherein, The electrically insulating layer (3) is applied by a spray method.

12. The method of claim 9, wherein, A gap of no more than 20 pm wide is created between a side of the semiconductor chip (2) and the first sublayer (3A) by the applying and the lithographically structuring of the first sublayer (3A), wherein the gap is filled with the second sublayer (3B).

13. The method of any one of claims 9-10, wherein, An opening (30) is formed in the electrically insulating layer (3), and wherein a portion of the electrically connecting layer (4) is applied to the side wall of the opening (30).

14. The method of any one of claims 9-10, wherein, The electrically connecting layer (4) is produced galvanically.

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