A method and system for reordering effective key area parameter vector sets

Abstract

The present invention provides a method and system for reordering an effective critical area parameter vector set, including: obtaining a circuit description language of an integrated circuit under test, and using a test vector generation tool (ATPG) to generate a test vector set for the integrated circuit under test; injecting a fault into the analog circuit of the integrated circuit under test, obtaining and determining whether the integrated circuit under test has a fault based on the test response value currently in the analog circuit; referring to the structural diagram of the integrated circuit under test, processing the total critical area coverage of transistors contained in different unit circuits relative to the area of the unit circuit, counting the number of times each test vector in the test vector set hits a fault, processing the resultant value to obtain a test characteristic value, sorting and processing the test vectors according to the test characteristic value, and reordering the test vector set for testing the integrated circuit under test. The present invention solves the technical problems of high integrated circuit testing cost, low testing efficiency, and low testing accuracy.

Description

Technical Field

[0001] The present invention relates to an integrated circuit testing technology, and in particular to an effective key area parameter vector set reordering method and system. Background Art

[0002] With the rapid advancement of modern semiconductor technology, chips consisting of hundreds of millions of MOS transistors have become available. At the 2019 IEEE International Electron Devices Meeting (IEMD), chip giant Intel predicted that chip manufacturing process node technology would maintain a two-year leap. Large-scale circuit designs and shrinking feature sizes have led to an increased diversity of manufacturing defects and a decrease in yield, making it particularly difficult to control these properties. By the end of 2020, the overall chip performance variation rate had increased to 69%, directly leading to a sharp increase in the number of test vectors required for testing, a significant increase in automatic test equipment (ATE) testing time, and rising testing costs.

[0003] Currently, automated test equipment (ATE) is expensive, technologically demanding, and requires significant upgrade costs. However, with the rapid advancement of CMOS technology, the scale of chip manufacturing has increased, and the density and complexity of circuit components have continued to rise. As a result, the performance and technology of ATE far exceed the actual needs of chip testing. Therefore, only by broadening our thinking, innovating, optimizing test methods, and fully utilizing existing equipment can we improve the efficiency of faulty chip testing and effectively reduce testing costs.

[0004] Patent application number CN03802114.5, "Method and Apparatus for Transmitting Scan Patterns in Scan-Based Integrated Circuits," discloses a transmitter, system, and method for reducing the test data volume and test execution time of ATE (Automatic Test Equipment) in scan-based integrated circuits. The scan-based integrated circuit includes multiple scan chains, each of which includes multiple serially connected scan cells. The transmitter is a combinational logic network connected to any virtual scan controller and any scan connector. The virtual scan controller controls the operation of the transmitter. The system transmits virtual scan patterns stored in the ATE and generates transmission scan patterns through the transmitter for testing manufacturing errors in the integrated circuit. This effectively increases the number of scan chains available through the ATE. The method further reorders the scan cells in a selected scan chain to generate transmission scan patterns and virtual scan patterns, and synthesizes the transmitter and compaction tool in the scan-based integrated circuit. When the transmitter is implemented using a combinational logic network, the input constraints imposed by the transmitter allow only a subset of the scan cells to accept a predetermined logic value at any one time, which is equal to or complementary to the ATE output. Unlike the transmitter scan setups in prior literature that only allow all-zero and all-one patterns to be applied to transmitter channels, this existing patent allows different combinations of logic values to appear on these channels at different times. Generating these test patterns simply requires expanding the commonly used ATPG tools to implement these additional input restrictions. Therefore, the process of generating the transmission scan pattern will use an initial set of input restrictions to generate the pattern and analyze the obtained coverage. If the obtained fault coverage is unsatisfactory, a different set of input restrictions is applied and a new set of vectors is generated. This process is repeated until the predetermined restriction criteria are met. The aforementioned existing patent uses an ATPG tool to expand the test pattern to implement these additional input restrictions, while the present application reorders the test vectors without changing the fault coverage accuracy. The specific implementation method used for the test vector reordering in this patent is different from that used in the present application. In addition, this patent is applied to the scenario of reducing the fault coverage of a base scan design, which is also different from the application scenario of the technical solution of the present application.

[0005] In summary, the existing technology has technical problems of high testing cost, low testing efficiency and low testing accuracy. Summary of the Invention

[0006] The technical problem to be solved by the present invention is how to solve the technical problems of high integrated circuit testing cost, low testing efficiency and low testing accuracy.

[0007] The present invention solves the above technical problems by adopting the following technical solutions: a method for reordering an effective key area parameter vector set comprises:

[0008] S1. Obtain a circuit description language of an integrated circuit under test, describe the integrated circuit under test using a hardware description language, and generate a test vector set for the integrated circuit under test using a test vector generation tool ATPG;

[0009] S2. Perform fault injection on the analog circuit of the integrated circuit under test, obtain a test response value of the current integrated circuit under test, and compare the test response value with a test response value of a normal circuit to determine whether the integrated circuit under test has a fault;

[0010] S3. Referring to the structural diagram of the integrated circuit under test, processing the total critical area coverage of transistors contained in different unit circuits relative to the area coverage of the unit circuits, counting the number of times each test vector in the test vector set hits a fault, processing the counted number of times to obtain a test characteristic value, sorting and processing the test vectors according to the test characteristic value, and re-sorting the test vector set for testing the integrated circuit under test;

[0011] Including: S31, obtaining characteristic dimensions of various transistors in analog circuits;

[0012] S32, obtaining the proportion data of each circuit unit of the analog circuit;

[0013] S33, processing the structural diagram in the simulation circuit to obtain total critical area data of transistors of each unit circuit and unit circuit area data;

[0014] S34, processing the total critical area data of the transistors and the unit circuit area data to obtain relative area coverage data of different unit circuits in the tested integrated circuit;

[0015] S35, counting the number of hits of each test vector in the process of the simulated fault test performed on the analog circuit;

[0016] S36 , estimating the test characteristic value of each of the test vectors according to the number of hits, and sorting the test vectors according to the magnitude of the test characteristic value to obtain the re-sorted test vector set.

[0017] The present invention sorts test vector sets and uses the test vectors to hit each type of faulty unit circuit based on the total critical area of transistors contained in the circuit relative to the total area of the unit circuit. The present invention utilizes a test vector generation tool, ATPG, to generate a test vector set for the integrated circuit under test. This reduces the testing time for faulty chips, improves testing efficiency, and reduces testing costs without changing the accuracy of fault coverage. Furthermore, the present method exhibits better results in ultra-large-scale complex circuits.

[0018] In a more specific technical solution, step S1 includes:

[0019] S11, analyzing and modeling the internal structure of the integrated circuit under test, describing the internal structure in the circuit description language, and generating a corresponding analog circuit accordingly;

[0020] S12. Acquire test parameters of the analog circuit, and use the test vector generation tool ATPG to generate the test vector set.

[0021] In a more specific technical solution, step S11 includes:

[0022] S111, collecting internal structure data of the integrated circuit under test;

[0023] S112: Analyze the internal structure data, model the integrated circuit under test, and construct the analog circuit accordingly.

[0024] In a more specific technical solution, step S12 includes:

[0025] S121, obtaining test type data and parameters of the analog circuit;

[0026] S122, obtaining data parameters and requirements for each test type of the analog circuit;

[0027] S123 , inputting the data and parameters of the test type, and the data parameters and requirements in each test type into the test vector generation tool ATPG to generate the test vector set.

[0028] This method balances the imbalance between the unit circuit area and the total critical area of the transistors contained in some circuits, which can occur in some production process designs. This facilitates accurate classification research and more objectively achieves the testing goal of earlier fault detection using test vectors during testing. Furthermore, this method is entirely software-based and requires no additional hardware, reducing testing costs and ensuring feasibility.

[0029] In a more specific technical solution, step S2 includes:

[0030] S21. Obtaining differential preset fault injection parameters;

[0031] S22, inputting the different preset fault injection parameters into the simulation circuit to obtain different test response values;

[0032] S23. Determine whether the tested integrated circuit has a fault according to the test response value.

[0033] The present invention not only considers the impact of the fault environment in the circuit's periphery on the unit circuit, but also focuses on the possibility of all faults occurring within the unit circuit, and also considers the possibility of various physical faults occurring inside the transistor, comprehensively considering the problem of circuit complexity.

[0034] Without changing the accuracy of fault coverage, the present invention comprehensively considers the circuit complexity problem and reorders the test vectors according to the test characteristic value of each test vector, so as to achieve the purpose of reducing test time, improving test efficiency and reducing test cost.

[0035] In a more specific technical solution, in step S34, the test vectors are sorted in descending order.

[0036] The present invention sorts the test vectors according to the test quality from high to low, and preferentially loads the test vectors with better test quality in the test set, so that these test vectors can hit the fault earlier in the test process, thereby reducing the test time of the faulty integrated circuit, improving the test efficiency and reducing the test cost.

[0037] In a more specific technical solution, a method for reordering an effective key area parameter vector set further includes:

[0038] S1', inputting the test vector into automatic test equipment ATE;

[0039] S2′, measuring the reordered test vector set in sequence with the automatic test equipment ATE to complete the test of the integrated circuit under test.

[0040] Based on the characteristics and operating process of automated test equipment (ATE), the present invention shows that after each test vector is input into the ATE, the faults that the test vector can detect in the integrated circuit remain fixed and unchanged, and will not change due to changes in the test vector order. However, different test vectors may hit the same fault, and the number of faults hit by different test vectors may also vary. Therefore, the method of changing the order in which test vectors are loaded can be used to prioritize the loading of more high-quality test vectors. This can maintain the fault coverage of the original test set, significantly shorten fault detection time, and improve test efficiency.

[0041] In a more specific technical solution, in step S2 ′, when the test vector hits a fault in the integrated circuit under test, it is determined to screen out the chip corresponding to the current integrated circuit under test.

[0042] In a more specific technical solution, a system for reordering an effective key area parameter vector set includes:

[0043] A vector set generation module is used to obtain the circuit description language of the integrated circuit under test and use the test vector generation tool ATPG to generate a test vector set for the integrated circuit under test;

[0044] a fault injection module, configured to inject a fault into the analog circuit of the integrated circuit under test, obtain and determine whether the integrated circuit under test has a fault based on a test response value currently in the analog circuit, the fault injection module being connected to the vector set generation module;

[0045] a reordering module, configured to refer to the structural diagram of the integrated circuit under test, process the total critical area coverage of transistors contained in different unit circuits relative to the area coverage of the unit circuits, count the number of times each test vector in the test vector set hits a fault, obtain a test characteristic value based on the count, sort and process the test vectors according to the test characteristic value, and reorder the test vector set to test the integrated circuit under test, wherein the reordering module is connected to the fault injection module;

[0046] It includes: a characteristic size acquisition unit: used to obtain the characteristic sizes of various transistors in the analog circuit;

[0047] A circuit unit ratio obtaining unit is used to obtain the ratio data of each circuit unit of the analog circuit;

[0048] A transistor critical area and unit area processing unit: used for processing the structural diagram in the analog circuit to obtain the total critical area data of the transistors and the unit circuit area data of each unit circuit;

[0049] A relative area coverage calculation unit is configured to process the total critical area data of the transistor and the unit circuit area data to obtain relative area coverage data of different unit circuits in the tested integrated circuit;

[0050] A test vector hit count counting unit is used to count the hit count of each test vector in the process of simulated fault testing on the analog circuit;

[0051] A test vector reordering unit is configured to estimate the test characteristic value of each of the test vectors according to the number of hits, and sort the test vectors according to the magnitude of the test characteristic value to obtain the reordered test vector set.

[0052] This method offers the following advantages over existing technologies: By sorting a set of test vectors and then comparing the total critical area of transistors contained in each type of faulty unit circuit with the total area of the unit circuit, the method reduces the testing time for faulty chips, improves testing efficiency, and reduces testing costs without compromising the accuracy of fault coverage. Furthermore, this method demonstrates superior performance in ultra-large and complex circuits.

[0053] This method balances the imbalance between the unit circuit area and the total critical area of the transistors contained in some circuits, which can occur in some production process designs. This facilitates accurate classification research and more objectively achieves the testing goal of earlier fault detection using test vectors during testing. Furthermore, this method is entirely software-based and requires no additional hardware, reducing testing costs and ensuring feasibility.

[0054] The present invention not only considers the impact of the fault environment in the circuit's periphery on the unit circuit, but also focuses on the possibility of all faults occurring within the unit circuit, and also considers the possibility of various physical faults occurring inside the transistor, comprehensively considering the problem of circuit complexity.

[0055] The present invention sorts the test vectors according to the test quality from high to low, and preferentially loads the test vectors with better test quality in the test set, so that these test vectors can hit the fault earlier in the test process, thereby reducing the test time of the faulty integrated circuit, improving the test efficiency and reducing the test cost.

[0056] Different test vectors in the present invention may hit the same fault, and the number of faults hit by different test vectors may also vary. Therefore, we can change the order in which test vectors are loaded, allowing more test vectors with better test quality to be loaded first, thereby maintaining the fault coverage of the original test set. This present invention solves the technical problems of high testing cost, low testing efficiency, and low testing accuracy in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 A basic flow chart of a method for reordering effective key area parameter vector sets;

[0058] Figure 2 A schematic diagram of the refinement process of an effective key area parameter vector set reordering method. DETAILED DESCRIPTION

[0059] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0060] Example 1

[0061] For integrated circuit testing, the main process is as follows:

[0062] S1. Analyze and model the internal structure of the circuit under test, and use the Automatic Test Pattern Generation (ATPG) tool to generate test patterns for this circuit. During this process, try to ensure that the circuit achieves a high fault coverage rate.

[0063] S2. After obtaining the test vector, refer to the structural diagram of the integrated circuit being tested and calculate the total critical area containing transistors in different unit circuits relative to the area coverage of the unit circuit. During the test process, combine the statistics of the number of times each test vector hits the corresponding unit circuit fault, estimate the test characteristic value of each test vector, re-sort the original test set, input the sorted test vector set into the automated test equipment ATE, and test each circuit to be tested. If the test vector hits any fault, it means that there is a problem with this chip and it cannot be used. If the chip passes all test vectors, it means that this chip has passed the test without any fault, which means that this chip has no faults and can be put into use.

[0064] This patented method is not targeted at the test vector generation process, but rather at the processing of the test vector set generated in the above process, and the reordering of the test vectors. The main focus of this patent is to reorder the test vectors based on the test characteristic value of each test vector, taking into account the circuit complexity without changing the fault coverage accuracy, in order to reduce test time, improve test efficiency, and reduce test costs.

[0065] Based on the characteristics and operating procedures of automated test equipment (ATE), we know that after each test vector is input into the ATE, the faults it can detect in the integrated circuit remain fixed and unaffected by changes in the order of the test vectors. However, different test vectors may hit the same fault, and the number of faults they hit may vary. Therefore, we can change the order in which the test vectors are loaded, prioritizing the loading of more high-quality test vectors. This not only maintains the fault coverage of the original test set, but also significantly shortens fault detection time and improves test efficiency.

[0066] This patent proposes a test vector adjustment method that uses the ratio of the total critical area of transistors to the ratio of circuit units to measure the test quality of test vectors. The test characteristic value of each test vector is estimated from a global test perspective. This patent primarily focuses on providing a higher-quality test set for automatic test equipment (ATE) by only transforming the order of test vectors while maintaining the fault coverage of the original test set, thereby reducing test time and costs.

[0067] The main content of the present invention is: based on the circuit description language, by calculating the total critical area of transistors in the unit circuit corresponding to the fault hit by the test vector relative to the area coverage of the unit circuit, the test vector is effectively measured using data. Assuming that for a chip under a certain process, the quality of the test vector with a larger test characteristic value is better, the test vector with a larger test characteristic value is placed at the front, and the test vectors are reordered accordingly. Therefore, when testing again, the test vector with the largest test characteristic value is placed in the first position. The unit circuit through which the first test vector passes has the greatest circuit complexity, so its probability of detecting a fault is the highest. The second and third test vectors have decreasing probability in turn. In actual testing, ATE follows a "stop on first failure" testing method. That is, as long as any fault is detected in the circuit, it indicates that the chip is damaged and unusable, and the test stops. Therefore, this sorting method can detect faults earlier, effectively reducing testing time and thus reducing testing costs.

[0068] Example 2

[0069] S1', using a test pattern generation tool (Automatic Test Pattern Generation, ATPG) to generate a test pattern set for this circuit according to the circuit description language.

[0070] S2', inject faults into the circuit. Determine whether the circuit has faults based on the test response value of the test vector input into the simulation circuit.

[0071] S3', referring to the structural diagram of the integrated circuit being tested, calculate the total critical area of the transistors contained in different unit circuits relative to the area coverage of the unit circuit, and in the fault simulation test, count the number of times each test vector hits the fault, comprehensively estimate the test characteristic value of each test vector, and rank the test vector with the largest test characteristic value in the first position, and then complete the sorting by analogy, and then obtain a new sorted test vector set.

[0072] S4': After sorting the test vector set, the test vectors are input into the automatic test equipment (ATE). The first test vector has the highest probability of detecting a fault, while the second and third test vectors have decreasing probability. Therefore, for a random fault, the sorted test vector set can detect the fault more quickly, thereby reducing test time and costs.

[0073] In summary, the present invention sorts test vector sets and uses the test vectors to determine the coverage of the total critical area of transistors contained in each type of faulty unit circuit relative to the total area of the unit circuit. Without changing the accuracy of fault coverage, this method reduces the testing time for faulty chips, improves test efficiency, and reduces testing costs. Furthermore, this method demonstrates even better results in very large and complex circuits.

[0074] This method balances the imbalance between the unit circuit area and the total critical area of the transistors contained in some circuits, which can occur in some production process designs. This facilitates accurate classification research and more objectively achieves the testing goal of earlier fault detection using test vectors during testing. Furthermore, this method is entirely software-based and requires no additional hardware, reducing testing costs and ensuring feasibility.

[0075] The present invention not only considers the impact of the fault environment in the circuit's periphery on the unit circuit, but also focuses on the possibility of all faults occurring within the unit circuit, and also considers the possibility of various physical faults occurring inside the transistor, comprehensively considering the problem of circuit complexity.

[0076] The present invention sorts the test vectors according to the test quality from high to low, and preferentially loads the test vectors with better test quality in the test set, so that these test vectors can hit the fault earlier in the test process, thereby reducing the test time of the faulty integrated circuit, improving the test efficiency and reducing the test cost.

[0077] Different test vectors in the present invention may hit the same fault, and the number of faults hit by different test vectors may also vary. Therefore, we can change the order in which test vectors are loaded, allowing more test vectors with better test quality to be loaded first, thereby maintaining the fault coverage of the original test set. This present invention solves the technical problems of high testing cost, low testing efficiency, and low testing accuracy in the prior art.

[0078] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for reordering an effective key area parameter vector set, characterized in that: The method comprises: S1. Obtain a circuit description language of an integrated circuit under test, describe the integrated circuit under test using a hardware description language, and generate a test vector set for the integrated circuit under test using a test vector generation tool ATPG; S2. Perform fault injection on the analog circuit of the integrated circuit under test, obtain a test response value of the current integrated circuit under test, and compare the test response value with a test response value of a normal circuit to determine whether the integrated circuit under test has a fault; S3. Referring to the structural diagram of the integrated circuit under test, processing the total critical area coverage of transistors contained in different unit circuits relative to the area coverage of the unit circuits, counting the number of times each test vector in the test vector set hits a fault, processing the counted number of times to obtain a test characteristic value, sorting and processing the test vectors according to the test characteristic value, and re-sorting the test vector set for testing the integrated circuit under test; Including: S31, obtaining characteristic dimensions of various transistors in analog circuits; S32, obtaining the proportion data of each circuit unit of the analog circuit; S33, processing the structural diagram in the simulation circuit to obtain total critical area data of transistors of each unit circuit and unit circuit area data; S34, processing the total critical area data of the transistors and the unit circuit area data to obtain relative area coverage data of different unit circuits in the tested integrated circuit; S35, counting the number of hits of each test vector in the process of the simulated fault test performed on the analog circuit; S36 , estimating the test characteristic value of each of the test vectors according to the number of hits, and sorting the test vectors according to the magnitude of the test characteristic value to obtain the re-sorted test vector set.

2. The method for reordering an effective key area parameter vector set according to claim 1, characterized in that: The step S1 comprises: S11, analyzing and modeling the internal structure of the integrated circuit under test, describing the internal structure in the circuit description language, and generating a corresponding analog circuit accordingly; S12. Acquire test parameters of the analog circuit, and use the test vector generation tool ATPG to generate the test vector set.

3. The method for reordering an effective key area parameter vector set according to claim 2, characterized in that: The step S11 includes: S111, collecting internal structure data of the integrated circuit under test; S112: Analyze the internal structure data, model the integrated circuit under test, and construct the analog circuit accordingly.

4. The method for reordering an effective key area parameter vector set according to claim 2, characterized in that: The step S12 includes: S121, obtaining test type data and parameters of the analog circuit; S122, obtaining data parameters and requirements for each test type of the analog circuit; S123 , inputting the data and parameters of the test type, and the data parameters and requirements in each test type into the test vector generation tool ATPG to generate the test vector set.

5. The method for reordering an effective key area parameter vector set according to claim 1, characterized in that: The step S2 comprises: S21. Obtaining differential preset fault injection parameters; S22, inputting the different preset fault injection parameters into the simulation circuit to obtain different test response values; S23. Determine whether the tested integrated circuit has a fault according to the test response value.

6. The method for reordering an effective key area parameter vector set according to claim 1, characterized in that: In step S34, the test vectors are sorted in descending order.

7. The method for reordering an effective key area parameter vector set according to claim 1, characterized in that: Also includes: S1', inputting the test vector into automatic test equipment ATE; S2′, measuring the reordered test vector set in sequence with the automatic test equipment ATE to complete the test of the integrated circuit under test.

8. The method for reordering effective key area parameter vector sets according to claim 7, characterized in that: In step S2 ′, when the test vector hits a fault in the integrated circuit under test, it is determined to filter out the chip corresponding to the current integrated circuit under test.

9. An effective key area parameter vector set reordering system, characterized in that: The system comprises: A vector set generation module is used to obtain the circuit description language of the integrated circuit under test and use the test vector generation tool ATPG to generate a test vector set for the integrated circuit under test; a fault injection module, configured to inject a fault into the analog circuit of the integrated circuit under test, obtain and determine whether the integrated circuit under test has a fault based on a test response value currently in the analog circuit, the fault injection module being connected to the vector set generation module; a reordering module, configured to refer to the structural diagram of the integrated circuit under test, process the total critical area coverage of transistors contained in different unit circuits relative to the area coverage of the unit circuits, count the number of times each test vector in the test vector set hits a fault, obtain a test characteristic value based on the count, sort and process the test vectors according to the test characteristic value, and reorder the test vector set to test the integrated circuit under test, wherein the reordering module is connected to the fault injection module; It includes: a characteristic size acquisition unit: used to obtain the characteristic sizes of various transistors in the analog circuit; A circuit unit ratio obtaining unit is used to obtain the ratio data of each circuit unit of the analog circuit; A transistor critical area and unit area processing unit: used for processing the structural diagram in the analog circuit to obtain the total critical area data of the transistors and the unit circuit area data of each unit circuit; A relative area coverage calculation unit is configured to process the total critical area data of the transistor and the unit circuit area data to obtain relative area coverage data of different unit circuits in the tested integrated circuit; A test vector hit count counting unit is used to count the hit count of each test vector in the process of simulated fault testing on the analog circuit; A test vector reordering unit is configured to estimate the test characteristic value of each of the test vectors according to the number of hits, and sort the test vectors according to the magnitude of the test characteristic value to obtain the reordered test vector set.

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