DFT test mode control circuit, method and chip
Through the dual verification mechanism of the timing and signal verification modules, the existing port resources are used to control the chip to enter the DFT test mode, which solves the problem of insufficient port quantity and realizes high reliability and low-cost DFT testing.
Patent Information
- Application Number
- CN202510515191.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-23
- Publication Date
- 2025-09-30
- Estimated Expiration
- 2045-04-23
AI Technical Summary
In chip design, the insufficient number of ports makes it impossible to effectively apply DFT testing, resulting in failure to meet DFT design requirements.
The timing verification module counts the rising edges of the test clock signal, and the signal verification module samples the test data signal. Only when the rising edge count value and the actual sampling value meet the preset standards at the same time, the test control module outputs a logic level signal to control the circuit under test to enter the DFT test mode.
Effectively utilize existing port resources to form a multiple verification mechanism, improve the reliability of entering the DFT test mode, reduce the number of ports, reduce chip design costs, and enhance the applicability and versatility of the chip.
Smart Images
Figure CN120044380B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to a DFT test mode control circuit, method and chip. Background Art
[0002] In the field of integrated circuit design, DFT (Design for Testability) technology effectively improves chip testability by inserting specific logic structures, such as scan chains and boundary scans. This allows for early detection of potential chip issues, improving product quality and reducing production costs. Given that the core of DFT technology lies in inserting test logic structures into a chip, six key ports are typically required to ensure their functionality: a test mode selection port, a test clock port, a test data input port, a test data output port, a test reset port, and a test enable port. These ports are used to implement different functions, from switching operating modes to transmitting test instructions or data, and are crucial to ensuring the effective operation of DFT circuits.
[0003] However, given the limited number of ports in some chip designs, it's impossible to allocate independent physical connections to all the ports required for DFT, resulting in designs that don't meet DFT requirements. For example, some chips only have four ports, which inevitably results in the lack of some functional ports required for DFT testing, making it impossible to effectively apply DFT technology for testing. Summary of the Invention
[0004] In view of the above-mentioned deficiencies in the prior art, the present invention provides a DFT test mode control circuit, method and chip, which solve the technical problem in the prior art that DFT testing cannot be performed when the number of chip ports is insufficient.
[0005] A first aspect of the present invention provides a DFT test mode control circuit, comprising a timing verification module, a signal verification module, and a test control module, wherein the output end of the timing verification module and the output end of the signal verification module are respectively connected to the input end of the test control module, and the output end of the test control module is connected to the circuit to be tested;
[0006] The input end of the timing verification module is connected to the test clock signal, which is used to count the rising edges of the test clock signal, record the rising edge count value, compare the rising edge count value with the pre-designed value, obtain the timing comparison result and output it to the test control module;
[0007] The input end of the signal verification module is connected to the test data signal, and is used to sample the test data signal at the rising edge of the test clock signal within a preset period, record the actual sampling value, compare the actual sampling value with the preset sampling value, obtain a signal comparison result and output it to the test control module, wherein the value of the preset period is equal to the pre-designed value;
[0008] The test control module is configured to output a preset logic level signal to control the circuit under test to enter a DFT test mode when the timing comparison result indicates that the rising edge count value is equal to a pre-designed value and the signal comparison result indicates that the actual sampling value is equal to the preset sampling value.
[0009] Optionally, the timing verification module includes a rising edge counter and a first comparator, wherein the output end of the rising edge counter is connected to the input end of the first comparator, and the output end of the first comparator is connected to the input end of the test control module; the input end of the rising edge counter is connected to the test clock signal, for incrementing the rising edge of the test clock signal, recording the rising edge count value and outputting it to the first comparator, wherein when the rising edge count value reaches a pre-designed value, the rising edge count value stops increasing and remains at the pre-designed value; the first comparator compares the rising edge count value with the pre-designed value, obtains a timing comparison result and outputs it to the test control module.
[0010] Optionally, the signal verification module includes a register unit and a comparator unit, wherein the output end of the register unit is connected to the input end of the comparator unit, and the output end of the comparator unit is connected to the input end of the test control module; the register unit is connected to the test data signal, and is used to sample the test data signal on the rising edge of the test clock signal within a preset period, record the actual sampling value and output it to the comparator unit; the comparator unit compares the actual sampling value with the preset sampling value, obtains a signal comparison result and outputs it to the test control module.
[0011] Optionally, the test data signal includes a test data input signal and a test enable signal, the register unit includes a first register and a second register, and the comparator unit includes a second comparator and a third comparator, wherein the output end of the first register is connected to the input end of the second comparator, the output end of the second register is connected to the input end of the third comparator, and the output end of the second comparator and the output end of the third comparator are respectively connected to the input end of the test control module; the input end of the first register is connected to the test data input signal, and is used to sample the test data input signal at the rising edge of the test clock signal within a preset period, record the first sampling value and output it to the second comparator, and the second comparator compares the first sampling value with the first preset sampling value. , obtain a first signal comparison result and output it to the test control module; the input end of the second register is connected to the test enable signal, for sampling the test enable signal at the rising edge of the test clock signal within a preset period, recording a second sampling value and outputting it to the third comparator, the third comparator compares the second sampling value with a second preset sampling value, obtains a second signal comparison result and outputs it to the test control module; when the timing comparison result indicates that the rising edge count value is equal to a pre-designed value, the first signal comparison result indicates that the first sampling value is equal to the first preset sampling value, and the second signal comparison result indicates that the second sampling value is equal to the second preset sampling value, the test control module outputs a high-level signal to control the circuit under test to enter the DFT test mode.
[0012] Optionally, the DFT test mode control circuit also includes a system reset module, which is respectively connected to the timing verification module, the signal verification module, the test control module and the circuit to be tested; the system reset module is used to generate a global reset signal in response to a system reset instruction to perform a reset operation on the timing verification module, the signal verification module and the test control module, and initialize the circuit to be tested.
[0013] Optionally, the DFT test mode control circuit also includes a test reset port; the test reset port is any output port in the circuit to be tested, and the test reset port is connected to the test device and is used to receive a test reset signal sent by the test device, wherein the signal output by the test reset port maintains an invalid level state.
[0014] Optionally, the signal output by the test reset port is set to an invalid level state through a preset connection operation based on a DFT test script.
[0015] A second aspect of the present invention provides a DFT test mode control method, which is applied to any of the above-mentioned DFT test mode control circuits, and includes:
[0016] Using the timing verification module to access the test clock signal, counting the rising edges of the test clock signal incrementally, recording the rising edge count value, comparing the rising edge count value with a pre-designed value, obtaining a timing comparison result and outputting it to the test control module;
[0017] Accessing a test data signal using the signal verification module, sampling the test data signal at the rising edge of the test clock signal within a preset period, recording an actual sampled value, comparing the actual sampled value with a preset sampled value, obtaining a signal comparison result, and outputting the result to the test control module, wherein the value of the preset period is equal to the pre-designed value;
[0018] When the timing comparison result indicates that the rising edge count value is equal to the pre-designed value, and the signal comparison result indicates that the actual sampling value is equal to the preset sampling value, the test control module outputs a preset logic level signal to control the circuit under test to enter the DFT test mode.
[0019] Optionally, the DFT test mode control circuit also includes a system reset module, which is respectively connected to the timing verification module, the signal verification module, the test control module and the circuit to be tested; before using the timing verification module to access the test clock signal, the method also includes: in response to a system reset instruction, the system reset module generates a global reset signal to perform a reset operation on the timing verification module, the signal verification module and the test control module, and initialize the circuit to be tested.
[0020] A third aspect of the present invention provides a chip, comprising any one of the above-mentioned DFT test port simulation circuits and at least one circuit to be tested.
[0021] The DFT test mode control circuit, method, and chip provided by the present invention respectively utilize a timing verification module to count the rising edges of a test clock signal, and utilize a signal verification module to sample a test data signal. Only when the rising edge count value and the actual sampled value simultaneously meet preset standard values for entering the test, can the test control module output a preset logic level signal, thereby controlling the circuit under test to enter the DFT test mode. The above circuit effectively utilizes the signal resources output by existing ports to form a multiple verification mechanism triggered by the test mode selection port, thereby improving the reliability of the circuit under test entering the DFT test mode. There is no need to set up a dedicated port for test mode selection, which significantly reduces the number of ports and reduces chip design costs. This makes the chip more applicable and versatile, and can meet the basic requirements of DFT testing without having all test ports.
[0022] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.
[0023] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:
[0025] Figure 1 This is a schematic diagram of the overall structure of a DFT test mode control circuit in an embodiment provided by the present application;
[0026] Figure 2 This is a schematic diagram of the overall structure of a DFT test mode control circuit in another embodiment provided by the present application;
[0027] Figure 3 A specific circuit diagram of a DFT test mode control circuit in another embodiment provided by this application;
[0028] Figure 4 A signal waveform diagram of a DFT test mode control circuit in another embodiment provided by the present application;
[0029] Figure 5 A schematic flow chart of a DFT test mode control method according to an embodiment of the present application;
[0030] Figure 6This is a flowchart of a DFT test mode control method in another embodiment provided by the present application.
[0031] In the picture:
[0032] PIN1, test clock port; PIN2, test data input port; PIN3, test enable port;
[0033] init_reg[7:0], the first sampling value; init_reg1[7:0], the second sampling value; test_mode_cnt[3:0], the rising edge count value; test_mode, the signal output by the test control module. DETAILED DESCRIPTION
[0034] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of the present application can be combined with each other.
[0035] In one embodiment, Figure 1 As shown, a DFT test mode control circuit is provided, including a timing verification module, a signal verification module and a test control module, wherein the output end of the timing verification module and the output end of the signal verification module are respectively connected to the input end of the test control module, and the output end of the test control module is connected to the circuit under test; the input end of the timing verification module is connected to a test clock signal, and is used to count the rising edges of the test clock signal, record the rising edge count value, compare the rising edge count value with a pre-designed value, obtain a timing comparison result, and output it to the test control module; the input end of the signal verification module is connected to a test data signal, and is used to sample the test data signal at the rising edge of the test clock signal within a preset period, record the actual sampled value, compare the actual sampled value with the preset sampled value, obtain a signal comparison result, and output it to the test control module, wherein the value of the preset period is equal to the pre-designed value; the test control module is used to output a preset logic level signal when the timing comparison result indicates that the rising edge count value is equal to the pre-designed value and the signal comparison result indicates that the actual sampled value is equal to the preset sampled value, so as to control the circuit under test to enter the DFT test mode.
[0036] The DFT test mode control circuit provided in this embodiment utilizes a timing verification module to count rising edges of a test clock signal and a signal verification module to sample a test data signal. Only when both the rising edge count value and the actual sampled value meet preset test entry criteria does the test control module output a preset logic level signal, thereby controlling the circuit under test to enter DFT test mode. This circuit effectively utilizes signal resources output by existing ports to form a multi-verification mechanism triggered by the test mode selection port, improving the reliability of the circuit under test entering DFT test mode. This eliminates the need for dedicated ports for test mode selection, significantly reducing the number of ports and chip design costs, making the chip more adaptable and versatile. It can meet the basic requirements of DFT testing without requiring all test ports.
[0037] The preset logic level signal is a high level signal.
[0038] In one embodiment, Figure 2 As shown, the timing verification module includes a rising edge counter and a first comparator, wherein the output end of the rising edge counter is connected to the input end of the first comparator, and the output end of the first comparator is connected to the input end of the test control module; the input end of the rising edge counter is connected to the test clock signal, which is used to count the rising edge of the test clock signal, record the rising edge count value and output it to the first comparator, wherein when the rising edge count value reaches a pre-designed value, the rising edge count value stops increasing and maintains at the pre-designed value; the first comparator compares the rising edge count value with the pre-designed value, obtains the timing comparison result and outputs it to the test control module.
[0039] In this embodiment, the rising edge counter can accurately record the number of rising edges of the test clock signal to ensure the accuracy of timing verification. The pre-designed value can also be adjusted according to specific test requirements, so that the timing verification module has high flexibility and versatility and can be applied to different test scenarios. The timing verification module and the signal verification module together constitute a multiple verification mechanism for test mode selection port triggering. The test mode will only be triggered when all conditions are met, thereby improving the reliability of entering the DFT test mode.
[0040] In one embodiment, Figure 2As shown, the signal verification module includes a register unit and a comparator unit, wherein the output end of the register unit is connected to the input end of the comparator unit, and the output end of the comparator unit is connected to the input end of the test control module; the register unit is connected to the test data signal, and is used to sample the test data signal at the rising edge of the test clock signal within a preset period, record the actual sampling value and output it to the comparator unit; the comparator unit compares the actual sampling value with the preset sampling value, obtains the signal comparison result and outputs it to the test control module.
[0041] In this embodiment, at least one register is provided in the register unit, and at least one comparator is provided in the comparator unit. The registers and the comparators are connected in a one-to-one correspondence. The register is used to access a signal output by a port and sample it to obtain a sampled value, and the correspondingly connected comparator is used to compare the sampled value with a preset sampled value to obtain a comparison result. Ultimately, all the obtained comparison results are output to the test control module. In conjunction with the timing verification module, on the basis of the rising edge count value reaching a pre-designed value, only when all comparison results show that all sampled values meet the preset sampled value, can the signal test_mode output by the test control module be controlled to a high level, thereby controlling the circuit under test to enter the DFT test mode. Redundant sampling is performed by the register unit, thereby enhancing the fault tolerance capability of the signal verification module. Multiple registers in the register unit work in parallel to process different types of test data signals, respectively, thereby improving the parallel processing capability of the signal verification module. The modular structure design and flexible configuration of the signal verification module can be expanded or tailored according to actual needs, thereby enhancing the versatility and adaptability of the signal verification module.
[0042] Specifically, such as Figure 2 and Figure 3As shown, the test data signal includes a test data input signal and a test enable signal, the register unit includes a first register and a second register, and the comparator unit includes a second comparator and a third comparator, wherein the output end of the first register is connected to the input end of the second comparator, the output end of the second register is connected to the input end of the third comparator, and the output end of the second comparator and the output end of the third comparator are respectively connected to the input end of the test control module; the input end of the first register is connected to the test data input signal, and is used to sample the test data input signal at the rising edge of the test clock signal within a preset period, record the first sampled value and output it to the second comparator, and the second comparator compares the first sampled value with the first preset sampled value, A first signal comparison result is obtained and output to a test control module; a test enable signal is connected to an input end of a second register for sampling the test enable signal at a rising edge of a test clock signal within a preset period, recording a second sampling value and outputting it to a third comparator; the third comparator compares the second sampling value with a second preset sampling value, obtains a second signal comparison result and outputs it to the test control module; when the timing comparison result indicates that the rising edge count value is equal to a pre-designed value, the first signal comparison result indicates that the first sampling value is equal to the first preset sampling value, and the second signal comparison result indicates that the second sampling value is equal to the second preset sampling value, the test control module outputs a high-level signal to control the circuit under test to enter a DFT test mode.
[0043] In this embodiment, taking the RTC circuit of the IIC interface as an example, there are only four available ports, including: PIN1 as the test clock port, PIN2 as the test data input port, PIN3 as the test enable port, and PIN4 as the test data output port; based on this, this circuit lacks a test reset port and a test mode selection port. Here we specifically analyze how this application implements the test mode selection port based on the existing port simulation, and the test reset port will be analyzed in subsequent content.
[0044] The implementation principle of the test mode selection port is based on the specific input timing of the output signals of the three ports PIN1, PIN2, and PIN3. The waveform of the signal is as follows: Figure 4As shown, the initial value of the test data input signal output by the test data input port PIN2 is 0, and is sampled in sequence at the rising edge of the test clock signal output by the test clock port PIN1 to obtain a first sampling value 8'b00000111, which changes to 0 at the 9th rising edge of the test clock signal and then remains at 0; the initial value of the test enable signal output by the test enable port PIN3 is 0, and is sampled in sequence at the rising edge of the test clock port PIN1 to obtain a second sampling value 8'b00101001, and then remains at 1; at the same time, the rising edge count value test_mode_cnt[3:0] recorded by the rising edge counter in the circuit is initially 0, and is increased by 1 at the rising edge of each test clock signal output by the test clock port PIN1, and remains unchanged after being added to the pre-designed value, which is specifically 8; the first register in the circuit is used to record the test enable signal. The test data input port PIN2 outputs the first sampling value init_reg[7:0] of the 8 cycles of the test data input signal. The second register in the circuit is used to record the second sampling value init_reg1[7:0] of the 8 cycles of the test enable signal output by the test enable port PIN3. The first preset sampling value 8'h07 is pre-stored in the second comparator, and the second preset sampling value 8'h29 is pre-stored in the third comparator. When the preset count value is 8, if the first sampling value init_reg[7:0] is 8'h07, the second sampling value init_reg1[7:0] is 8'h29, and the rising edge count value test_mode_cnt[3:0] is 8, the test control module outputs a high-level signal test_mode, thereby controlling the circuit under test to enter the test mode.
[0045] It should be noted that, since the test control module outputs the high-level signal test_mode, the three ports PIN1, PIN2, and PIN3 are all in the normal mode working state and are not used as test mode signals. Therefore, the three ports PIN1, PIN2, and PIN3 can be used to output specific stimuli to control the circuit under test to enter the DFT test mode, saving a conventionally used test mode selection port. At the same time, the rising edge counter counts the rising edges of the test clock signal, ensuring that the high-level signal test_mode is generated only in the first 8 cycles after power-on; when the circuit in the chip operates in the normal mode, even if the output signals of the PIN2 port and the PIN3 port are abnormal, it can effectively prevent the test control module from outputting the high-level signal test_mode, avoiding the circuit under test from being controlled to enter the DFT test mode when operating in the normal mode, thereby disrupting the normal operation of the circuit.
[0046] In one embodiment, the DFT test mode control circuit further includes a system reset module, which is respectively connected to the timing verification module, the signal verification module, the test control module, and the circuit under test; the system reset module is used to generate a global reset signal in response to a system reset instruction to perform a reset operation on the timing verification module, the signal verification module, and the test control module, and initialize the circuit under test.
[0047] Specifically, the DFT test mode control circuit also includes a test reset port; the test reset port is any output port in the circuit to be tested, the test reset port is connected to the test equipment, and is used to receive a test reset signal sent by the test equipment, wherein the signal output by the test reset port maintains an invalid level state.
[0048] Furthermore, the signal output by the test reset port is set to an invalid level state through a preset connection operation based on the DFT test script.
[0049] Among them, the invalid level state refers to a state in which a signal is in a state that will not trigger any specific function or operation. In digital circuit design, signals usually have two basic level states, namely the high level state of logic 1 and the low level state of logic 0. According to specific design requirements, one of the levels may be defined as a valid level state, and the other as an invalid level state. When the signal is in a valid level state, it will trigger a specific operation or function; when the signal is in an invalid level state, it will not trigger any specific operation or function; taking the test reset signal as an example, if the high level is the valid level state, then the low level is the invalid level state, which means that the signal will not trigger the reset operation.
[0050] In this embodiment, the basic function of the test reset port is to perform a reset operation when the circuit under test enters test mode. Considering that the logic for generating the high-level signal test_mode output by the test control module can be reset by the system reset module, the test reset port cannot be shared with the system reset module. Otherwise, after entering test mode, executing the function of the test reset port will directly exit test mode. Based on this, the present application directly sets an output port of the circuit under test as the test reset port through a hookup in the DFT script, and sets the signal output by this port to an invalid level state within the circuit, thereby preventing the test reset port from triggering any reset operation. Since all registers are reset when the chip is powered on by the system reset module, the test mode is entered by sending a sequence without powering off. That is, the test control module outputs a high-level signal test_mode, all registers are reset, and the internal state of the circuit under test is initialized. Therefore, there is no need to use the test reset port for reset. Therefore, while saving one test mode selection port, one test reset port is also saved. Only four ports are required to implement the full functionality of DFT testing.
[0051] In one embodiment, Figure 5 As shown, a DFT test mode control method is provided, which can be applied to the DFT test mode control circuit of any of the above embodiments. The execution subject of the method can be a signal detection device or a computer device, etc. The method includes the following steps:
[0052] Step 101: Use the timing verification module to access the test clock signal, count the rising edges of the test clock signal, record the rising edge count value, compare the rising edge count value with the pre-designed value, obtain the timing comparison result and output it to the test control module.
[0053] Step 102: Using a signal verification module to access a test data signal, sampling the test data signal at the rising edge of a test clock signal within a preset period, recording the actual sampled value, comparing the actual sampled value with the preset sampled value, obtaining a signal comparison result, and outputting it to a test control module, wherein the value of the preset period is equal to the pre-designed value;
[0054] Step 103 , when the timing comparison result indicates that the rising edge count value is equal to the pre-designed value, and the signal comparison result indicates that the actual sampling value is equal to the preset sampling value, the test control module outputs a preset logic level signal to control the circuit under test to enter the DFT test mode.
[0055] The DFT test mode control method provided in this embodiment uses a timing verification module and a signal verification module to accurately count and sample the test clock signal and test data signal, respectively, and perform strict comparison operations. Only when the timing comparison results and the signal comparison results meet the requirements will the circuit under test be triggered to enter the DFT test mode. This dual verification mechanism greatly improves the reliability of entering the test mode and reduces the possibility of misjudgment. The timing verification module and the signal verification module each output the comparison results to the test control module. This centralized processing method improves system integration, and the various functional modules are independent and work together, enhancing the flexibility and maintainability of the circuit.
[0056] Further, such as Figure 6 As shown, the DFT test mode control method further includes before step 101:
[0057] Step 104 : In response to the system reset instruction, the system reset module generates a global reset signal to reset the timing verification module, the signal verification module, and the test control module, and initialize the circuit under test.
[0058] In this embodiment, a global reset signal is generated by the system reset module to ensure that all related modules and the circuit under test are in the initial state, providing a stable environment for subsequent tests and reducing the impact of external interference on the test results. There is no need to design reset logic for each module separately. The overall system reset is the reset before the circuit under test enters the DFT test mode. After the overall system reset, the timing verification module, the signal verification module, and the test control module directly enter the working state. In the shortest time period, the test control module can output the high-level signal test_mode to control the circuit under test to enter the DFT test mode, further reducing the setting of the test reset port and compressing the number of ports.
[0059] In one embodiment, a chip is provided, comprising the DFT test mode control circuit according to any of the above embodiments and at least one circuit to be tested.
[0060] In this embodiment, the chip can put the circuit under test into a test state by utilizing the signal resources output by the existing ports, thereby effectively reducing the number of ports required to be provided on the chip, reducing the chip size, and lowering the chip cost.
[0061] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0062] The above embodiments merely illustrate several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art may make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.
Claims
1. A DFT test mode control circuit, characterized in that: It includes a timing verification module, a signal verification module and a test control module, wherein the output end of the timing verification module and the output end of the signal verification module are respectively connected to the input end of the test control module, and the output end of the test control module is connected to the circuit to be tested; The input end of the timing verification module is connected to the test clock signal, which is used to count the rising edges of the test clock signal, record the rising edge count value, compare the rising edge count value with the pre-designed value, obtain the timing comparison result and output it to the test control module; The input end of the signal verification module is connected to the test data signal, which is used to sample the test data signal at the rising edge of the test clock signal within a preset period, record the actual sampling value, compare the actual sampling value with the preset sampling value, obtain the signal comparison result and output it to the test control module, wherein the value of the preset period is equal to the pre-designed value, and the test data signal includes a test data input signal and a test enable signal; The test control module is configured to output a preset logic level signal to control the circuit under test to enter a DFT test mode when the timing comparison result indicates that the rising edge count value is equal to a pre-designed value and the signal comparison result indicates that the actual sampling value is equal to the preset sampling value; The DFT test mode control circuit further includes a test reset port; The test reset port is any output port in the circuit to be tested, and is connected to a test device for receiving a test reset signal sent by the test device. The signal output by the test reset port maintains an invalid level state.
2. The DFT test mode control circuit according to claim 1, wherein: The timing verification module includes a rising edge counter and a first comparator, wherein the output end of the rising edge counter is connected to the input end of the first comparator, and the output end of the first comparator is connected to the input end of the test control module; The input end of the rising edge counter is connected to the test clock signal, and is used to count the rising edges of the test clock signal, record the rising edge count value and output it to the first comparator, wherein when the rising edge count value reaches a pre-designed value, the rising edge count value stops increasing and is maintained at the pre-designed value; The first comparator compares the rising edge count value with a pre-designed value to obtain a timing comparison result and outputs the result to the test control module.
3. The DFT test mode control circuit according to claim 1, wherein: The signal verification module includes a register unit and a comparator unit, wherein the output end of the register unit is connected to the input end of the comparator unit, and the output end of the comparator unit is connected to the input end of the test control module; The register unit receives the test data signal and is used to sample the test data signal at the rising edge of the test clock signal within a preset period, record the actual sampled value and output it to the comparator unit; The comparator unit compares the actual sampling value with the preset sampling value, obtains a signal comparison result and outputs it to the test control module.
4. The DFT test mode control circuit according to claim 3, wherein: The register unit includes a first register and a second register, and the comparator unit includes a second comparator and a third comparator, wherein the output end of the first register is connected to the input end of the second comparator, the output end of the second register is connected to the input end of the third comparator, and the output end of the second comparator and the output end of the third comparator are respectively connected to the input end of the test control module; The input end of the first register is connected to the test data input signal, and is used to sample the test data input signal at the rising edge of the test clock signal within a preset period, record a first sampling value and output it to the second comparator, and the second comparator compares the first sampling value with a first preset sampling value to obtain a first signal comparison result and output it to the test control module; The input end of the second register is connected to the test enable signal, and is used to sample the test enable signal at the rising edge of the test clock signal within a preset period, record a second sampled value and output it to the third comparator, and the third comparator compares the second sampled value with a second preset sampled value to obtain a second signal comparison result and output it to the test control module; When the timing comparison result indicates that the rising edge count value is equal to a pre-designed value, the first signal comparison result indicates that the first sampling value is equal to a first preset sampling value, and the second signal comparison result indicates that the second sampling value is equal to a second preset sampling value, the test control module outputs a preset logic level signal to control the circuit under test to enter a DFT test mode.
5. The DFT test mode control circuit according to claim 1, wherein: The DFT test mode control circuit further includes a system reset module, which is connected to the timing verification module, the signal verification module, the test control module and the circuit to be tested respectively; The system reset module is used to generate a global reset signal in response to a system reset instruction to perform a reset operation on the timing verification module, the signal verification module and the test control module, and initialize the circuit to be tested.
6. The DFT test mode control circuit according to claim 1, wherein: The signal output by the test reset port is set to an invalid level state through a preset connection operation based on a DFT test script.
7. A DFT test mode control method, characterized in that: The method is applied to the DFT test mode control circuit according to any one of claims 1 to 6, and the method includes: Using the timing verification module to access the test clock signal, counting the rising edges of the test clock signal incrementally, recording the rising edge count value, comparing the rising edge count value with a pre-designed value, obtaining a timing comparison result and outputting it to the test control module; Accessing a test data signal using the signal verification module, sampling the test data signal at the rising edge of the test clock signal within a preset period, recording an actual sampled value, comparing the actual sampled value with a preset sampled value, obtaining a signal comparison result, and outputting the result to the test control module, wherein the value of the preset period is equal to the pre-designed value; When the timing comparison result indicates that the rising edge count value is equal to the pre-designed value, and the signal comparison result indicates that the actual sampling value is equal to the preset sampling value, the test control module outputs a preset logic level signal to control the circuit under test to enter the DFT test mode.
8. The DFT test mode control method according to claim 7, wherein: The DFT test mode control circuit further includes a system reset module, which is respectively connected to the timing verification module, the signal verification module, the test control module, and the circuit under test; before using the timing verification module to access the test clock signal, the method further includes: In response to a system reset instruction, the system reset module generates a global reset signal to reset the timing verification module, the signal verification module, and the test control module, and initialize the circuit under test.
9. A chip, characterized in that: The method comprises the DFT test mode control circuit according to any one of claims 1 to 6 and at least one circuit to be tested.