Techniques for performing write training on dynamic random access memory

Abstract

The present invention relates to techniques for performing write training on dynamic random access memory. Various embodiments include a memory device capable of performing a write training operation to determine that certain timing conditions are met without storing a data pattern in the memory. Existing methods for write training involve storing a long data pattern in the memory and then reading the long data pattern to determine whether the data is correctly written to the memory. In contrast, the memory device of the present disclosure generates a data pattern within the memory device that matches a data pattern sent to the memory device by an external memory controller. If the data pattern generated by the memory device matches the data pattern received from the memory controller, the memory device stores a pass status in a register. If the data patterns do not match, the memory device stores a pass status in a register. The memory controller reads the register to determine whether the write training passed or failed.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 144,971, entitled “TECHNIQUESFOR TRANSFERRING COMMANDS TO A DRAM,” filed on February 2, 2021. This application further claims priority to U.S. Provisional Patent Application No. 63 / 152,814, entitled “DATA SCRAMBLING ON A MEMORY INTERFACE,” filed on February 23, 2021. This application further claims priority to U.S. Provisional Patent Application No. 63 / 152,817, entitled “DRAM COMMAND INTERFACE TRAINING,” filed on February 23, 2021. This application further claims priority to U.S. Provisional Patent Application No. 63 / 179,954, entitled “DRAM WRITE TRAINING,” filed on April 26, 2021. The subject matter of these related applications is incorporated herein by reference. Background Art

[0003] Fields of various embodiments

[0004] Various embodiments relate generally to computer memory devices and, more particularly, to techniques for performing write training on dynamic random access memory.

[0005] Description of Related Technology

[0006] Among other things, a computer system typically includes one or more processing units, such as a central processing unit (CPU) and / or a graphics processing unit (GPU), and one or more memory systems. One memory system is called system memory, which is accessible by the CPU and GPU. Another memory system is graphics memory, which is typically only accessible by the GPU. These memory systems include multiple memory devices. An example memory device used in system memory and / or graphics memory is synchronous dynamic random access memory (SDRAM, or more briefly, DRAM).

[0007] Typically, high-speed DRAM memory devices employ multiple interfaces. These interfaces include a command address interface for transmitting commands to DRAM. Such commands include commands to initiate write operations, commands to initiate read operations, and the like. These interfaces also include a data interface for transmitting data to and from DRAM. Command write operations transmit commands to DRAM synchronously. During command write operations, DRAM samples incoming commands on certain command input pins relative to the rising or falling edge of a clock signal. Similarly, data write operations transmit data to DRAM synchronously. During data write transmission, DRAM samples incoming data on certain data input pins relative to the rising or falling edge of a clock signal. Further, data read operations transmit data synchronously from DRAM. During read and write transmissions, DRAM presents outgoing data on certain data output pins relative to the rising or falling edge of a clock signal. The clock signals for commands transmitted to DRAM, data transmitted to DRAM, and data transmitted from DRAM may use the same or different clock signals. Further, the data input pins may be the same or different from the data output pins.

[0008] In order to reliably transmit commands and data to and from the DRAM, certain timing requirements must be met. One timing requirement is the setup time, which defines the minimum amount of time that a command or data signal must be stable before the clock edge that transmits the respective command or data signal. Another timing requirement is the hold time, which defines the minimum amount of time that a command or data signal must be stable after the clock edge that transmits the respective command or data signal. If the setup time and / or the hold time are not met, commands and / or data may be transmitted with one or more errors, resulting in corrupted command or data information.

[0009] As the speed of DRAM memory devices increases, the time between consecutive clock edges decreases, resulting in a shorter time period to meet the setup time and hold time. Further, the timing of clock signals, command signals, and data signals is affected by changes caused by process changes during manufacturing and local changes caused by operating temperature, power supply voltage, interference from other signals, etc. As a result, the setup time and hold time are more difficult to meet as the speed of DRAM devices increases. To alleviate this problem, DRAM memory devices generally have a skew circuit to change the timing of command signals and / or data signals relative to the clock signal. Periodically, a memory controller associated with the DRAM causes the DRAM to enter a training process for command write operations, data write operations, and / or data read operations. During such a training process, the memory controller changes the skew of one or more command input pins, data input pins, and / or data output pins until the memory controller determines that the DRAM each reliably performs a command write operation, a data write operation, and / or a data read operation. The memory controller periodically repeats these training operations when operating conditions change over time, such as changes in operating temperature, power supply voltage, etc., to ensure reliable DRAM operation.

[0010] In particular, with respect to write training, a memory controller writes a write training data pattern, or more briefly, a write data pattern, to a portion of a DRAM memory core. Typically, the data pattern is a pseudo-random bit sequence suitable for detecting errors on a particular data input of a DRAM memory device. The memory controller then reads the data pattern from the same portion of the DRAM memory core. If the data pattern read by the memory controller from that portion of the DRAM memory core matches the data pattern that the memory controller previously wrote to that portion of the DRAM memory core, the training operation is successful. However, if the two data patterns do not match, the memory controller adjusts the skew of the data input pin that displays one or more errors. The memory controller iteratively repeats the write training operation and adjusts the skew of the data input pin until the data patterns match. The memory controller then returns the DRAM to normal operation.

[0011] One disadvantage of this technique for DRAM write training is that as the speed of DRAM devices increases, the length of the data patterns required to adequately and reliably perform training operations will also increase, both for write training operations and for read training operations. Long data patterns generally require more time to write to and read from the DRAM, thereby increasing the amount of time to write the data pattern and read the data pattern during write training. Likewise, long data patterns generally require more storage capacity of the DRAM, while reducing the amount of memory space available to store data other than write training.

[0012] In some implementations, a separate memory, such as a first-in-first-out (FIFO) memory, is used to store data patterns for write training, rather than being part of the DRAM memory core portion. The FIFO memory stores the write training pattern, rather than the DRAM memory core. The memory controller then reads back the write training pattern from the separate FIFO memory, rather than from the DRAM memory core. However, as the size of the data pattern increases, the size of the FIFO memory also increases, thereby consuming a large portion of the DRAM die area and increasing the cost of the DRAM. Although the size of the FIFO memory can be reduced, this will result in only a portion of the write training data pattern being stored in the FIFO memory, thereby reducing the effectiveness of the write training operation.

[0013] Furthermore, whether using part of the DRAM memory core or a separate memory, such as a FIFO memory, the memory controller writes long write training data patterns to the DRAM and reads the same long write training data patterns from the DRAM multiple times during each write training operation, thereby reducing the available bandwidth of the DRAM for performing load and store operations other than write training.

[0014] As noted above, what is needed in the art are more efficient techniques for performing signal training of memory devices. Summary of the invention

[0015] Various embodiments of the present disclosure set forth a computer-implemented method for performing a write training operation on a memory device. The method includes initializing a first register on the memory device with a first data pattern. The method also includes receiving a second data pattern on an input pin of the memory device. The method also includes comparing the first data pattern and the second data pattern to generate a result value. The method also includes storing the result value in a second register. The method also includes the result value indicating whether the write training operation was successful.

[0016] Other embodiments include, but are not limited to, systems implementing one or more aspects of the disclosed technology, one or more computer-readable media including commands for executing one or more aspects of the disclosed technology, and methods of executing one or more aspects of the disclosed technology.

[0017] At least one technical advantage of the disclosed technology relative to the prior art is that, with the disclosed technology, the lengthy write training data pattern sent to the memory device during the write training operation does not need to be stored in the memory device or read from the memory device to determine whether the write training operation is successful. Instead, the memory controller only needs to send the write training data pattern and read the pass / fail result to determine whether the write training operation is successful. Therefore, relative to the prior art that requires reading the write training data pattern from the memory device, the write training operation is completed in about half the time.

[0018] Another advantage of the disclosed technology is that all pins of the data interface are trained simultaneously, thus requiring shorter training time relative to conventional methods. In contrast, according to the conventional method of writing a data pattern to a DRAM memory core and then reading the data pattern back, only the data input / output pins themselves are trained. After the training of the data pins is completed, additional pins of the data interface that are not stored in the DRAM memory core are trained in a separate training operation. By using a pseudo-random bit sequence (PRBS) pattern checker operating at the input / output pin level, all pins of the data interface are trained in parallel, further reducing the training time. These advantages present one or more technical advances relative to the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to understand in detail the manner in which the above-mentioned features of the various embodiments are employed, a more specific description of the inventive concept briefly outlined above may be obtained with reference to the various embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings only show typical embodiments of the inventive concept and therefore should not be considered to limit the scope in any way, and there are other equally effective embodiments.

[0020] Figure 1 is a block diagram of a computer system configured to implement one or more aspects of various embodiments;

[0021] Figure 2 According to various embodiments Figure 1 A block diagram of a training architecture included in a system memory controller and / or a PPS memory controller of a computer system of FIG.

[0022] Figure 3 According to various embodiments Figure 1 A block diagram of a training architecture for a memory device included in a system memory and / or a parallel processing memory of a computer system;

[0023] Figure 4 According to various embodiments Figure 1A block diagram of a linear feedback shift register (LFSR) subsystem of a memory device included in a system memory and / or a parallel processing memory of a computer system of the present invention; and

[0024] Figure 5 According to various embodiments Figure 1 A flowchart of method steps for executing a write training operation on a memory device included in a system memory and / or a parallel processing memory of a computer system. DETAILED DESCRIPTION

[0025] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of various embodiments. However, it will be apparent to one skilled in the art that the inventive concept may be practiced without one or more of these specific details.

[0026] System Overview

[0027] Figure 1 1 is a block diagram of a computer system 100 configured to implement one or more aspects of various embodiments. As shown, computer system 100 includes, but is not limited to, a central processing unit (CPU) 102 and a system memory 104 coupled to a parallel processing subsystem 112 via a memory bridge 105 and a communication path 113. Memory bridge 105 is coupled to system memory 104 via a system memory controller 130. Memory bridge 105 is further coupled to an I / O (input / output) bridge 107 via a communication path 106, which in turn is coupled to a switch 116. Parallel processing subsystem 112 is coupled to a parallel processing memory 134 via a parallel processing subsystem (PPS) memory controller 132.

[0028] In operation, I / O bridge 107 is configured to receive user input information from input device 108, such as a keyboard or mouse, and send the input information to CPU 102 where it is processed via communication path 106 and memory bridge 105. Switch 116 is configured to provide connections between I / O bridge 107 and other components of computer system 100, such as network adapter 118 and various add-in cards 120 and 121.

[0029] Continuing with the accompanying drawings, the I / O bridge 107 is coupled to a system disk 114, which may be configured to store content, applications, and data for the CPU 102 and the parallel processing subsystem 112. In general, the system disk 114 provides non-volatile storage for applications and data, and may include a fixed or removable hard drive, a flash memory device, a CD-ROM (compact disc read-only memory), a DVD-ROM (digital versatile disk-ROM), a Blu-ray, an HD-DVD (high-definition DVD), or other magnetic, optical, or solid-state storage device. Finally, although not explicitly shown, other components, such as a universal serial bus or other port connection, a compact disc drive, a digital versatile disk drive, a film recording device, etc., may also be connected to the I / O bridge 107.

[0030] In various embodiments, memory bridge 105 may be a northbridge chip, and I / O bridge 107 may be a southbridge chip. Furthermore, communication paths 106 and 113, as well as other communication paths within computer system 100, may be implemented using any technically suitable protocol, including but not limited to AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol known in the art.

[0031] In some embodiments, the parallel processing subsystem 112 includes a graphics subsystem that delivers pixels to the display device 110, which can be any conventional cathode ray tube, liquid crystal display, light emitting diode display, etc. In such an embodiment, the parallel processing subsystem 112 combines circuits optimized for graphics and video processing, including, for example, video output circuits. Such circuits may be included across one or more parallel processing units (PPUs) included in the parallel processing subsystem 112. In some embodiments, each PUPS includes a graphics processing unit (GPU), which can be configured to cause the graphics rendering pipeline to perform various operations on pixel data generated based on graphics data provided by the CPU 102 and / or the system memory 104. Each PPU can be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), a memory device), or in any other technically feasible manner.

[0032] In some embodiments, parallel processing subsystem 112 incorporates circuits optimized for general purpose and / or computational processing. Furthermore, such circuits may be included across one or more PPUs within parallel processing subsystem 112 that are configured to perform such general purpose and / or computational operations. In other embodiments, one or more PPUs within parallel processing subsystem 112 may be configured to perform graphics processing, general purpose processing, and computational processing operations. System memory 104 includes at least one device driver 103 configured to manage processing operations of one or more PPUs within parallel processing subsystem 112.

[0033] In various embodiments, the parallel processing subsystem 112 may be integrated Figure 1 For example, parallel processing subsystem 112 may be integrated with CPU 102 and other connected circuits on a single chip to form a system on a chip (SoC).

[0034] In operation, CPU 102 is the main processor of computer system 100, controlling and coordinating the operations of other system components. In particular, CPU 102 issues commands that control the operation of the PPUs within parallel processing subsystem 112. In some embodiments, CPU 102 writes the command stream of the PPUs within parallel processing subsystem 112 to a data structure ( Figure 1 The data structure may be located in system memory 104, PP memory 134, or another storage location accessible to both CPU 102 and PPU (not explicitly shown). A pointer to the data structure is written to a pushbuffer to start processing the command stream in the data structure. The PPU reads the command stream from the pushbuffer and then executes the commands asynchronously with respect to the operation of CPU 102. In an embodiment where multiple pushbuffers are generated, the application program, through device driver 103, may specify an execution priority for each pushbuffer to control the scheduling of different pushbuffers.

[0035] Each PPU includes an I / O (input / output) unit that communicates with the rest of the computer system 100 through the communication path 113 and the memory bridge 105. The I / O unit generates packets (or other signals) for transmission on the communication path 113, and also receives all incoming packets (or other signals) from the communication path 113, thereby directing the incoming packets to the appropriate elements of the PPU. The connection between the PPU and the rest of the computer system 100 may be different. In some embodiments, the parallel processing subsystem 112 including at least one PPU is implemented as an add-in card that can be inserted into an expansion slot of the computer system 100. In other embodiments, the PPU may be integrated with a bus bridge on a single chip, such as the memory bridge 105 or the I / O bridge 107. Furthermore, in other embodiments, some or all elements of the PPU may be included in a single integrated circuit or chip system (SoC) with the CPU 102.

[0036] The CPU 102 and PPU within the parallel processing system 112 access the system memory through the system memory controller 130. The system memory controller 130 sends signals to the memory device transfers in the system memory 104 to start the memory device, send commands to the memory device, write data to the memory device, read data from the memory device, etc. An example memory device employed in the system memory 104 is a double data rate SDRAM (DDR SDRAM, or more briefly DDR). DDR memory devices perform memory write and read operations at twice the data rate of previous generation single data rate (SDR) memory devices.

[0037] In addition, the PPU and / or other components within the parallel processing system 112 access the PP memory 134 through a parallel processing system (PPS) memory controller 132. The PPS memory controller 132 sends signals to memory devices in the PP memory 134 to start the memory devices, send commands to the memory devices, write data to the memory devices, read data from the memory devices, etc. The PP memory 134 is an example memory device used in synchronous graphics random access memory (SGRAM), which is a specialized form of SDRAM used for computer graphics applications. One specific type of SGRAM is a graphics double data rate SGRAM (GDDR SDRAM, or more briefly GDDR). Compared to DDR memory devices, GDDR memory devices are configured with a wider data bus to transfer more data bits per memory write and read operation. By using double data rate technology and a wider data bus, GDDR memory devices are able to achieve the high data transfer rates typically required by the PPU.

[0038] It will be appreciated that the system shown below is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of CPUs 102, and the number of parallel processing subsystems 112, may be modified as desired. For example, in some embodiments, system memory 104 may be directly connected to CPU 102 rather than through memory bridge 105, and other devices may communicate with system memory 104 through memory bridge 105 and CPU 102. In other alternative topologies, parallel processing subsystem 112 may be connected to I / O bridge 107 or directly to CPU 102 rather than to memory bridge 105. In other embodiments, I / O bridge 107 and memory bridge 105 may be integrated into a single chip rather than existing as one or more discrete devices. Finally, in some embodiments, there may be no memory bridge 105. Figure 1 For example, the switch 116 may be eliminated, and the network adapter 118 and the add-in cards 120, 121 may be directly connected to the I / O bridge 107.

[0039] It will be appreciated that the core architecture described below is illustrative and subject to variation and modification. Among other things, within the scope of the embodiments of the present disclosure, Figure 1 The computer system 100 may include any number of CPUs 102, parallel processing subsystems 112, or memory systems, such as system memory 104 and parallel processing memory 134. Further, as used herein, references to shared memory may include any one or more technically feasible memories, including but not limited to local memory shared by one or more PPUs within a parallel processing subsystem 112, memory shared between multiple parallel processing subsystems 112, cache memory, parallel processing memory 134, and / or system memory 104. Please also note that, as used herein, references to cache memory may include any one or more technically feasible memories, including but not limited to L1 cache, L1.5 cache, and L2 cache. In view of the foregoing, one of ordinary skill in the art will recognize that in Figure 1 The architecture described in the specification does not in any way limit the scope of the various embodiments of the present disclosure.

[0040] Performing write training operations on DRAM

[0041] Various embodiments are directed to techniques for efficiently performing write training of DRAM memory devices. The DRAM memory device includes one or more linear feedback shift registers (LFSRs) that generate write patterns in the form of pseudo-random bit sequences (PRBS). In some embodiments, each of several input pins of an interface (such as a data interface) undergoing a write training operation is coupled to a separate LFSR to check the PRBS pattern received on the corresponding input pin. To start write training, a memory controller associated with the memory device sends a reset command and / or a reset signal to the LFSR on the memory device to seed the LFSR. In response, the memory device seeds the LFSR with a predetermined seed value and / or polynomial. Additionally or alternatively, the memory controller sends a seed value and / or a polynomial to the memory device through another interface (such as a separate command address interface) that has been trained to seed the LFSR. In response, the memory device seeds the LFSR according to the seed value and / or polynomial received from the memory controller. In some embodiments, the memory controller includes a reset command, a reset signal, or a seed value and / or a polynomial in a write training command transmitted by the memory controller to the memory device through the command address interface. In some embodiments, the write training result register is self-cleared to an initial value when the memory device loads a seed value into the LFSR to prepare the write training result register to receive a pass / fail status (also referred to herein as a pass / fail result value) for the current write training operation.

[0042] During a write training operation, the memory controller sends a write training pattern to one or more interface pins on the memory device based on the same seed value and / or polynomial that the memory device uses to seed the LFSR. As the memory device receives the bit pattern, a write training checker on the one or more interface pins checks the incoming write training pattern on the one or more interface pins against the output of the LFSR in the memory device. In some embodiments, the PRBS checker for the input pins is implemented using exclusive OR (XOR) logic.

[0043] If the incoming write data pattern matches the data pattern generated by the LFSR in the memory device, the write training operation passes and the memory device records a pass status in the write training result register. However, if the incoming write data pattern does not match the data pattern generated by the LFSR in the memory device, the write training operation fails and the memory device records a fail status in the write training result register. In some embodiments, the write training result register includes a separate pass / fail status bit for each input pin that undergoes a write training operation.

[0044] During a write training operation, the memory controller periodically advances the LFSR on the memory controller by shifting the value in the LFSR on the memory controller. Accordingly, the memory controller sends a new write training command to the memory device. In response, the memory device advances the LFSR on the memory device by shifting the value in the LFSR on the memory device. In this way, the LFSR on the memory controller and the LFSR on the memory device maintain the same value during the write training operation. Therefore, the LFSR on the memory controller and the LFSR on the memory device generate the same data pattern during the write training operation.

[0045] When the memory device completes all or part of the write training operation, the memory controller reads the value in the write training result register to determine whether the write training operation passes or fails. In some embodiments, when the memory controller reads the value of the write training result register, the write training result register is self-cleared to an initial value. In some embodiments, the write training result register is initially cleared to indicate a failure state. Thereafter, the write training result register is updated as needed after each write training command to indicate whether the write training operation corresponding to the write training command passes or fails. When the status register is read to the memory controller, the status register is self-cleared again to indicate a failure state.

[0046] Figure 2 According to various embodiments, Figure 11 is a block diagram of a training architecture 200 included in the system memory controller 130 and / or the PPS memory controller 132 of the computer system 100.

[0047] The training architecture 200 includes a memory controller processor 226 that sends signals to components of the training architecture 200 included in the memory controller and to memory devices included in the system memory 104 and / or the PP memory 134. Figure 3 The training architecture 300 of FIG. 2 is shown in FIG. 2 . The memory controller processor 226 sends signals to start the memory device, send commands to the memory device, write data to the memory device, read data from the memory device, etc. The memory controller processor 226 generates commands to send to the memory device and sends the commands to the transmitter 208. The transmitter 208 in turn sends the commands to the memory device through the command address (CA) output pin 206.

[0048] In addition, the memory controller processor 226 sends a read / write command trigger to the read / write linear feedback shift register (R / W LFSR) 220, thereby generating a synchronous operation. The read / write command trigger can be in the form of a command, signal, etc. sent by the memory controller processor 226 and received by the R / W LFSR 220. The first synchronous operation generated by the read / write command trigger initializes the R / W LFSR 220 to a known state in order to generate a sequence value. The second synchronous operation generated by the read / write command trigger causes the R / W LFSR 220 to change from generating a current sequence value to generating a next sequence value. When the R / W LFSR 220 is initialized, the R / W LFSR 220 loads the LFSR seed value from the configuration register 234 to generate an initial sequence value. Before the R / W LFSR 220 is initialized, the memory controller processor 226 stores the LFSR seed value in the configuration register 234. When the R / W LFSR 220 is advanced, the R / W LFSR 220 advances from generating a current sequence value to a next sequence value. The memory controller processor 226 is used to advance Figure 3 The training architecture 300 initializes and advances the R / W LFSR 220 synchronously with the memory device of the R / W LFSR 320 in order to maintain synchronization between the R / W LFSR 220 and the R / W LFSR 320. In this way, the training architecture 300 can verify that the data received by the memory device matches the data sent by the training architecture 200 in the system memory controller.

[0049] The R / W LFSR 220 sends the sequence value to the encoder 230. The encoder 230 performs an encoding operation on the sequence value. The sequence value sent by the training architecture 200 to the DQ, DQX I / O, EDC pins 216 is usually encoded to optimize the signal transmission on the memory interface. The goal of sending encoded data on the physical I / O layer between the memory controller and the memory device is to optimize the data for signal transmission. The encoding optimizes the data to minimize the transition on the interface, minimize the crosstalk, reduce the consumption of the terminal circuit direct current (DC) power on the interface, etc. The data can be encoded by a maximum transition avoidance (MTA) operation to reduce the number of low-to-high and / or high-to-low signal transitions to improve the signal-to-noise ratio (SNR) on the memory interface. Additionally or alternatively, the data can be encoded by a data bus inversion (DBI) operation to reduce the number of high signal values ​​on the memory interface, thereby reducing the power consumed by the memory interface. Additionally or alternatively, the data can be encoded by any technically feasible operation.

[0050] The encoder 230 generates a coded sequence value to be sent to the memory device and transmits the coded sequence value to the transmitter 218. The transmitter 218 in turn transmits the coded sequence value to the memory device via one or more data (DQ), extended data (DQX), and / or error detection and correction (EDC) pins 216.

[0051] Figure 3 According to various embodiments Figure 1 1 is a block diagram of a training architecture 300 for a memory device included in the system memory 104 and / or the parallel processing memory 134 of the computer system 100. As further described, the training architecture 300 includes components for command address interface training, data read interface training, and data write interface training. Through these components, the training architecture 300 performs command address training operations, data read training operations, and data write training operations without storing training data in the DRAM core 326 of the memory device. When operating the memory device at a higher speed, the memory controller periodically performs these training operations so that setup time and hold time are met on all input pins and output pins of the memory device.

[0052] In general, the memory controller performs training operations in a specific order. First, the memory controller performs training operations on the command address interface. The command address interface training can be performed by any technically feasible technique. By first training the command address interface, the memory device is ready to receive commands and write mode registers as needed to perform data read interface training and data write interface training. In general, the command address interface does not need to be trained as long as the setup and hold times are met on all command address (CA) input pins 306. The memory controller causes the seed value and / or polynomial to be loaded into the command address linear feedback shift register (CALFSR) 310. The memory controller applies the data pattern to one or more CA input pins 306. The CA input pins 306 are sent to the CA LFSR 310 and the XOR gate 312 through the receiver 308. The CA LFSR 310 replicates the same pattern as the memory controller. The XOR gate 312 compares the data pattern on the CA input pins 306 with the data from the CA LFSR 310. If the data pattern on the CA input pins 306 matches the data from the CA LFSR 310, the XOR gate 312 sends a low value. If the data pattern on the CA input pin 306 does not match the data from the CA LFSR 310, the XOR gate 312 sends a high value. The pattern 304 of the input multiplexer 302 selects the bottom input to send the output of the XOR gate 312 to the transmitter 314 and then to one or more data (DQ), extended data (DQX) and / or error detection and correction (EDC) pins 316. The memory controller then reads one or more DQ, DQX and / or EDC pins 316 to determine whether the command address input training was successful. Once the command address input training is completed, the command address received from the memory controller passes through the CA input pin 306 and the receiver 308 and then reaches the DRAM core 326. In various embodiments, feedback from the memory device for different usage situations caused by interface training can be sent by the memory device to the memory controller through any one or more DQ, DQX and / or EDC pins 316 in any technically feasible combination.

[0053] After completing the command address interface training, the memory controller may send commands to the memory device to facilitate the data read interface training and the data write interface training. The memory device receives these commands through the CA input pin 306. The receiver 308 sends the commands from the CA input pin 306 to the command decoder 332. The command decoder 332 decodes the commands received from the training architecture 200 in the memory controller. Some commands are used to store values ​​to and / or load values ​​from the configuration register 334. For example, the command decoder 332 may receive a command to store a value in the configuration register 334 to store a linear feedback shift register (LFSR) seed value, which is loaded into the read / write linear feedback shift register (R / W LFSR) 320 each time the R / W LFSR 320 is initialized.

[0054] Some commands perform different operations in the memory device. For example, the command decoder 332 may receive a read command, and in response, the memory device performs a read operation to load data from the DRAM core 326 and sends the data to the memory controller. Similarly, the command decoder 332 may receive a write command, and in response, the memory device performs a write operation to store data received from the memory controller in the DRAM core 326. Further, if the command decoder 332 receives a read command or a write command during data read interface training or data write interface training, the command decoder 332 sends a trigger obtained from the read / write command to the R / W LFSR 320. The read / write command trigger initializes the R / W LFSR 320 to generate a first sequence value and / or advances the R / W LFSR 320 from a current sequence value to a next sequence value.

[0055] Second, the memory controller performs a training operation on the data read interface. Generally speaking, the training operation on the data read interface is performed before the training operation on the data write interface. The order of the training operation ensures that the data read from the memory device is correct, which allows the memory controller to perform the best write training operation. The memory controller sends a command to the memory device to load the seed value and / or polynomial into the R / W LFSR 320. The R / W LFSR 320 sends a series of sequence values ​​to the encoder 330 based on the seed value and / or polynomial.

[0056] The encoder 330 performs an encoding operation on the sequence value. The sequence value sent by the R / W LFSR 320 to the DQ, DQX I / O pin 316 is usually encoded to optimize the signal transmission on the memory interface. The goal of sending encoded data on the physical I / O layer between the memory controller and the memory device is to optimize the data for signal transmission. The encoding optimizes the data to minimize the transition on the interface, minimize crosstalk, reduce the amount of direct current (DC) power consumed by the terminal circuit on the interface, etc. The data can be encoded by a maximum transition avoidance (MTA) operation to reduce the number of low-to-high and / or high-to-low signal transitions to improve the signal-to-noise ratio (SNR) on the memory interface. Additionally or alternatively, the data can be encoded by a data bus inversion (DBI) operation to reduce the number of high signal values ​​on the memory interface so as to reduce the power consumed on the memory interface. Additionally or alternatively, the data can be encoded by any technically feasible operation.

[0057] The mode 304 of the input multiplexer 302 selects the top input to send the output of the encoder 330 to the transmitter 314 and then to one or more data (DQ), extended data (DQX), and / or error detection and correction (EDC) pins 316. The memory controller then reads the one or more DQ, DQX, and / or EDC pins 316 to determine whether the data received from the R / W LFSR 320 is in the expected pattern.

[0058] Third, the memory controller performs a training operation on the data write interface. The memory controller causes the seed value and / or polynomial to be loaded into the R / W LFSR 320. The memory controller applies a data pattern to one or more DQ, DQX, and / or EDC pins 316. The DQ, DQX, and / or EDC pins 316 are sent to the R / W LFSR 320 and the XOR gate 322 via the receiver 318. The R / W LFSR 320 replicates the same pattern as the R / W LFSR 220 on the memory controller. The encoder 330 encodes the pattern presented by the R / W LFSR 320 to replicate the encoded data received from the memory controller via the receiver 318. The XOR gate 322 encodes the data pattern on the DQ, DQX, and / or EDC pins 316 and the data from the encoder 330. If the data pattern on the CA input pin 306 matches the data from the encoder 330, the XOR gate 322 sends a low value. If the data pattern on the DQ, DQX, and / or EDC pins 316 does not match the data from the encoder 330, the XOR gate 322 sends a high value. The output of the XOR gate 322 is sent to the write training result register 324 and stores the pass / fail write training status for each DQ, DQX, and / or EDC pin 316 that undergoes write training. The memory controller reads the write training result register 324 to determine the result of the write training operation. When the memory controller reads the write training result register 324, the mode 304 of the input multiplexer 302 selects the second from the top input to send the output of the write training result register 324 to one or more DQ, DQX, and / or EDC pins 316 through the transmitter 314. The memory controller then reads one or more DQ, DQX, and / or EDC pins 316 to determine whether the data write training is successful. Once the data write training is completed, the write data received from the memory controller passes through the DQ, DQX, and / or EDC pins 316 and the receiver 318, and then reaches the DRAM core 326.

[0059] In some embodiments, once the fail status is stored in the write training result register 324, the fail status remains in the write training result register 324 until the memory device is reset. Even if a subsequent data write interface training operation results in a pass status, the fail status of the write training result register 324 will not change to a pass status. Instead, the write training result register 324 maintains the fail status of the previous failed data write interface training operation. In these embodiments, the fail status indicates at least one data write interface training operation performed since the last reset of the memory device caused the fail status. The fail status is cleared when the memory device is reset. The reset of the memory device is performed in response to reading a register that triggers a reset, by loading the R / W LFSR 220 according to a seed value, by receiving a signal on a reset pin of the memory device, etc.

[0060] Once the data read training and data write training are completed, the mode 304 of the input multiplexer 302 selects the second from the bottom input to send the output of the DRAM core 326 to the transmitter 314 and then to one or more data (DQ), extended data (DQX), and / or error detection and correction (EDC) pins 316.

[0061] It will be understood that the system shown below is illustrative and may be subject to variations and modifications. Among other things, the training architecture 300 includes components for command address interface training, data read interface training, and data write interface training. However, within the scope of the present disclosure, the training architecture 300 may include components for training any other technically feasible input and / or output interface. Further, in some instances, a single LFSR generates a source signal, such as a pseudo-random bit sequence (PRBS), for training any combination of one or more I / O pins of a memory device, including all I / O pins of a memory device. Additionally or alternatively, an LFSR may generate a PRBS for training any one or more I / O pins of a memory device. Additionally or alternatively, multiple LFSRs may generate a PRBS for one or more I / O pins of a memory device, as described above.

[0062] Figure 4 According to various embodiments Figure 1 1 is a block diagram of a linear feedback shift register (LFSR) subsystem 400 of a memory device included in the system memory 104 and / or the parallel processing memory 134 of the computer system 100. As shown, the LFSR subsystem 400 includes a plurality of LFSRs 410(0)-410(4) and a plurality of XOR gates 420(0)-420(3).

[0063] LFSR subsystem 400 includes LFSRs 410(0)-410(3) that directly generate a bit sequence, such as a pseudo-random bit sequence (PRBS) for a particular I / O pin of a memory device. Thus, DQ0 LFSR 410(0) generates DQ0 PRBS 430(0) for bit 0 of a data pin bus of the memory device. Similarly, DQ2 LFSR 410(2) generates DQ2 PRBS 430(2) for bit 2 of a data pin bus of the memory device. In a similar manner, DQ4 LFSR 410(4) generates DQ4 PRBS 430(4) for bit 4 of a data pin bus of the memory device, and DQ6 LFSR 410(6) generates DQ6 PRBS 430(6) for bit 6 of a data pin bus of the memory device. The error detection and correction (EDC) LFSR 410 (8) generates an EDC PRBS 430 (8) for the EDC bits of the EDC pin bus of the memory device.

[0064] LFSR subsystem 400 generates a PRBS for the remaining DQ bits based on any technically feasible two or more combinations of the outputs of DQ LFSRs 410(0)-(8) in LFSR subsystem 400. In some examples, LFSR subsystem 400 generates DQ1 PRBS 430(1) based on a logical combination of two or more other LFSRs, such as the output of XOR gate 420 that performs an XOR function on the outputs of DQ0 LFSR 410(0) and DQ2 LFSR 410(2). Similarly, LFSR subsystem 400 generates DQ3 PRBS 430(1) based on a logical combination of two or more other LFSRs, such as the output of XOR gate 422 that performs an XOR function on the outputs of DQ2 LFSR 410(2) and DQ4 LFSR 410(4).

[0065] LFSR subsystem 400 generates DQ5 PRBS 430(5) based on any technically feasible logical combination of the outputs of two or more other LFSRs, such as the output of XOR gate 424 that performs an XOR function on the outputs of DQ4 LFSR 410(4) and DQ6 LFSR 410(6). LFSR subsystem 400 generates DQ7 PRBS 430(7) based on logical combinations of two or more other LFSRs, such as the output of XOR gate 426 that performs an XOR function on the output of DQ6 LFSR 410(6) and the output of EDC LFSR 410(8). By sharing LFSRs among multiple outputs, LFSR subsystem 400 generates a unique PRBS for each output of a particular signal bus without requiring a separate LFSR for each signal bus output. In the above example, LFSR subsystem 400 includes only five LFSRs and still generates a unique PRBS for each of the eight signal bus outputs.

[0066] It is understood that the system shown herein is illustrative and that variations and modifications are possible. In some examples, the techniques described herein in conjunction with a data (DQ) pin of a memory device can be used for an extended data (DQX) pin, an error detection and correction (EDC) pin, a command address (CA) pin, and / or any other input / output pin of a memory device.

[0067] Additionally or alternatively, the patterns generated by the memory device may be subject to a coding scheme that reduces and / or eliminates the maximum transitions of training, such as a coding scheme based on phase amplitude modulation (PAM4) signaling parameters. As a result, the patterns generated by the memory device can eliminate the need to add complete MTA encoder logic, which can be expensive.

[0068] In some examples, when the LFSR subsystem 400 sends randomized LFSR data from the parallel processing subsystem 112 to the DRAM core 326, if the LFSR subsystem 400 does not perform some type of encoding to avoid maximum transitions, the training results may be negatively affected. Therefore, the training results may be suboptimal because conventional read / write operations avoid maximum transitions by using MTA encoding logic. Therefore, the LFSR subsystem 400 can perform low-overhead techniques to simulate the benefits of MTA without having to implement complete MTA encoding and decoding logic. These techniques involve detection of maximum transitions of random LFSR outputs. The technique converts the maximum transition on the random LFSR output into a non-maximum transition (0<->2, 0<->1, no transition, etc.). More generally, the encoding performed by the LFSR subsystem 400 can manipulate random data in order to simulate the characteristics of MTA encoding / decoding without adding complete MTA encoder / decoder logic to the LFSR subsystem 400.

[0069] Figure 5 According to various embodiments Figure 1 Flowchart of method steps for performing a write training operation in a memory device in the system memory 104 and / or the parallel processing memory 134 of a computer system. Figure 1-4 Although the method steps are described with reference to a system, one of ordinary skill in the art will understand that any system configured to perform the method steps in any order is within the scope of the present invention.

[0070] As shown, the method 500 begins at step 502, where the memory device initializes a write training LFSR (such as R / W LFSR 320) on the memory device according to a seed value. The memory controller causes the seed value and / or polynomial to be loaded into the R / W LFSR 320. To start write training, a memory controller associated with the memory device sends a reset command and / or reset signal to the R / W LFSR 320 on the memory device to seed the R / W LFSR 320. In response, the memory device seeds the R / W LFSR 320 with a predetermined seed value and / or polynomial. Additionally or alternatively, the memory controller sends the seed value and / or polynomial to the memory device through another interface (such as a separate command address interface) that has been trained to seed the R / W LFSR 320. In response, the memory device seeds the R / W LFSR 320 according to the seed value and / or polynomial received from the memory controller. In some embodiments, in the write training command sent by the memory controller to the memory device through the command address interface, the memory controller includes a reset command, a reset signal or a seed value and / or a polynomial. In some embodiments, when the memory device loads the seed value into the LFSR to prepare the write training result register to receive the pass / fail status of the current write training operation, the write training result register is self-cleared to the initial value.

[0071] The memory device receives the data pattern in the form of a signal on an input pin at step 504. The memory controller applies the data pattern to one or more DQ, DQX, and / or EDC pins 316.

[0072] At step 506, the memory device compares the signal on the input pins to the value in the write training LFSR, such as R / W LFSR 320. The DQ, DQX, and / or EDC pins 316 are sent through the receiver 318 to the R / W LFSR 320 and the XOR gate 322. The R / W LFSR 320 replicates the same pattern as the memory controller. The XOR gate 322 compares the data pattern on the DQ, DQX, and / or EDC pins 316 to the data from the R / W LFSR 320. If the data pattern on the CA input pins 306 matches the data from the R / W LFSR 320, the XOR gate 322 sends a low value. If the data pattern on the DQ, DQX, and / or EDC pins 316 does not match the data from the R / W LFSR 320, the XOR gate 322 sends a high value.

[0073] At step 508, the memory device records the result in a result register, such as a write training result register 324. The output of the XOR gate 322 is sent to the write training result register 324 and stores a pass / fail write training status for each DQ, DQX and / or EDC pin 316 that undergoes write training. The memory device optionally advances the R / W LFSR 320. During a write training operation, the memory controller periodically advances the LFSR on the memory controller by shifting the value in the LFSR on the memory controller. Accordingly, the memory controller sends a new write training command to the memory device. In response, the memory device advances the R / W LFSR 320 on the memory device by shifting the value in the R / W LFSR 320 on the memory device. In this way, the LFSR on the memory controller and the R / W LFSR 320 on the memory device maintain the same value during the write training operation. Therefore, the LFSR on the memory controller and the R / W LFSR 320 on the memory device generate the same data pattern during the write training operation.

[0074] At step 510, the memory device determines whether the write test is complete. The memory device may determine whether the test is complete based on completing multiple iterations of the write training operation, based on a command received from a memory controller, etc. If the memory device determines that the write test is not complete, the method 500 proceeds to step 504, as described above.

[0075] However, if the memory device determines that the write test is complete, the method 500 proceeds to step 512, where the memory device sends the result to the memory controller. When the memory device completes all or part of the write training operation, the memory controller reads the write training result register 324 to determine the result of the write training operation, thereby determining whether the write training operation passed or failed. When the memory controller reads the write training result register 324, the mode 304 of the input multiplexer 302 selects the second from the top input to send the output of the write training result register 324 through the transmitter 314, and then to one or more DQ, DQX and / or EDC pins 316. The memory controller then reads the one or more DQ, DQX and / or EDC pins 316 to determine whether the data write training is successful.

[0076] At step 514, the memory device clears the result register. In some embodiments, when the memory controller reads the value of the write training result register, the write training result register is self-cleared to the initial value. In some embodiments, the write training result register is initially cleared to indicate a failure state. Thereafter, the write training result register is updated as needed after each write training command to indicate whether the write training operation corresponding to the write training command passed or failed. When the status register is read to the memory controller, the status register is self-cleared again to indicate a failure state.

[0077] The method 500 then terminates. Alternatively, the method 500 proceeds to step 502 to perform additional write training operations.

[0078] In summary, various embodiments are directed to techniques for efficiently performing write training of DRAM memory devices. The DRAM memory device includes one or more linear feedback shift registers (LFSRs) that generate write patterns in the form of pseudo-random bit sequences (PRBS). In some embodiments, each of several input pins of an interface undergoing a write training operation, such as a data interface, is coupled to a corresponding LFSR to check the PRBS pattern received on the corresponding input pin. In order to start write training, a memory controller associated with the memory device sends a reset command and / or a reset signal to the LFSR on the memory device to seed the LFSR. In response, the memory device seeds the LFSR with a predetermined seed value and / or polynomial. Additionally or alternatively, the memory controller sends a seed value and / or polynomial to the memory device through another interface that has been trained, such as a separate command address interface, to seed the LFSR. In response, the memory device seeds the LFSR with a seed value and / or polynomial received from the memory controller. In some embodiments, in a write training command sent by the memory controller to the memory device through the command address interface, the memory controller includes a reset command, a reset signal, or a seed value and / or a polynomial. In some embodiments, when the memory device loads the seed value into the LFSR to prepare the write training result register to receive the pass / fail status for the current write training operation, the write training result register is self-cleared to the initial value.

[0079] During a write training operation, the memory controller sends a write training pattern to one or more interface pins on the memory device based on the same seed value and / or polynomial that the memory device uses to seed the LFSR. As the memory device receives the bit pattern, a write training checker on the one or more interface pins checks the incoming write training pattern on the one or more interface pins against the output of the LFSR in the memory device. In some embodiments, the PRBS checker for the input pins is implemented using XOR logic.

[0080] If the incoming write data pattern matches the data pattern generated by the LFSR of the memory device, the write training operation passes and the memory device records a pass status in the write training result register. However, if the incoming write data pattern does not match the data pattern generated by the LFSR of the memory device, the write training operation fails and the memory device records a fail status in the write training result register. In some embodiments, the write training result register includes a separate pass / fail status bit for each input pin that undergoes a write training operation.

[0081] During a write training operation, the memory controller periodically advances the LFSR on the memory controller by shifting the value in the LFSR on the memory controller. Accordingly, the memory controller sends a new write training command to the memory device. In response, the memory device advances the LFSR on the memory device by shifting the value in the LFSR on the memory device. In this way, the LFSR on the memory controller and the LFSR on the memory device maintain the same value during the write training operation. Therefore, the LFSR on the memory controller and the LFSR on the memory device generate the same data pattern during the write training operation.

[0082] When the memory device completes all or part of the write training operation, the memory controller reads the value in the write training result register to determine whether the write training operation passed or failed. In some embodiments, when the memory controller reads the value of the write training result register, the write training result register is self-cleared to an initial value. In some embodiments, the write training result register is initially cleared to indicate a failure state. Thereafter, the write training result register is updated as needed after each write training command to indicate whether the write training operation corresponding to the write training command passed or failed. When the status register is read to the memory controller, the status register is self-cleared again to indicate a failure state.

[0083] At least one technical advantage of the technology disclosed herein over the prior art is that, according to the technology disclosed herein, the lengthy write training data pattern sent to the memory device during the write training operation does not need to be stored in the memory device or read from the memory device to determine whether the write training operation is successful. Instead, the memory controller only needs to send the write training data pattern and read the pass / fail result to determine whether the write training operation is successful. Therefore, the write training operation is completed in about half the time relative to the prior art that requires reading the write training data pattern from the memory device.

[0084] Another advantage of the disclosed technology is that all pins of the data interface are trained simultaneously, resulting in shorter training time relative to conventional methods. In contrast, according to the conventional method of writing the data pattern to the DRAM memory core and then reading the data pattern back, only the data input / output pins themselves are trained. After the training of the data pins is completed, additional pins of the data interface that are not stored to the DRAM memory core are trained in a separate training operation. By using a PRBS pattern checker operating at the input / output pin level, all pins of the data interface are trained in parallel, further reducing the training time. These advantages represent one or more technical improvements relative to the prior art methods.

[0085] Any and all combinations of any claim elements recited in any claim and / or any elements described in this application, in any manner, are within the intended scope of the disclosure and protection.

[0086] The description of various embodiments has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the embodiments of the present disclosure. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.

[0087] Aspects of the present embodiment may be embodied as a system, method, or computer program product. Therefore, aspects of the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment (including firmware, resident software, microcode, etc.), or a combination of software and hardware embodiments, which may all be collectively referred to herein as a "module" or "system". In addition, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer-readable media having a computer-readable program code embodied thereon.

[0088] Any combination of one or more computer-readable media may be utilized. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, device or apparatus, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media would include the following: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with a command execution system, apparatus or device.

[0089] Aspects of the present disclosure are described above with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box of the flowchart and / or block diagram and the combination of the boxes in the flowchart and / or block diagram can be implemented by computer program commands. These computer program commands can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device, so as to produce a machine so that these computer program commands can implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram when executed by the processor of the computer or other programmable data processing device. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special-purpose processor or a field programmable gate array.

[0090] The flow chart and block diagram in the figure show the architecture, function and operation of the possible implementation of the system, method and computer program product according to each embodiment of the present disclosure. To this end, each box in the flow chart or block diagram may represent a module, fragment or part of the code, which includes one or more executable commands for realizing the specified logical function. It should also be noted that in some alternative embodiments, the function indicated in the box may not occur in the order indicated in the figure. For example, depending on the function involved, the two boxes shown in succession can actually be executed substantially at the same time, or these boxes can sometimes be executed in the opposite order. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer commands.

[0091] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the following claims.

Claims

1. A computer-implemented method for performing a write training operation on a memory device, the method comprising: initializing a first register on the memory device with a first data pattern based on a seed value stored in a second register; receiving a second data pattern on an input pin of the memory device; comparing the first data pattern and the second data pattern to generate a result value; as well as The result value is stored in a third register, wherein the result value indicates whether the write training operation is successful.

2. The computer-implemented method of claim 1 , further comprising: determining that the first data pattern matches the second data pattern, The result value indicates a passing result.

3. The computer-implemented method of claim 1 , further comprising: determining that the first data pattern does not match the second data pattern, The result value indicates a failure result.

4. The computer-implemented method of claim 1 , further comprising: receiving a command to read the result value; as well as The resulting value is sent to an output pin of the memory device.

5. The computer-implemented method of claim 4, further comprising: After sending the result value, the third register is initialized to an initial value.

6. The computer-implemented method of claim 1 , wherein comparing the first data pattern and the second data pattern comprises: An exclusive-OR (XOR) operation is performed on the first data pattern and the second data pattern.

7. The computer-implemented method of claim 6, wherein the result value is based on an output of the XOR operation.

8. The computer-implemented method of claim 1 , wherein initializing the first register comprises: receiving a reset command from a memory controller; as well as A predetermined value is stored in the first register.

9. The computer-implemented method of claim 1 , further comprising: After initializing the first register, the third register is initialized to an initial value.

10. The computer-implemented method of claim 9, wherein the initial value comprises a fail state.

11. The computer-implemented method of claim 1 , further comprising: receiving initial values ​​from a memory controller; as well as The initial value is stored in the first register.

12. The computer implemented method of claim 1, wherein the first register comprises a linear feedback shift register.

13. The computer-implemented method of claim 1, wherein at least one of the first data pattern or the second data pattern comprises a pseudo-random bit sequence.

14. A system comprising: Memory controller; as well as a memory device coupled to the memory controller, which: initializing a first register on the memory device with a first data pattern based on a seed value stored in a second register; receiving a second data pattern from the memory controller on an input pin of the memory device; comparing the first data pattern and the second data pattern to generate a result value; and The result value is stored in a third register.

15. The system of claim 14, wherein the memory device further: determining that the first data pattern matches the second data pattern, The result value indicates a passing result.

16. The system of claim 14, wherein the memory device further: determining that the first data pattern does not match the second data pattern, The result value indicates a failure result.

17. The system of claim 14, wherein the memory device further: receiving a command to read the result value; and The resulting value is sent to an output pin of the memory device.

18. The system of claim 17, wherein after sending the result value, the memory device further initializes the third register to an initial value.

19. The system of claim 14, wherein when the memory device compares the first data pattern and the second data pattern, the memory device performs an exclusive-OR (XOR) operation on the first data pattern and the second data pattern.

20. The system of claim 19, wherein the result value is based on an output of the XOR operation.

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