Memory refresh rate management method, system, storage medium and device

Abstract

The present invention provides a memory refresh rate management method, system, storage medium and device, the method comprising: simulating the refresh rate, temperature and capacitance state in combination with the use environment of the memory, and storing a basic model established based on the simulation results in a memory controller; the memory controller obtains the real-time temperature of the memory body, and obtains a real-time function model of the capacitance charge and the charge and discharge time in combination with the basic model; in response to the capacitor being charged after a read and write operation and its charge dropping to a service threshold, the memory is refreshed; the memory controller obtains the memory temperature change and the memory particle access frequency monitored by the monitor; in response to the abnormality of the linear function of the temperature change over time and / or the abnormality of the data access address distribution, the data encryption function is turned on and / or the memory refresh rate is increased. According to the present invention, the problem of frequent memory read and write errors when the temperature and memory self-refresh frequency are not properly matched can be effectively solved, thereby improving the user service quality.

Description

Technical Field

[0001] The present invention relates to the field of server technology, in particular to the field of server memory technology, and specifically to a server memory refresh rate. Background Art

[0002] With the continuous rise and development of cloud computing technology and its related derivative technologies and products, the volume of business in the internet industry has gradually experienced explosive growth. As the physical carrier of virtual data, servers' storage, processing, and interactive capabilities fundamentally determine the upper limit of cloud computing. With the growth of internet user traffic, network real-time data throughput has also increased exponentially, bringing with it challenges to the performance of server nodes throughout the entire data center.

[0003] In current server architectures, memory plays a crucial role, second only to the CPU (Central Processing Unit). Memory reliability, availability, and serviceability largely determine a server node's performance bottlenecks and actual business performance.

[0004] In the current industry landscape, the trend toward centralized computing and processing resources through multi-node, multi-cabinet computing clusters is undeniable. For example, on Intel's EagleStream platform, a single CPU in a typical X86 server can support eight memory channels, or 16 memory sticks. However, for the most common and widely used two-way (two-CPU) server, a single node would need to support 32 memory sticks. A computing center often has thousands of nodes, requiring a staggering amount of memory. Ensuring memory reliability with such a massive workload is both crucial and challenging.

[0005] Some memory currently available on the market supports ECC (Error Checking and Correcting), which corrects single-bit errors and checks two-bit errors. When a CE (Correctable Error) occurs, ECC memory corrects the error and reports it to the system. Although the error is corrected, this behavior can significantly impact server node performance. When the number of reported errors reaches a certain level, it can have a noticeable impact on ongoing services.

[0006] Generally speaking, memory can be narrowly understood as many storage particles integrated on a PCB (Printed Circuit Board) and connected to the motherboard through gold fingers.

[0007] A single memory chip is a Bank, several Banks stacked together are a BankGroup, several BankGroups together are a Rank, and several Ranks together are a DIMM (Dual-Inline-Memory-Modules). A single Bank can be understood as an abstract logical space with rows and columns, which implements data storage in the form of a matrix, such as Figure 1 shown.

[0008] As for the underlying physical link of the actual Bank, Figure 2 As shown, it can be understood as a lot of small capacitors. Each small capacitor represents a register, which is charged and discharged. Its default state depends on the specific hardware settings. Figure 2 .

[0009] The method of counting by charging and discharging capacitors brings high read and write speed and response speed as well as large capacity of erasable and writable space to the memory, but it is also this mechanism that brings memory errors. For a storage unit, as long as it is not read or written for a period of time and no operation is performed on it, its capacitor will gradually discharge. When it is discharged to a certain extent (refer to Figure 3 Schematic diagram), it will have a devastating impact on the logical judgment of its registers.

[0010] Therefore, according to JEDEC specifications, a refresh action must be performed at least every 64ms to charge the capacitor to ensure data accuracy.

[0011] At the same time, since this working mechanism relies on the charging and discharging of capacitors, it is strongly related to the electronic properties of metals, which in turn are strongly related to temperature. When the temperature is low, electrons are inert, so the rate of capacitor leakage will be lower than at room temperature, and the bit error rate will also be lower; when the temperature is high, the electronic activity increases, and the rate of capacitor leakage also becomes faster. According to the JEDEC 64ms requirement, the bit error rate may be greatly improved in some cases.

[0012] At the same time, when the same row of data in the same bank is accessed repeatedly and quickly, an electric field will be formed around it, which will have a serious impact on the surrounding rows and accelerate their leakage rate. In this case, it is even possible to forcibly tamper with the data content in other rows, posing a great threat to the security of the entire system.

[0013] Commonly used DDR4 and DDR5 memory devices support "Temperature Controlled Refresh Modes" according to JEDEC specifications. This means that when the memory state machine is in the Refresh state, the capacitor self-refresh rate is adjusted based on the temperature. This is achieved by setting registers on the memory device based on the measured temperature.

[0014] To save power, reduce latency, and reduce bandwidth, a common approach is to set the refresh rate to 0.5x when the temperature is below 45°C, default to single refresh between 45°C and 85°C, and trigger double refresh when the temperature is above 85°C. This design has an obvious problem: the refresh rate control is too coarse.

[0015] In addition, existing technologies have proposed methods for optimizing memory refresh rates. These methods generally involve performing read and write tests on the memory to obtain a set of empirical data, finding the frequency with the lowest bit error rate at different temperatures, and optimizing the frequency. This method has three problems: First, obtaining empirical data solely through read and write tests on the memory is too crude; second, this method was proposed too early, and the current new generation of DDR4 already supports dynamic regulation at different temperatures, so the improvement is not significant compared to this; third, this refresh rate regulation strategy does not take into account the situation where the memory itself is vulnerable to bypass attacks such as RowHammer, and needs to be optimized.

[0016] In summary, existing solutions for dynamically controlling memory self-refresh frequency still have a lot of room for improvement. Therefore, in view of the above shortcomings and problems in the existing technology, it is necessary to propose an optimized memory refresh rate management method to solve or improve the above situation. Summary of the Invention

[0017] In view of this, the purpose of the present invention is to provide an improved memory refresh rate management method, system, storage medium and device, so as to solve the problems existing in the prior art.

[0018] Based on the above objectives, on one hand, the present invention provides a memory refresh rate management method, wherein the method comprises the following steps:

[0019] Simulate the refresh rate, temperature, and capacitance status based on the memory usage environment, and store the basic model based on the simulation results in the memory controller;

[0020] The memory controller obtains the real-time temperature of the memory body and obtains a function model of the real-time capacitance and charge and discharge time in combination with the basic model;

[0021] In response to the capacitor being charged by a read and write operation and the amount of the capacitor falling to a service threshold, refreshing the memory;

[0022] The memory controller obtains the memory temperature changes and memory particle access frequency monitored by the monitor;

[0023] In response to abnormality in the linear function of temperature change over time and / or abnormality in data access address distribution, a data encryption function is enabled and / or a memory refresh rate is increased.

[0024] In some embodiments of the memory refresh rate management method according to the present invention, simulating the refresh rate, temperature, and capacitance state in combination with the memory usage environment and storing a basic model established based on the simulation results in the memory controller further includes:

[0025] The capacitance, charge and discharge time, and temperature are simulated in combination with the capacitance temperature coefficient of the capacitor used in the memory, and a basic model is established based on the simulation results.

[0026] In some embodiments of the memory refresh rate management method according to the present invention, in response to the capacitor being charged after a read / write operation and its charge level dropping to a service threshold, refreshing the memory further comprises:

[0027] After the capacitor is charged through one reading and writing, the amount of electricity is calculated based on a function model of the amount of electricity in the capacitor and the charging and discharging time and compared with the service threshold.

[0028] In some embodiments of the memory refresh rate management method according to the present invention, enabling the data encryption function and / or increasing the memory refresh rate in response to an abnormal linear function of temperature change over time and / or an abnormal data access address distribution further includes:

[0029] In response to detecting a rapid abnormal temperature drop based on a linear function of temperature change over time, sending an instruction to the BIOS to enable a data encryption function; and / or

[0030] In response to data access requests being abnormally concentrated in the same area, a memory refresh rate is set to an integer multiple of the current refresh rate until the data access situation returns to normal.

[0031] Another aspect of the present invention further provides a memory refresh rate management system, comprising:

[0032] A memory simulation module configured to simulate the refresh rate, temperature, and capacitance state in combination with the memory usage environment, and store a basic model established based on the simulation results in the memory controller;

[0033] A function model building module configured to obtain the real-time temperature of the memory body by the memory controller and to obtain a function model of the real-time capacitance and charge / discharge time in combination with the basic model;

[0034] a memory refresh execution module, the memory refresh execution module being configured to refresh the memory in response to the capacitor being charged after a read / write operation and the amount of the capacitor dropping to a service threshold;

[0035] A memory status monitoring module configured to obtain memory temperature changes and memory chip access frequencies monitored by a monitor from a memory controller;

[0036] A state abnormality protection module is configured to enable a data encryption function and / or increase a memory refresh rate in response to an abnormal linear function of temperature change over time and / or an abnormal data access address distribution.

[0037] In some embodiments of the memory refresh rate management system according to the present invention, the memory emulation module is further configured to:

[0038] The capacitance, charge and discharge time, and temperature are simulated in combination with the capacitance temperature coefficient of the capacitor used in the memory, and a basic model is established based on the simulation results.

[0039] In some embodiments of the memory refresh rate management system according to the present invention, the memory refresh execution module is further configured to:

[0040] After the capacitor is charged through one reading and writing, the amount of electricity is calculated based on a function model of the amount of electricity in the capacitor and the charging and discharging time and compared with the service threshold.

[0041] In some embodiments of the memory refresh rate management system according to the present invention, the abnormal state protection module is further configured to:

[0042] In response to detecting a rapid abnormal temperature drop based on a linear function of temperature change over time, sending an instruction to the BIOS to enable a data encryption function; and / or

[0043] In response to data access requests being abnormally concentrated in the same area, a memory refresh rate is set to an integer multiple of the current refresh rate until the data access situation returns to normal.

[0044] In another aspect of the present invention, a computer-readable storage medium is provided, storing computer program instructions, which, when executed, implement any of the above-mentioned memory refresh rate management methods according to the present invention.

[0045] In another aspect of the present invention, a computer device is provided, comprising a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, any one of the above-mentioned memory refresh rate management methods according to the present invention is executed.

[0046] The present invention has at least the following beneficial technical effects: Based on the method of the present invention, instead of relying solely on the refresh temperature mechanism specified by the JEDEC specification, a more precise method is adopted for regulation, effectively improving the reliability of memory storage, reducing the probability of uncorrectable errors (UCE), improving the RAS (Reliability, Availability, and Serviceability) performance of the entire machine, and improving service quality. In addition, a security mechanism against physical attacks and side-channel attacks is added, thereby improving the security of memory data and the automation level of the security system. According to the present invention, the problem of frequent memory read and write errors (CE and UCE) when the temperature and memory self-refresh frequency are not properly matched can be effectively solved, thereby improving user service quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying any creative work.

[0048] In the figure:

[0049] Figure 1 Shows the Bank logic abstract schematic diagram;

[0050] Figure 2 The diagram shows the underlying physical link of the Bank and its capacitor charging and discharging link.

[0051] Figure 3 The diagram shows the relationship between the memory chip capacitance and logic judgment;

[0052] Figure 4 Shows a schematic diagram of the working mechanism of a single capacitor in a memory chip;

[0053] Figure 5 A schematic block diagram of an embodiment of a memory refresh rate management method according to the present invention is shown;

[0054] Figure 6 A schematic diagram showing a flow chart of an embodiment of a memory refresh rate management method according to the present invention is shown;

[0055] Figure 7 A schematic diagram of bit error rate optimization according to an embodiment of a memory refresh rate management method of the present invention is shown;

[0056] Figure 8The invention shows the security and automation optimization intention of the memory refresh rate management method according to the embodiment of the present invention;

[0057] Figure 9 A schematic block diagram of an embodiment of a memory refresh rate management system according to the present invention is shown;

[0058] Figure 10 A schematic diagram illustrating an embodiment of a computer-readable storage medium for implementing a memory refresh rate management method according to the present invention is shown;

[0059] Figure 11 A schematic diagram of the hardware structure of an embodiment of a computer device implementing a memory refresh rate management method according to the present invention is shown. DETAILED DESCRIPTION

[0060] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0061] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are intended to distinguish two non-identical entities or non-identical parameters with the same name. Therefore, "first" and "second" are used for convenience of expression only and should not be understood as limitations on the embodiments of the present invention. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, other steps or units inherent to a process, method, system, product, or device that includes a series of steps or units.

[0062] Simply put, the purpose of the present invention is to achieve dynamic regulation of the memory self-refresh frequency at different temperatures to reduce the memory bit error rate, thereby improving the overall performance of the server and optimizing the user service experience; at the same time, considering the situation where the memory is subjected to physical attacks or side-channel attacks, the security strategy is optimized.

[0063] To this end, the working mechanism and principle on which the present invention is based are first explained.

[0064] Figure 4 The diagram shows a single capacitor in a memory chip. The capacitor is responsible for storage. When charged, it represents 1, and when uncharged, it represents 0. For capacitors, their charging and discharging have inherent physical laws. For a common RC circuit (resistor-capacitance circuit), the time constant τ = RC, and the capacitor voltage u c = U × [1-e(-t / τ)], combined with the specific physical link, the charge and discharge time of the capacitor can be calculated. However, unlike common hardware links, this requires the addition of a variable: temperature.

[0065] Although manufacturers have tried their best to achieve higher temperature stability for capacitors through their own unique means, for the memory usage environment, even a slight temperature change can have a great impact under such high-frequency switching and charging and discharging.

[0066] In a working environment such as memory, there are four aspects that need to be considered regarding the impact of temperature on its charging and discharging: first, the impact of temperature on the life of the capacitor; second, the impact of temperature on the loss of the capacitor; third, the impact of temperature on the insulation resistance of the capacitor. Generally, the insulation resistance decreases with increasing temperature. When the insulation resistance is low, the leakage current of the capacitor will increase, which will affect the working performance of the capacitor; fourth, the impact of temperature on the capacitance of the capacitor. This parameter has the greatest impact on the calculation method of the present invention. Capacitor manufacturers generally also conduct actual tests and simulations on temperature-related parameters. Combining these data, the optimized value based on the capacitor charging and discharging formula mentioned above can be obtained. Of course, after taking into account the impact of temperature, this function is a three-dimensional function that can be described by simulation software.

[0067] Recombination Figure 3 The memory chip's judgment logic for the capacitor charge can be used to optimize the refresh frequency (time) at different temperatures based on the basic model obtained in the first step.

[0068] To this end, a first aspect of the present invention provides a memory refresh rate management method 100. Figure 5 FIG. 1 is a schematic block diagram showing an embodiment of a memory refresh rate management method according to the present invention. Figure 5 In the illustrated embodiment, the method includes:

[0069] Step S110: Simulating the refresh rate, temperature, and capacitance state in combination with the memory usage environment, and storing a basic model established based on the simulation results in the memory controller;

[0070] Step S120: the memory controller obtains the real-time temperature of the memory body, and obtains a function model of the real-time capacitance and charge / discharge time in combination with the basic model;

[0071] Step S130: in response to the capacitor being charged by a read and write operation and its charge level dropping to a service threshold, refreshing the memory;

[0072] Step S140: The memory controller obtains the memory temperature change and memory chip access frequency monitored by the monitor;

[0073] Step S150: In response to the abnormality of the linear function of temperature change over time and / or the abnormality of data access address distribution, turning on the data encryption function and / or increasing the memory refresh rate.

[0074] In general, to address the aforementioned issues in the prior art, it is first necessary to establish a model for the real-time state of the memory and perform simulations. To this end, in step S110, the refresh rate, temperature, and capacitance state are simulated in conjunction with the memory's usage environment. The basic model established based on the simulation results is stored in the memory controller MC (Memory Controller). In step S120, the memory controller obtains the real-time temperature of the memory itself for different applications and, based on this basic model, generates a functional model of the real-time capacitance and charge / discharge time at that temperature.

[0075] On this basis, when the capacitor is charged after one read and write operation and it is determined that the charge level thereof drops to the service threshold, the memory is refreshed in step S130 .

[0076] Then, considering the possibility that the memory body is subjected to abnormal attacks (such as physical attacks or side-channel attacks), the security policy is optimized. In step S140, the memory controller obtains the memory temperature changes and memory particle access frequency monitored by the monitor.

[0077] Once it is found that the linear function of temperature change over time is abnormal and / or the data access address distribution is abnormal, the data encryption function is turned on and / or the memory refresh rate is increased in step S150 to achieve hardware memory system security and automatic optimization.

[0078] Figure 6 This is a schematic diagram of the memory refresh rate management optimization method based on the underlying physical link of the memory of the present invention. Figure 6 Give a detailed description of the entire optimization method.

[0079] First, as mentioned above, the three factors of "capacitance - charge and discharge time - temperature" are simulated in combination with the capacitance temperature coefficient of the capacitor used in the memory, and the established basic model and further function model are written into the MC.

[0080] Therefore, in some embodiments of the memory refresh rate management method 100 according to the present invention, the refresh rate, temperature, and capacitance status are simulated in combination with the memory usage environment, and the basic model established based on the simulation results is stored in the memory controller, which further includes: simulating the capacitance charge, charging and discharging time, and temperature in combination with the capacitance temperature coefficient of the capacitor used by the memory, and establishing a basic model based on the simulation results.

[0081] There will be a temperature sensor on the memory body. MC obtains the real-time temperature of the memory body through the sensor and then makes logical judgments based on the model obtained by previous simulation.

[0082] Therefore, in some embodiments of the memory refresh rate management method 100 according to the present invention, in response to the capacitor being charged after a read and write operation and its charge level dropping to a service threshold, refreshing the memory further includes: after the capacitor is charged after a read and write operation, calculating the charge level based on a function model of the capacitor charge level and the charge and discharge time and comparing it with the service threshold.

[0083] After the capacitor is charged through a read and write operation, its charge level is determined based on the aforementioned function model. When its charge level drops to a business threshold (e.g., 85%, 80%, 75%, 70%, etc.), it is refreshed (the threshold here can be adjusted based on the user's actual business accuracy requirements). This ensures that the capacitor in the memory particle is always at a correct and stable readable and writable logic level, achieving the optimal solution for memory self-refresh frequency and bit error rate at different temperatures.

[0084] Secondly, the present invention also takes into account physical attacks on the memory (such as Cold Boot, which uses low temperature to artificially extend the capacitor discharge time to achieve violent data acquisition) and side-channel attacks (such as Bank Hammer, which forms a large electromagnetic field by repeatedly accessing the same row of the same particle at high speed, accelerating the capacitor discharge and illegally tampering with the data in the surrounding rows).

[0085] To this end, according to the present invention, a monitor function is provided in the memory controller MC. While obtaining the temperature of the memory body, it determines whether the linear function of temperature change over time is normal. If a rapid abnormal temperature drop occurs, it is determined that the memory has been physically attacked, and an instruction is sent to the BIOS to turn on the data encryption function (such as Intel's TME or AMD's SME and other technologies. The specific encryption logic can also be optimized in combination with this system).

[0086] The monitor also monitors bank data access. If it finds access requests concentrated in the same area (for example, the same row) within a short period of time, it considers the memory to have been attacked by a side channel. It then sets the memory refresh rate to an integer multiple, preferably X2, until the access frequency returns to normal. This ensures hardware-based memory system security and automated optimization.

[0087] Therefore, in some embodiments of the memory refresh rate management method 100 according to the present invention, enabling the data encryption function and / or increasing the memory refresh rate in response to abnormal linear function of temperature change over time and / or abnormal data access address distribution further includes:

[0088] In response to detecting a rapid abnormal temperature drop based on a linear function of temperature change over time, sending an instruction to the BIOS to enable a data encryption function; and / or

[0089] In response to data access requests being abnormally concentrated in the same area, a memory refresh rate is set to an integer multiple of the current refresh rate until the data access situation returns to normal.

[0090] In order to further illustrate the implementation of the method according to the present invention, Figure 7 and Figure 8 Explain in detail. Figure 7 As shown, the refresh rate, temperature, and capacitance are first simulated in conjunction with the specific operating environment. For specific simulation steps, refer to the previous embodiment. The MC then arbitrates the refresh rate based on the simulation results and the actual operating environment, obtaining the most accurate refresh rate for the capacitor logic level. This achieves adaptive optimization of the memory refresh rate based on the operating environment temperature, reducing the memory system bit error rate and improving service efficiency and accuracy.

[0091] In addition, in order to achieve safety and automation optimization, such as Figure 8 As shown in the figure, the MC monitors temperature changes and data access in real time. If it detects an abnormal temperature drop or an unusually concentrated distribution of data access addresses, the MC decides to enable TME encryption or set the memory self-refresh frequency to an integer multiple (preferably 2) of the original frequency, achieving security and automated optimization of the memory system.

[0092] Based on the aforementioned embodiments of the present invention, the present invention establishes a "bit error rate - capacitor charge - charge and discharge time - temperature" model based on the underlying physical storage mechanism of memory to optimize the memory self-refresh frequency control mechanism and improve service reliability. Furthermore, the present invention establishes a corresponding monitoring mechanism based on the underlying physical storage mechanism of memory to automatically prevent physical attacks and side-channel attacks.

[0093] It should be noted that the function model used for control can also be constructed in combination with specific machine models and working environments by adding variables such as "ambient humidity, vibration, impact, acceleration, atmospheric pressure", which is scalable.

[0094] The second aspect of the present invention further provides a memory refresh rate management system 200. Figure 9 FIG. 2 shows a schematic block diagram of an embodiment of a memory refresh rate management system 200 according to the present invention. Figure 9 As shown, the system includes:

[0095] A memory simulation module 210 configured to simulate the refresh rate, temperature, and capacitance state in combination with the memory usage environment, and store a basic model established based on the simulation results in the memory controller;

[0096] A function model building module 220 is configured to obtain the real-time temperature of the memory body by the memory controller, and to obtain a function model of the real-time capacitance and charge / discharge time in combination with the basic model;

[0097] a memory refresh execution module 230 configured to refresh the memory in response to the capacitor being charged after a read / write operation and the charge level thereof dropping to a service threshold;

[0098] A memory status monitoring module 240 configured to obtain memory temperature changes and memory chip access frequencies monitored by a monitor from a memory controller;

[0099] The state abnormality protection module 250 is configured to enable data encryption function and / or increase memory refresh rate in response to abnormal linear function of temperature change over time and / or abnormal data access address distribution.

[0100] In some embodiments of the memory refresh rate management system 200 according to the present invention, the memory emulation module 210 is further configured to:

[0101] The capacitance, charge and discharge time, and temperature are simulated in combination with the capacitance temperature coefficient of the capacitor used in the memory, and a basic model is established based on the simulation results.

[0102] In some embodiments of the memory refresh rate management system 200 according to the present invention, the memory refresh execution module 230 is further configured to:

[0103] After the capacitor is charged through one reading and writing, the amount of electricity is calculated based on a function model of the amount of electricity in the capacitor and the charging and discharging time and compared with the service threshold.

[0104] In some embodiments of the memory refresh rate management system 200 according to the present invention, the abnormal state protection module 250 is further configured to:

[0105] In response to detecting a rapid abnormal temperature drop based on a linear function of temperature change over time, sending an instruction to the BIOS to enable a data encryption function; and / or

[0106] In response to data access requests being abnormally concentrated in the same area, a memory refresh rate is set to an integer multiple of the current refresh rate until the data access situation returns to normal.

[0107] A third aspect of the embodiments of the present invention further provides a computer-readable storage medium. Figure 10 FIG. 1 is a schematic diagram showing a computer-readable storage medium of a memory refresh rate management method according to an embodiment of the present invention. Figure 10As shown, the computer-readable storage medium 300 stores computer program instructions 310, which can be executed by a processor. When the computer program instructions 310 are executed, the method of any one of the above embodiments is implemented.

[0108] It should be understood that, to the extent that they do not conflict with each other, all the embodiments, features, and advantages described above for the memory refresh rate management method according to the present invention are also applicable to the memory refresh rate management system and storage medium according to the present invention.

[0109] According to a fourth aspect of the embodiments of the present invention, a computer device 400 is provided, including a memory 420 and a processor 410. The memory stores a computer program, and when the computer program is executed by the processor, the method of any one of the above embodiments is implemented.

[0110] like Figure 11 As shown in FIG, a hardware structure diagram of an embodiment of a computer device for executing a memory refresh rate management method provided by the present invention is shown. Figure 11 Taking the computer device 400 shown as an example, the computer device includes a processor 410 and a memory 420, and may also include: an input device 430 and an output device 440. The processor 410, the memory 420, the input device 430 and the output device 440 can be connected via a bus or other means. Figure 11 The input device 430 can receive input digital or character information and generate signal input related to memory refresh rate management. The output device 440 can include a display device such as a display screen.

[0111] The memory 420, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as the program instructions / modules corresponding to the resource monitoring method in the embodiment of the present application. The memory 420 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required for at least one function; and the data storage area may store data created by the use of the resource monitoring method, etc. In addition, the memory 420 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 420 may optionally include a memory remotely located relative to the processor 410, and these remote memories may be connected to the local module via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0112] The processor 410 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions and modules stored in the memory 420, that is, implements the resource monitoring method of the above method embodiment.

[0113] Finally, it should be noted that the computer-readable storage medium (e.g., memory) herein may be a volatile memory or a non-volatile memory, or may include both a volatile memory and a non-volatile memory. By way of example and not limitation, the non-volatile memory may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. The volatile memory may include a random access memory (RAM), which may act as an external cache memory. By way of example and not limitation, RAM may be obtained in a variety of forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to include, but are not limited to, these and other suitable types of memory.

[0114] It will also be appreciated by those skilled in the art that the various exemplary logic blocks, modules, circuits and algorithmic steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, a general description has been given of the functions of various schematic components, blocks, modules, circuits and steps. Whether this function is implemented as software or hardware depends on specific applications and the design constraints imposed on the entire system. Those skilled in the art can implement the function in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the disclosed scope of the embodiments of the present invention.

[0115] The various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure herein may be implemented or executed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and / or any other such configuration.

[0116] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope of the embodiments disclosed in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless expressly limited to the singular.

[0117] It should be understood that, as used herein, the singular form "a" or "an" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the items listed in association. The serial numbers of the embodiments disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0118] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples. Within the spirit of the embodiments of the present invention, the technical features of the above embodiments or different embodiments may be combined, and there are many other variations of different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the scope of protection of the embodiments of the present invention.

Claims

1. A memory refresh rate management method, characterized in that: The following steps are involved: Simulate the refresh rate, temperature, and capacitance status based on the memory usage environment, and store the basic model based on the simulation results in the memory controller; The memory controller obtains the real-time temperature of the memory body and obtains a function model of the real-time capacitance and charge and discharge time in combination with the basic model; In response to the capacitor being charged by a read and write operation and the amount of the capacitor falling to a service threshold, refreshing the memory; The memory controller obtains the memory temperature changes and memory particle access frequency monitored by the monitor; In response to abnormal linear function of temperature change over time and / or abnormal data access address distribution, turning on a data encryption function and / or increasing a memory refresh rate; Among them, in response to the capacitor undergoing a read-write charging and its charge dropping to a business threshold, refreshing the memory further includes: after the capacitor undergoes a read-write charging, calculating the charge based on a function model of the capacitor charge and the charging and discharging time and comparing it with the business threshold.

2. The method according to claim 1, characterized in that The simulating of the refresh rate, temperature, and capacitance state in combination with the usage environment of the memory and storing the basic model established based on the simulation results in the memory controller further includes: The capacitance, charge and discharge time, and temperature are simulated in combination with the capacitance temperature coefficient of the capacitor used in the memory, and a basic model is established based on the simulation results.

3. The method according to claim 1 or 2, characterized in that The enabling of the data encryption function and / or increasing the memory refresh rate in response to abnormal linear function of temperature change over time and / or abnormal data access address distribution further includes: In response to detecting a rapid abnormal temperature drop based on a linear function of temperature change over time, sending an instruction to the BIOS to enable a data encryption function; and / or In response to data access requests being abnormally concentrated in the same area, a memory refresh rate is set to an integer multiple of the current refresh rate until the data access situation returns to normal.

4. A memory refresh rate management system, characterized in that: include: A memory simulation module configured to simulate the refresh rate, temperature, and capacitance state in combination with the memory usage environment, and store a basic model established based on the simulation results in the memory controller; A function model building module configured to obtain the real-time temperature of the memory body by the memory controller and to obtain a function model of the real-time capacitance and charge / discharge time in combination with the basic model; a memory refresh execution module, the memory refresh execution module being configured to refresh the memory in response to the capacitor being charged after a read / write operation and the amount of the capacitor dropping to a service threshold; A memory status monitoring module configured to obtain memory temperature changes and memory chip access frequencies monitored by a monitor from a memory controller; a state abnormality protection module, the state abnormality protection module being configured to enable a data encryption function and / or increase a memory refresh rate in response to an abnormal linear function of temperature change over time and / or an abnormal data access address distribution; The memory refresh execution module is further configured to: after the capacitor is charged through one read and write operation, calculate the amount of electricity based on a function model of the amount of electricity in the capacitor and the charge and discharge time, and compare the calculation with the service threshold.

5. The system according to claim 4, characterized in that The memory simulation module is further configured as follows: The capacitance, charge and discharge time, and temperature are simulated in combination with the capacitance temperature coefficient of the capacitor used in the memory, and a basic model is established based on the simulation results.

6. The system according to claim 4 or 5, characterized in that The abnormal state protection module is further configured as follows: In response to detecting a rapid abnormal temperature drop based on a linear function of temperature change over time, sending an instruction to the BIOS to enable a data encryption function; and / or In response to data access requests being abnormally concentrated in the same area, a memory refresh rate is set to an integer multiple of the current refresh rate until the data access situation returns to normal.

7. A computer-readable storage medium, characterized in that Computer program instructions are stored, and when the computer program instructions are executed, the memory refresh rate management method according to any one of claims 1 to 3 is implemented.

8. A computer device comprising a memory and a processor, characterized in that: The memory stores a computer program, and when the computer program is executed by the processor, the memory refresh rate management method according to any one of claims 1 to 3 is executed.

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