Write Control Method, Storage Device, and Control Circuit Based on Write Behavior Prediction

Abstract

The present invention provides a write control method based on write behavior prediction, a memory storage device, and a memory control circuit unit. The method includes: monitoring a first data write behavior of a host system within a first time range; predicting a second data write behavior of the host system within a second time range according to the first data write behavior; obtaining a first measurement parameter and a first target parameter corresponding to the first data write behavior; determining a write control parameter according to the first measurement parameter, the first target parameter, and the second data write behavior; and sending a write instruction sequence according to the write control parameter to instruct a rewritable non-volatile memory module to perform data writing based on a plurality of write modes within the second time range. Thereby, the stability of the data write speed of the memory storage device can be improved.

Description

Technical Field

[0001] The present invention relates to a memory control technology, and more particularly to a write control method, a memory storage device, and a memory control circuit unit based on write behavior prediction. Background Art

[0002] Some types of memory storage devices support multiple write modes, such as the Single Level Cell (SLC) mode combined with the Triple Level Cell (TLC) mode. In general, the memory storage device can store data in the SLC area based on the SLC mode to reduce the storage capacity of a single storage cell and improve the data storage speed as much as possible. After the SLC area is exhausted, the memory storage device can switch to the TLC mode to store data at a slower speed, but can increase the storage capacity of a single storage cell. Thereby, the memory storage device can adopt different write modes to store data in different scenarios to achieve a balance between data storage speed and memory capacity. However, in practice, the TLC mode often synchronously executes a garbage collection (GC) program, resulting in a further decrease in the data storage speed of the memory storage device in the TLC mode. In addition, frequent switching between write modes also easily causes the data storage speed of the memory storage device to be difficult to maintain stable. Summary of the Invention

[0003] In view of this, the present invention provides a write control method, a memory storage device, and a memory control circuit unit based on write behavior prediction, which can improve the stability of the data write speed of the memory storage device.

[0004] An exemplary embodiment of the present invention provides a write control method based on write behavior prediction, which is used for a rewritable non-volatile memory module. The write control method includes: monitoring a first data write behavior of a host system within a first time range; predicting a second data write behavior of the host system within a second time range according to the first data write behavior, where the second time range is different from the first time range; obtaining a first measurement parameter and a first target parameter corresponding to the first data write behavior; determining a write control parameter according to the first measurement parameter, the first target parameter, and the second data write behavior; and sending a write instruction sequence according to the write control parameter to instruct the rewritable non-volatile memory module to perform data writing based on a plurality of write modes within the second time range, where the amount of written data corresponding to each of the plurality of write modes is controlled by the write control parameter.

[0005] An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used to connect to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to: monitor a first data writing behavior of the host system within a first time range; predict a second data writing behavior of the host system within a second time range according to the first data writing behavior, where the second time range is different from the first time range; obtain a first measurement parameter and a first target parameter corresponding to the first data writing behavior; determine a write control parameter according to the first measurement parameter, the first target parameter, and the second data writing behavior; and send a write instruction sequence according to the write control parameter to instruct the rewritable non-volatile memory module to perform data writing based on a plurality of write modes within the second time range, where the write data amounts respectively corresponding to the plurality of write modes are controlled by the write control parameter.

[0006] An exemplary embodiment of the present invention further provides a memory control circuit unit, which is used to control a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is used to connect to a host system. The memory interface is used to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is configured to: monitor a first data writing behavior of the host system within a first time range; predict a second data writing behavior of the host system within a second time range according to the first data writing behavior, where the second time range is different from the first time range; obtain a first measurement parameter and a first target parameter corresponding to the first data writing behavior; determine a write control parameter according to the first measurement parameter, the first target parameter, and the second data writing behavior; and send a write instruction sequence according to the write control parameter to instruct the rewritable non-volatile memory module to perform data writing based on a plurality of write modes within the second time range, where the write data amounts respectively corresponding to the plurality of write modes are controlled by the write control parameter.

[0007] Based on the above, after monitoring the first data writing behavior of the host system within the first time range, the second data writing behavior of the host system within the second time range can be predicted according to the first data writing behavior. In addition, after obtaining the first measurement parameter and the first target parameter corresponding to the first data writing behavior, according to the first measurement parameter, the first target parameter, and the second data writing behavior, a write control parameter can be determined and a write instruction sequence can be sent according to the write control parameter to instruct the rewritable non-volatile memory module to perform data writing based on multiple writing modes within the second time range. In particular, the amount of written data corresponding to each of the multiple writing modes is controlled by the write control parameter. Thereby, the stability of the data writing speed of the memory storage device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown according to an exemplary embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device shown according to an exemplary embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a host system and a memory storage device shown according to an exemplary embodiment of the present invention;

[0011] Figure 4 is a schematic diagram of a memory storage device shown according to an exemplary embodiment of the present invention;

[0012] Figure 5 is a schematic diagram of a memory control circuit unit shown according to an exemplary embodiment of the present invention;

[0013] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module shown according to an exemplary embodiment of the present invention;

[0014] Figure 7 is a schematic diagram of a first time range and a second time range and corresponding first data writing behavior and second data writing behavior shown according to an exemplary embodiment of the present invention;

[0015] Figure 8 is a flowchart of a write control method based on write behavior prediction shown according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used in the drawings and the description to refer to the same or like parts.

[0017] Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device can be used with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0018] Figure 1 FIG. is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 FIG. is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0019] Please refer to Figure 1 and Figure 2 , the host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be connected to a system bus 110.

[0020] In an exemplary embodiment, the host system 11 may be connected to the memory storage device 10 through the data transfer interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transfer interface 114. In addition, the host system 11 may be connected to the I / O device 12 through the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0021] In an exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be disposed on a motherboard 20 of the host system 11. The number of the data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be connected to the memory storage device 10 in a wired or wireless manner.

[0022] In an exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a low energy Bluetooth memory storage device (e.g., iBeacon), etc., which are memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be connected to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0023] In an exemplary embodiment, the host system 11 is a computer system. In an exemplary embodiment, the host system 11 may be any system that can substantially cooperate with the memory storage device to store data. In an exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include Figure 3 the memory storage device 30 and the host system 31.

[0024] Figure 3 is a schematic diagram of a host system and a memory storage device shown in an exemplary embodiment of the present invention. Please refer to Figure 3 , the memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 may be various non-volatile memory storage devices such as a secure digital (SD) card 32, a compact flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices such as an embedded multi media card (eMMC) 341 and / or an embedded multi chip package (eMCP) storage device 342, etc., which directly connect the memory module to the substrate of the host system.

[0025] Figure 4 is a schematic diagram of a memory storage device shown in an exemplary embodiment of the present invention. Please refer toFigure 4 , the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0026] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 can also be compliant with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be encapsulated in a single chip with the memory control circuit unit 42, or the connection interface unit 41 is disposed outside a chip containing the memory control circuit unit 42.

[0027] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware form and perform operations such as data writing, reading, and erasing in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0028] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a SLC NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a TLC NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0029] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data into the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby obtaining the one or more bits stored in this memory cell.

[0030] In an exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can form multiple physical programming units, and these physical programming units can form multiple physical erasure units. Specifically, the memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be at least classified into lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in an MLC NAND flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0031] In an exemplary embodiment, the physical programming unit is the smallest unit for programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units can include a data bit area and a redundancy bit area. The data bit area contains a plurality of physical sectors for storing user data, and the redundancy bit area is used for storing system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or a greater or smaller number of physical sectors, and the size of each physical sector can also be larger or smaller. On the other hand, the physical erasure unit is the smallest unit for erasure. That is, each physical erasure unit contains the smallest number of storage units to be erased together. For example, the physical erasure unit is a physical block.

[0032] Figure 5 is a schematic diagram of a memory control circuit unit shown according to an exemplary embodiment of the present invention. Please refer to Figure 5 , the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0033] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions are executed to perform operations such as data writing, reading, and erasing. When explaining the operation of the memory management circuit 51 below, it is equivalent to explaining the operation of the memory control circuit unit 42.

[0034] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into this read-only memory. When the memory storage device 10 operates, these control instructions are executed by the microprocessor unit to perform operations such as data writing, reading, and erasing.

[0035] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of the rewritable non-volatile memory module 43 in the form of program code (for example, the system area dedicated to storing system data in the memory module). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. After that, the microprocessor unit runs these control instructions to perform operations such as writing, reading, and erasing data.

[0036] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are connected to the microcontroller. The storage unit management circuit is used to manage the storage units or groups of storage units of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process the data to be written into the rewritable non-volatile memory module 43 and the data read from the rewritable non-volatile memory module 43. The write instruction sequence, the read instruction sequence, and the erase instruction sequence can each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 can also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct the execution of corresponding operations.

[0037] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 is used to receive and identify the instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it must be understood that the present invention is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.

[0038] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, the data to be written to the rewritable non-volatile memory module 43 will be converted into a format acceptable to the rewritable non-volatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences can include a write instruction sequence for indicating writing data, a read instruction sequence for indicating reading data, an erase instruction sequence for indicating erasing data, and corresponding instruction sequences for indicating various memory operations (such as changing the read voltage level or performing a garbage collection operation, etc.). These instruction sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences can include one or more signals, or data on the bus. These signals or data can include instruction codes or program codes. For example, in the read instruction sequence, information such as the identification code for reading and the memory address will be included.

[0039] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correcting circuit 54, a buffer memory 55, and a power management circuit 56.

[0040] The error checking and correcting circuit (also referred to as the decoding circuit) 54 is connected to the memory management circuit 51 and is used to perform error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 51 receives a write instruction from the host system 11, the error checking and correcting circuit 54 generates corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to this write instruction, and the memory management circuit 51 writes the data corresponding to this write instruction and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. After that, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, it reads the corresponding error correcting code and / or error detecting code of this data at the same time, and the error checking and correcting circuit 54 performs error checking and correcting operations on the read data according to this error correcting code and / or error detecting code.

[0041] The buffer memory 55 is connected to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0042] In an exemplary embodiment, Figure 4 the rewritable non-volatile memory module 43 may include a flash memory module. In an exemplary embodiment, Figure 4 the memory control circuit unit 42 may include a flash memory controller. In an exemplary embodiment, Figure 5 the memory management circuit 51 may include a flash memory management circuit.

[0043] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Please refer to Figure 6 , the memory management circuit 51 may logically group the physical units 610(0) to 610(B) in the rewritable non-volatile memory module 43 into a storage area 601 and a spare area 602.

[0044] In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of multiple consecutive or non-consecutive physical addresses. In an exemplary embodiment, a physical unit may also refer to a virtual block (VB). A virtual block may include multiple physical addresses or multiple physical programming units.

[0045] The physical units 610(0) to 610(A) in the storage area 601 are used to store user data (such as fromFigure 1 user data of the host system 11). For example, the physical units 610(0) to 610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A + 1) to 610(B) in the idle area 602 do not store data (such as valid data). For example, if a certain physical unit does not store valid data, this physical unit can be associated (or added) to the idle area 602. In addition, the physical units in the idle area 602 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the idle area 602 to store this new data. In an exemplary embodiment, the idle area 602 is also referred to as a free pool.

[0046] The memory management circuit 51 can configure the logic units 612(0) to 612(C) to map the physical units 610(0) to 610(A) in the storage area 601. In an exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address can include one or more logical block addresses (LBAs) or other logical management units. In an exemplary embodiment, a logic unit can also correspond to a logical programming unit or be composed of multiple consecutive or non-consecutive logical addresses.

[0047] It should be noted that a logic unit can be mapped to one or more physical units. If a certain physical unit is currently mapped by a certain logic unit, it means that the data stored in this physical unit currently includes valid data. On the contrary, if a certain physical unit is not currently mapped by any logic unit, it means that the data stored in this physical unit currently is invalid data.

[0048] The memory management circuit 51 can record the management data (also referred to as logical-to-physical mapping information) describing the mapping relationship between the logic units and the physical units in at least one logical-to-physical mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information in this logical-to-physical mapping table.

[0049] The rewritable non-volatile memory module 43 can program the storage units to store data based on multiple write modes (also referred to as programming modes). In the following exemplary embodiments, it is taken as an example that the multiple write modes include a first write mode and a second write mode, but the present invention is not limited thereto. In other exemplary embodiments, the rewritable non-volatile memory module 43 can also store data based on more write modes (such as a third write mode), and the present invention does not limit it.

[0050] In an exemplary embodiment, a memory cell programmed based on a first write mode in the rewritable non-volatile memory module 43 can be used to store p bits. A memory cell programmed based on a second write mode in the rewritable non-volatile memory module 43 can be used to store p bits. Both p and q are positive integers, and p is different from q.

[0051] In an exemplary embodiment, the first write mode can include the SLC mode or the pseudo SLC mode, and the second write mode can include the TLC mode. Therefore, p can be 1, and q can be 3, but the present invention is not limited thereto. In an exemplary embodiment, the first write mode and the second write mode can respectively include other programming modes, and p and / or q can be other positive integers as long as p is less than q (or p is different from q).

[0052] The memory management circuit 51 can monitor the data writing behavior (also referred to as the first data writing behavior) of the host system 11 within a time range (also referred to as the first time range). For example, the first data writing behavior can be used to write data (also referred to as the first data) from the host system 11 into the rewritable non-volatile memory module 43 within the first time range.

[0053] According to the first data writing behavior, the memory management circuit 51 can predict the data writing behavior (also referred to as the second data writing behavior) of the host system 11 within another time range (also referred to as the second time range). For example, the second data writing behavior can be used to write data (also referred to as the second data) from the host system 11 into the rewritable non-volatile memory module 43 within the second time range. The second time range can be different from the first time range. For example, the second time range can follow the first time range.

[0054] On the other hand, the memory management circuit 51 can obtain a measurement parameter (also referred to as the first measurement parameter) and a target parameter (also referred to as the first target parameter) corresponding to the first data writing behavior. The first measurement parameter can be obtained by real-time monitoring of the first data writing behavior. For example, the first measurement parameter can reflect the actual writing speed of the measured first data.

[0055] In an exemplary embodiment, the memory management circuit 51 can obtain the target parameter (i.e., the first target parameter) corresponding to the first data writing behavior according to the type of the first data writing behavior (such as sequential writing and / or random writing) and the write mode adopted (such as the first write mode and / or the second write mode). For example, the first target parameter can reflect the preset writing speed (also referred to as the target writing speed) corresponding to the first data writing behavior.

[0056] In an exemplary embodiment, a management table may be pre-stored in the rewritable non-volatile memory module 43 (e.g., stored in the system area of the rewritable non-volatile memory module 43). The management table may record target parameters corresponding to different data writing behaviors. Therefore, according to the first data writing behavior, the memory management circuit 51 may obtain the corresponding target parameter from this management table as the first target parameter. For example, assuming that the type of the first data writing behavior is sequential writing and the writing mode adopted by the first data writing behavior is the first writing mode (e.g., SLC mode), the memory management circuit 51 may query the management table according to this information to obtain the first target parameter. In an exemplary embodiment, the memory management circuit 51 may also update (e.g., adjust) the information in the management table (e.g., the first target parameter corresponding to the first data writing behavior) according to the first measurement parameter to continuously optimize the management table.

[0057] The memory management circuit 51 may determine at least one write control parameter according to the first measurement parameter, the first target parameter, and the second data writing behavior. Then, the memory management circuit 51 may send at least one write instruction sequence to the rewritable non-volatile memory module 43 according to the write control parameter to instruct the rewritable non-volatile memory module 43 to perform data writing based on multiple writing modes within the second time range. In particular, the amount of written data corresponding to each of the multiple writing modes may be controlled by the write control parameter.

[0058] Figure 7 is a schematic diagram of the first time range and the second time range and the corresponding first data writing behavior and second data writing behavior shown in the exemplary embodiment of the present invention. Please refer to Figure 7 , assuming that the first time range is between time points T(0) and T(1), and the second time range is between time points T(1) and T(2). The second time range is sorted after the first time range on the time axis (i.e., Figure 7 the horizontal axis), and the first time range and the second time range do not overlap with each other. The time length ΔT(1) covered by the first time range may be the same as or different from the time length ΔT(2) covered by the second time range. In addition, in an exemplary embodiment, there may also be a little time interval between the first time range and the second time range, which is not limited in the present invention.

[0059] In an exemplary embodiment, the memory management circuit 51 may predict the amount of data to be written by the host system 11 within a second time range (i.e., the amount of data of the second data) according to the first data writing behavior of the host system 11 within a first time range. For example, the memory management circuit 51 may obtain the actual writing speed of the host system 11 within the first time range (i.e., the actual writing speed of the first data) according to the amount of data written corresponding to the first data writing behavior (i.e., the amount of data of the first data) and the time length ΔT(1) covered by the first time range. Then, the memory management circuit 51 may predict the amount of data to be written by the host system 11 within the second time range according to this actual writing speed and the time length ΔT(2) covered by the second time range. For example, the memory management circuit 51 may predict the amount of data to be written by the host system 11 within the second time range according to the following equations (1.1) and (1.2).

[0060] V(1) = S(1) / ΔT(1) (1.1)

[0061] S(2) = V(1)×ΔT(2) (1.2)

[0062] In equations (1.1) and (1.2), V(1) represents the actual writing speed of the host system 11 within the first time range, S(1) represents the amount of data of the first data, and S(2) represents the amount of data of the second data.

[0063] After predicting the amount of data to be written by the host system 11 within the second time range (i.e., the amount of data of the second data), the memory management circuit 51 may control the rewritable non-volatile memory module 43 to store the second data within the second time range through the writing control parameter, so as to attempt to keep the data writing speed of the host system 11 stable within the second time range and / or avoid too large a change in this data writing speed within the second time range.

[0064] In an exemplary embodiment, the writing control parameter may be used to control the amount of data written corresponding to the first writing mode (also referred to as the first amount of written data) and the amount of data written corresponding to the second writing mode (also referred to as the second amount of written data) within the second time range. In particular, the writing control parameter may be used to control the sum of the first amount of written data and the second amount of written data to be not less than (i.e., greater than or equal to) the predicted (total) amount of data to be written by the host system 11 within the second time range. Thereby, it can be ensured that the second data can be successfully and completely stored in the rewritable non-volatile memory module 43 within the second time range.

[0065] In an exemplary embodiment, the memory management circuit 51 may determine the writing control parameter according to the following equation (2.1).

[0066] S(2) = V(M1) × ΔT(1) × x% + V(M2) × ΔT(1) × y% (2.1)

[0067] In Equation (2.1), V(M1) represents the preset writing speed at which the rewritable non-volatile memory module 43 stores data based on the first writing mode, V(M2) represents the preset writing speed at which the rewritable non-volatile memory module 43 stores data based on the second writing mode, and the parameters x and y represent the writing control parameters. According to Equation (2.1), the parameter x can be used to control the amount of data stored based on the first writing mode in the second data, and the parameter y can be used to control the amount of data stored based on the second writing mode in the second data.

[0068] In an exemplary embodiment, the memory management circuit 51 can satisfy the predicted data (i.e., the second data) storage requirements of the host system 11 within the second time range and keep the writing speed of the second data stable by dynamically setting or adjusting the writing control parameters (such as the parameters x and y in Equation (2.1)).

[0069] In an exemplary embodiment, the first measurement parameter includes the actual writing speed of the host system 11 within the first time range, and the first target parameter includes the target writing speed of the host system 11 within the first time range. For example, the actual writing speed of the host system 11 within the first time range can be obtained by real-time monitoring of the first data writing behavior. In addition, the target writing speed of the host system 11 within the first time range can include the preset writing speed (i.e., the target writing speed) corresponding to the first data writing behavior.

[0070] In an exemplary embodiment, the memory management circuit 51 can determine the writing control parameters according to the actual writing speed and the target writing speed. By dynamically setting or adjusting the writing control parameters, the memory management circuit 51 can attempt to control the predicted data writing speed of the host system 11 within the second time range to be between the actual writing speed and the target writing speed.

[0071] In an exemplary embodiment, the memory management circuit 51 can determine the writing control parameters according to the following Equation (3.1).

[0072] V(2) = V(M1) × x% + V(M2) × y% (3.1)

[0073] In Equation (3.1), V(2) represents the estimated write speed of the host system 11 within the second time range. By dynamically setting or adjusting the parameters x and y in Equation (3.1), the memory management circuit 51 can attempt to control the predicted data write speed of the host system 11 within the second time range to be between the actual write speed and the target write speed.

[0074] In an exemplary embodiment, the memory management circuit 51 can also determine an allowable speed (also referred to as a fluctuation allowable speed) according to the actual write speed. The error between the fluctuation allowable speed and the actual write speed is less than a preset ratio. For example, the preset ratio can be expressed as z%, and the value of z can be adjusted according to practical requirements.

[0075] In an exemplary embodiment, the memory management circuit 51 can determine the write control parameter according to the actual write speed and the fluctuation allowable speed. By dynamically setting or adjusting the write control parameter, the memory management circuit 51 can attempt to control the predicted data write speed of the host system 11 within the second time range to be between the actual write speed and the fluctuation allowable speed. Thereby, the effect of keeping the data write speed of the host system 11 stable within the second time range can also be achieved.

[0076] In an exemplary embodiment, when the actual write speed is greater than the target write speed, the memory management circuit 51 can dynamically set or adjust the write control parameter to control the predicted data write speed of the host system 11 within the second time range to be between the actual write speed and a reference threshold (also referred to as a first reference threshold). For example, the first reference threshold is the larger of the target write speed and the fluctuation allowable speed. For example, the memory management circuit 51 can compare the target write speed and the fluctuation allowable speed. If the target write speed is greater than the fluctuation allowable speed, the memory management circuit 51 can set the target write speed as the first reference threshold. Alternatively, if the target write speed is less than the fluctuation allowable speed, the memory management circuit 51 can set the fluctuation allowable speed as the first reference threshold.

[0077] In an exemplary embodiment, when the actual writing speed is less than the target writing speed, the memory management circuit 51 can dynamically set or adjust the writing control parameters to control the predicted data writing speed of the host system 11 within a second time range to be between the actual writing speed and another reference threshold value (also referred to as the second reference threshold value). For example, the second reference threshold value is the smaller of the target writing speed and the allowable fluctuation speed. For example, the memory management circuit 51 can compare the target writing speed with the allowable fluctuation speed. If the target writing speed is greater than the allowable fluctuation speed, the memory management circuit 51 can set the allowable fluctuation speed as the second reference threshold value. Alternatively, if the target writing speed is less than the allowable fluctuation speed, the memory management circuit 51 can set the target writing speed as the second reference threshold value.

[0078] In an exemplary embodiment, during the process of determining the writing control parameters (such as parameters x, y) according to Equation (2.1) and / or (3.1), the memory management circuit 51 selects the solution set containing the largest parameter y from the solution sets of multiple (x, y) as the optimal solution set. Thereby, in the second data writing operation, the memory management circuit 51 can maximize the data volume of the data stored based on the second writing mode (such as the TLC mode) and / or reduce the data volume of the data stored based on the first writing mode (such as the SLC mode) as much as possible, so as to reduce the consumption speed of the physical units programmed based on the first writing mode (such as the SLC mode) in the rewritable non-volatile memory module 43.

[0079] It should be noted that in the foregoing exemplary embodiments, it is exemplified that the second data writing behavior includes data storage based on multiple writing modes. However, in another exemplary embodiment, the second data writing behavior within the second time range can also be based on only one of the first writing mode and the second writing mode for data storage, and the present invention is not limited thereto. For example, in an exemplary embodiment, if the parameter y in Equation (2.1) and / or (3.1) is set to zero, it means that data is stored only through the first writing mode within the second time range (i.e., the second writing mode is not enabled). Alternatively, in an exemplary embodiment, if the parameter x in Equation (2.1) and / or (3.1) is set to zero, it means that data is stored only through the second writing mode within the second time range (i.e., the first writing mode is not enabled).

[0080] In an exemplary embodiment, the memory management circuit 51 may monitor in real time the available capacity in the rewritable non-volatile memory module 43 corresponding to the first write mode (e.g., SLC mode). The memory management circuit 51 may determine whether to enable the second write mode within a second time range according to the available capacity. For example, the memory management circuit 51 may determine whether the available capacity in the rewritable non-volatile memory module 43 corresponding to the first write mode (e.g., SLC mode) is less than a preset value. If the available capacity is less than the preset value, the memory management circuit 51 may determine to enable the second write mode within the second time range (i.e., set the parameter y in Equation (2.1) and / or (3.1) to a value greater than zero). Alternatively, if the available capacity is not less than the preset value, the memory management circuit 51 may determine not to enable the second write mode within the second time range (i.e., set the parameter y in Equation (2.1) and / or (3.1) to zero).

[0081] In an exemplary embodiment, in response to the available capacity being less than the preset value, the memory management circuit 51 may further execute a garbage collection (GC) program within the second time range. In the GC program, valid data may be copied from a source unit (i.e., a physical unit storing valid data) to a target unit, thereby increasing the available capacity corresponding to the first write mode.

[0082] In an exemplary embodiment, the memory management circuit 51 may determine whether to enable the second write mode within the second time range according to the predicted amount of write data of the host system 11 within the second time range (i.e., the amount of data of the second data) and the available capacity in the rewritable non-volatile memory module 43 corresponding to the first write mode (e.g., SLC mode). For example, if the predicted amount of write data of the host system 11 within the second time range is greater than the available capacity, the memory management circuit 51 may determine to enable the second write mode within the second time range (i.e., set the parameter y in Equation (2.1) and / or (3.1) to a value greater than zero). Alternatively, if the predicted amount of write data of the host system 11 within the second time range is not greater than the available capacity, the memory management circuit 51 may determine not to enable the second write mode within the second time range (i.e., set the parameter y in Equation (2.1) and / or (3.1) to zero). In addition, the memory management circuit 51 may also be combined with other management rules to determine whether to enable the second write mode within the second time range, which is not limited in the present invention.

[0083] Figure 8 is a flowchart of a write control method based on write behavior prediction shown in an exemplary embodiment of the present invention. Please refer to Figure 8, in step S801, the monitoring host system monitors the first data writing behavior within the first time range. In step S802, based on the first data writing behavior, the second data writing behavior of the host system within the second time range is predicted, where the second time range is different from the first time range. In step S803, the first measurement parameter and the first target parameter corresponding to the first data writing behavior are obtained. In step S804, based on the first measurement parameter, the first target parameter, and the second data writing behavior, the write control parameter is determined. In step S805, a write instruction sequence is sent according to the write control parameter to instruct the rewritable non-volatile memory module to perform data writing based on multiple writing modes within the second time range, where the amount of written data corresponding to each of the multiple writing modes is controlled by the write control parameter.

[0084] However, Figure 8 The steps in [it] have been described in detail above and will not be elaborated here. It should be noted that, Figure 8 The steps in [it] can be implemented as multiple pieces of program code or circuits, and the present invention does not limit this. In addition, Figure 8 The method of [it] can be used in combination with the above exemplary embodiments or used alone, and the present invention does not limit this.

[0085] In summary, the exemplary embodiments proposed by the present invention can predict the second data writing behavior of the host system within the second time range based on the first data writing behavior of the host system within the first time range and determine the write control parameter according to the prediction result. In particular, the write control parameter can be used to control the amount of written data corresponding to each of the multiple writing modes within the second time range. Thereby, the stability of the data writing speed of the memory storage device can be effectively improved.

[0086] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A write control method based on write behavior prediction, characterized in that For a rewritable non-volatile memory module, the write control method includes: Monitoring the first data writing behavior of the host system within a first time range; Predicting the second data writing behavior of the host system within a second time range according to the first data writing behavior, where the second time range is different from the first time range; Obtaining a first measurement parameter and a first target parameter corresponding to the first data writing behavior; Determining write control parameters according to the first measurement parameter, the first target parameter and the second data writing behavior, where the write control parameters include a first write parameter and a second write parameter; and Sending a write instruction sequence to the rewritable non-volatile memory module according to the write control parameters, where the write instruction sequence is used to instruct the rewritable non-volatile memory module to store a first part of the write data in the rewritable non-volatile memory module based on a first write mode, and store a second part of the write data in the rewritable non-volatile memory module based on a second write mode, the data amount of the first part of the write data is controlled by the first write parameter, and the data amount of the second part of the write data is controlled by the second write parameter, a storage unit programmed based on the first write mode in the rewritable non-volatile memory module is used to store p bits, and a storage unit programmed based on the second write mode in the rewritable non-volatile memory module is used to store q bits, both p and q are positive integers, and p is different from q.

2. The write control method according to claim 1, wherein the step of predicting the second data writing behavior of the host system within the second time range according to the first data writing behavior includes: Predicting the write data amount of the host system within the second time range according to the first data writing behavior.

3. The write control method according to claim 1, wherein the write control parameters are used to control a first write data amount corresponding to the first write mode and a second write data amount corresponding to the second write mode within the second time range, and the sum of the first write data amount and the second write data amount is not less than the predicted write data amount of the host system within the second time range.

4. The write control method according to claim 1, wherein the first measurement parameter includes the actual write speed of the host system within the first time range, the first target parameter includes the target write speed of the host system within the first time range, and the step of determining the write control parameters according to the first measurement parameter, the first target parameter and the second data writing behavior includes: Determining the write control parameters according to the actual write speed and the target write speed to control the predicted data write speed of the host system within the second time range to be between the actual write speed and the target write speed.

5. The write control method according to claim 4, wherein the step of determining the write control parameter according to the actual write speed and the target write speed further includes: Determining a fluctuation allowable speed according to the actual write speed, wherein an error between the fluctuation allowable speed and the actual write speed is less than a preset ratio; And Determining the write control parameter according to the actual write speed and the fluctuation allowable speed to control the predicted data write speed of the host system within the second time range to be between the actual write speed and the fluctuation allowable speed.

6. The write control method according to claim 1, wherein the step of predicting the second data write behavior of the host system within the second time range according to the first data write behavior includes: Determining whether to enable the second write mode within the second time range according to the available capacity corresponding to the first write mode in the rewritable non-volatile memory module.

7. A memory storage device, characterized in that, Including: A connection interface unit for connecting to a host system; A rewritable non-volatile memory module; And A memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is configured to: Monitor a first data write behavior of the host system within a first time range; Predict a second data write behavior of the host system within a second time range according to the first data write behavior, wherein the second time range is different from the first time range; Obtain a first measurement parameter and a first target parameter corresponding to the first data write behavior; Determine a write control parameter according to the first measurement parameter, the first target parameter and the second data write behavior, wherein the write control parameter includes a first write parameter and a second write parameter; And Sending a write instruction sequence to the rewritable non-volatile memory module according to the write control parameter, wherein the write instruction sequence is used to instruct the rewritable non-volatile memory module to store a first part of write data in the rewritable non-volatile memory module based on a first write mode, and store a second part of the write data in the rewritable non-volatile memory module based on a second write mode, The data volume of the first part of the write data is controlled by the first write parameter, and the data volume of the second part of the write data is controlled by the second write parameter, One storage unit programmed based on the first write mode in the rewritable non-volatile memory module is used to store p bits, and one storage unit programmed based on the second write mode in the rewritable non-volatile memory module is used to store q bits, where p and q are both positive integers and p is different from q.

8. The memory storage device according to claim 7, wherein the operation of the memory control circuit unit for predicting the second data writing behavior of the host system within the second time range according to the first data writing behavior includes: Predicting the amount of data to be written by the host system within the second time range according to the first data writing behavior.

9. The memory storage device according to claim 7, wherein the write control parameter is used to control the first amount of data written corresponding to the first write mode and the second amount of data written corresponding to the second write mode within the second time range, and The sum of the first amount of data written and the second amount of data written is not less than the predicted amount of data to be written by the host system within the second time range.

10. The memory storage device according to claim 7, wherein the first measurement parameter includes the actual writing speed of the host system within the first time range, the first target parameter includes the target writing speed of the host system within the first time range, and the operation of the memory control circuit unit for determining the write control parameter according to the first measurement parameter, the first target parameter and the second data writing behavior includes: Determining the write control parameter according to the actual writing speed and the target writing speed, so as to control the predicted data writing speed of the host system within the second time range to be between the actual writing speed and the target writing speed.

11. The memory storage device according to claim 10, wherein the operation of the memory control circuit unit for determining the write control parameter according to the actual writing speed and the target writing speed further includes: Determining a fluctuation allowable speed according to the actual writing speed, wherein the error between the fluctuation allowable speed and the actual writing speed is less than a preset ratio; And Determining the write control parameter according to the actual writing speed and the fluctuation allowable speed, so as to control the predicted data writing speed of the host system within the second time range to be between the actual writing speed and the fluctuation allowable speed.

12. The memory storage device according to claim 7, wherein the operation of the memory control circuit unit for predicting the second data writing behavior of the host system within the second time range according to the first data writing behavior includes: Determining whether to enable the second write mode within the second time range according to the available capacity corresponding to the first write mode in the rewritable non-volatile memory module.

13. A memory control circuit unit, characterized in that, For controlling a rewritable non-volatile memory module, the memory control circuit unit includes: A host interface for connecting to a host system; A memory interface for connecting to a rewritable non-volatile memory module; and A memory management circuit connected to the host interface and the memory interface, wherein the memory management circuit is configured to: Monitor the first data writing behavior of the host system within the first time range; Predict a second data writing behavior of the host system within a second time range according to the first data writing behavior, where the second time range is different from the first time range; Obtain a first measurement parameter and a first target parameter corresponding to the first data writing behavior; Determine a write control parameter according to the first measurement parameter, the first target parameter, and the second data writing behavior, where the write control parameter includes a first write parameter and a second write parameter; and Send a write instruction sequence to the rewritable non-volatile memory module according to the write control parameter, where the write instruction sequence is used to instruct the rewritable non-volatile memory module to store a first part of the write data in the rewritable non-volatile memory module based on a first write mode, and store a second part of the write data in the rewritable non-volatile memory module based on a second write mode, the data volume of the first part of the write data is controlled by the first write parameter, and the data volume of the second part of the write data is controlled by the second write parameter, a storage unit programmed based on the first write mode in the rewritable non-volatile memory module is used to store p bits, a storage unit programmed based on the second write mode in the rewritable non-volatile memory module is used to store q bits, both p and q are positive integers, and p is different from q.

14. The memory control circuit unit according to claim 13, wherein the operation of the memory management circuit predicting the second data writing behavior of the host system within the second time range according to the first data writing behavior includes: Predict the amount of write data of the host system within the second time range according to the first data writing behavior.

15. The memory control circuit unit according to claim 13, wherein the write control parameter is used to control a first write data volume corresponding to the first write mode and a second write data volume corresponding to the second write mode within the second time range, and the sum of the first write data volume and the second write data volume is not less than the predicted amount of write data of the host system within the second time range.

16. The memory control circuit unit according to claim 13, wherein the first measurement parameter includes the actual write speed of the host system within the first time range, the first target parameter includes the target write speed of the host system within the first time range, and the operation of the memory management circuit determining the write control parameter according to the first measurement parameter, the first target parameter, and the second data writing behavior includes: Determine the write control parameter according to the actual write speed and the target write speed to control the predicted data write speed of the host system within the second time range to be between the actual write speed and the target write speed.

17. The memory control circuit unit according to claim 16, wherein the operation of the memory management circuit to determine the write control parameter according to the actual write speed and the target write speed further includes: Determining a fluctuation allowable speed according to the actual write speed, wherein an error between the fluctuation allowable speed and the actual write speed is less than a preset ratio; And Determining the write control parameter according to the actual write speed and the fluctuation allowable speed, so as to control the predicted data write speed of the host system within the second time range to be between the actual write speed and the fluctuation allowable speed.

18. The memory control circuit unit according to claim 13, wherein the operation of the memory management circuit to predict the second data write behavior of the host system within the second time range according to the first data write behavior includes: Determining whether to enable the second write mode within the second time range according to the available capacity corresponding to the first write mode in the rewritable non-volatile memory module.

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