Semiconductor device structure and method of fabricating the same

Abstract

The application relates to a semiconductor device structure and a preparation method thereof, which comprises a field plate and a plurality of resistors, the resistors have different resistance values, one end of each resistor is electrically connected to different positions on the surface of the field plate, and the other end is connected to a source voltage. Since the electric potential at the connection point of each resistor and the field plate is different due to the different resistance values of the resistors, the electric potential of each part of the field plate can be accurately adjusted by adjusting the resistance values of the resistors.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device structure and a preparation method thereof. BACKGROUND

[0002] In a semiconductor device, the greater the electric field intensity under the field oxide layer, the more easily the semiconductor device is broken down, and therefore, it is necessary to adjust the field intensity distribution under the field oxide layer to improve the breakdown voltage of the semiconductor device. In the conventional technology, the way of forming a resistive field plate on the surface of the field oxide layer is usually adopted to adjust the field intensity distribution under the field oxide layer in the semiconductor device, and the potential difference of each part under the field plate is adjusted by applying different voltages to the head and tail of the resistive field plate, so as to adjust the field intensity distribution under the field oxide layer. However, the voltage adjustment range of the resistive field plate is limited, and the potential difference decreases uniformly on the whole field plate, and there is a problem that the potential of each part of the field plate cannot be accurately adjusted. SUMMARY

[0003] Therefore, it is necessary to provide a semiconductor device structure and a preparation method thereof which can accurately adjust the potential of each part of the field plate.

[0004] The present application designs a semiconductor device structure, which comprises:

[0005] a field plate;

[0006] a plurality of resistors, the resistances of the plurality of resistors are not the same; one end of each of the resistors is electrically connected to different positions on the surface of the field plate, and the other end is connected to a source voltage.

[0007] In one of the embodiments, the semiconductor device structure further comprises a plurality of first interconnection structures which are arranged at intervals, one end of each of the plurality of first interconnection structures is connected to one of the resistors in one-to-one correspondence, and the other end is located at different positions on the surface of the field plate.

[0008] In one of the embodiments, the semiconductor device structure further comprises a plurality of metal interconnection layers; the metal interconnection layers are located between the first interconnection structures and the resistors and are connected to the first interconnection structures and the resistors in one-to-one correspondence.

[0009] In one of the embodiments, the plurality of first interconnection structures are arranged at equal intervals.

[0010] In one of the embodiments, the semiconductor device structure further comprises:

[0011] a substrate, the substrate is formed with a source region and a drain region which are adjacent to each other;

[0012] a field oxide layer, which is located on the surface of the substrate and extends from the surface of the source region to the surface of the drain region.

[0013] The field plate extends from the surface of the source region to the surface of the field oxide layer away from the substrate.

[0014] In one embodiment, the semiconductor device structure further includes a second interconnect structure located on the side of the plurality of first interconnect structures away from the source region, with one end in contact with the field plate and the other end connected to the input voltage.

[0015] The present invention also provides a method for fabricating a semiconductor device structure, the method comprising:

[0016] Forming a field plate;

[0017] Multiple resistors are formed outside the field plate, and the resistance values ​​of the multiple resistors are not exactly the same; one end of each resistor is electrically connected to a different position on the surface of the field plate, and the other end of each resistor is connected to the source voltage.

[0018] In one embodiment, after forming the field plate and before forming the resistor, the method further includes:

[0019] Multiple first interconnect structures are formed on the surface of the field plate with first intervals. One end of each first interconnect structure is connected to a resistor in a one-to-one correspondence, and the other end is located at different positions on the surface of the field plate.

[0020] In one embodiment, after forming the first interconnect structure and before forming the resistor, the method further includes:

[0021] Multiple metal interconnect layers are formed between the first interconnect structure and the resistor; each metal interconnect layer is connected to the first interconnect structure and the resistor in a one-to-one correspondence.

[0022] In one embodiment, prior to forming the field plate, the method further includes:

[0023] Provide substrate;

[0024] A source region and a drain region are formed within the substrate, wherein the source region and the drain region are adjacent to each other;

[0025] The field oxide layer is formed on the surface of the substrate and extends from the surface of the source region to the surface of the drain region.

[0026] In one embodiment, while forming a plurality of first interconnect structures arranged at first intervals on the surface of the field plate, a second interconnect structure is also formed on the surface of the field plate. The second interconnect structure is located on the side of the plurality of first interconnect structures away from the source region, with one end in contact with the field plate and the other end connected to the input voltage.

[0027] The above-mentioned semiconductor device structure and its fabrication method include a field plate and multiple resistors. The resistance values ​​of the multiple resistors are not the same. One end of each resistor is electrically connected to a different position on the surface of the field plate, and the other end is connected to the source voltage. Since the potential at the connection point between each resistor and the field plate is different due to the different resistance values ​​of each resistor, the potential of each part of the field plate can be accurately adjusted by adjusting the resistance values ​​of each resistor. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of a semiconductor device structure in one embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of the structure of an N-type high-voltage MOSFET with a field plate added in one embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of the electric field distribution of the N-type high-voltage MOS transistor before and after the addition of the field plate in one embodiment of the present invention;

[0032] Figure 4 This is a schematic diagram of a semiconductor device structure in another embodiment of the present invention;

[0033] Figure 5 This is a flowchart of a method for fabricating a semiconductor device structure according to one embodiment of the present invention;

[0034] Figure 6 This is a flowchart of a method for fabricating a semiconductor device structure provided in another embodiment of the present invention.

[0035] Explanation of reference numerals in the attached figures: 10-field plate, 20-resistor, 30-first interconnect structure, 40-metal interconnect layer, 50-substrate, 501-source region, 502-drain region, 60-field oxide layer, 70-second interconnect structure. Detailed Implementation

[0036] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0039] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0040] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0042] This invention provides a semiconductor device structure, such as Figure 1 As shown, the semiconductor device structure includes: a field plate 10; multiple resistors 20, the resistance values ​​of which are not exactly the same; one end of each resistor 20 is electrically connected to a different position on the surface of the field plate 10, and the other end of each resistor is connected to the source voltage.

[0043] The semiconductor device may include bipolar transistors, field-effect transistors, etc., and this embodiment is not limited thereto. The field plate 10 may include a metal field plate, a polycrystalline silicon field plate, etc., and this embodiment is not limited thereto. The field plate 10 can prevent excessive electric field concentration by changing the potential distribution in the semiconductor device, thereby improving the breakdown voltage of the semiconductor device. For example, taking an N-type high-voltage metal-oxide-semiconductor field-effect transistor (MOSFET, also known as MOS) as an example... Figure 2 and Figure 3 As shown, Figure 2 For the drain region 502 (N) of the N-type high-voltage MOSFET after adding field plate 10 - ) to source area 501 (P + ) structural diagram, Figure 2 The area enclosed by the dashed line represents the built-in electric field formed during P / N region contact. Figure 3 The electric field distribution diagram of the N-type high-voltage MOSFET in the off state before and after the addition of field plate 10 is shown below. Figure 3 As shown, when the field plate 10 is not applied, the electric field distribution of the built-in electric field of the N-type high-voltage MOSFET is a single-peak distribution, with the peak electric field at point A. At this point, voltage breakdown is likely to occur. When the field plate 10 is applied... Figure 3 Behind the L1 field plate shown, the built-in electric field extends to... Figure 3Extending to the right and decreasing the peak electric field, the built-in electric field distribution is bimodal, with peak electric fields at points B and B'. The electric field strength at points B and B' is less than that at point A. Therefore, adding field plate 10 increases the breakdown voltage of the N-type high-voltage MOSFET. Furthermore, when adding... Figure 3 Behind the L2 field plate shown, the built-in electric field continues to... Figure 3 Extending to the right, the peak electric field continues to decrease. At this point, the electric field distribution of the built-in electric field is still bimodal, with peak electric fields at points C and C', and the breakdown voltage of the N-type high-voltage MOSFET is further increased. It should be noted that the length of the field plate 10 cannot be extended indefinitely; the length of the field plate 10 can be determined according to the actual application scenario. In addition, the above... Figure 3 The electric field strength at points B' and C' may exceed that at points B and C.

[0044] It should be noted that in traditional technology, the breakdown voltage of a semiconductor device is usually increased by adding a resistive field plate. The resistive field plate adjusts the potential difference of different parts of the field plate 10 by applying different voltages at the beginning and end of the field plate 10, thereby adjusting the electric field distribution of the semiconductor device. However, the voltage adjustment range of the resistive field plate is limited, and the potential difference of different parts of the resistive field plate decreases uniformly on the resistive field plate. In other words, the resistive field plate can only adjust the potential of the field plate 10 as a whole, and cannot accurately adjust the potential of different parts of the field plate 10. This solution involves forming multiple resistors 20 outside the field plate 10, with one end of each resistor 20 electrically connected to a different location on the surface of the field plate 10, and the other end of each resistor 20 connected to the source voltage. Since the potential at the connection point between each resistor 20 and the field plate 10 varies depending on the resistance value of each resistor 20, this solution can accurately adjust the potential of different parts of the field plate 10 by adjusting the resistance value of each resistor 20. Furthermore, by introducing the resistors 20 in this solution, it is possible to achieve... Figure 4 The difference between the peak and valley values ​​of the bimodal electric field formed after the addition of the field plate 10 is reduced, which further weakens the peak electric field and thus increases the breakdown voltage of the semiconductor device.

[0045] In addition, the number of resistors 20, the resistance value of each resistor 20, and the connection position of each resistor 20 to the surface of the field plate 10 can be adjusted according to the actual application scenario. By continuously testing the breakdown voltage of the adjusted semiconductor device structure, the number of resistors 20, the resistance value of each resistor 20, and the connection position of each resistor 20 to the surface of the field plate 10 can be determined.

[0046] Optionally, each resistor 20 can be a fixed resistor. Alternatively, each resistor 20 can be a variable resistor. The resistance value can be changed by applying different bias voltages across each variable resistor, thus allowing adjustment of the resistance value of each resistor 20 without redesigning the layout, shortening the tape-out cycle. Furthermore, since the other end of each resistor 20 is connected to the source voltage, no additional voltage port is needed, saving layout design area.

[0047] In the above-mentioned semiconductor device structure, the semiconductor device structure includes a field plate and multiple resistors. The resistance values ​​of the multiple resistors are not exactly the same. One end of each resistor is electrically connected to a different position on the surface of the field plate, and the other end is connected to the source voltage. Since the potential at the connection point between each resistor and the field plate is different due to the different resistance values ​​of each resistor, the potential of each part of the field plate can be accurately adjusted by adjusting the resistance value of each resistor.

[0048] In one embodiment, such as Figure 4 As shown, the semiconductor device structure also includes a plurality of first interconnect structures 30 arranged at intervals. One end of each of the plurality of first interconnect structures 30 is connected to a resistor 20 in a one-to-one correspondence, and the other end is located at different positions on the surface of the field plate 10.

[0049] Specifically, multiple dielectric layers can be formed on the surface of the field plate 10, and each dielectric layer can be distributed at different positions on the surface of the field plate. Through holes can be formed in the dielectric layers and filled with metal to form a first interconnect structure 30. The first interconnect structure 30 can conduct electricity, so the resistor 20 can adjust the potential at the connection between each first interconnect structure 30 and the field plate 10 by connecting to the first interconnect structure 30.

[0050] In one embodiment, please continue to refer to Figure 4 The semiconductor device structure also includes multiple metal interconnect layers 40; the metal interconnect layers 40 are located between the first interconnect structure 30 and the resistor 20, and are connected to the first interconnect structure 30 and the resistor 20 in a one-to-one correspondence.

[0051] Specifically, the metal interconnect layer 40 is used to connect the first interconnect structure 30 and the resistor 20. The material of the metal interconnect layer 40 may include copper, aluminum, etc., and this embodiment does not limit it.

[0052] In one embodiment, a plurality of first interconnect structures 30 are arranged at equal intervals.

[0053] Specifically, the spacing between each first interconnect structure 30 can be equal, or optionally, the spacing between each first interconnect structure 30 can be unequal, and the spacing between each first interconnect structure 30 can be determined based on the test results of the breakdown voltage.

[0054] In one embodiment, please continue to refer toFigure 4 The semiconductor device structure also includes: a substrate 50, in which adjacent source regions 501 and drain regions 502 are formed; a field oxide layer 60, located on the surface of the substrate 50, and extending from the surface of the source region 501 to the surface of the drain region 502; and a field plate 10 extending from the surface of the source region 501 to the surface of the field oxide layer 60 away from the substrate 50.

[0055] Specifically, such as Figure 4 As shown, the field plate 10 can extend from the surface of the source region 501 to the surface of the field oxide layer 60 away from the substrate 50, so that no additional power supply is needed for the field plate 10, which can effectively reduce the lead wires and save the layout design area. Furthermore, the design of integrating the field plate 10 with the source region 501 can also simplify the fabrication process.

[0056] In one embodiment, please continue to refer to Figures 1 to 4 The semiconductor device structure also includes a second interconnect structure 70, which is located on the side of the plurality of first interconnect structures 30 away from the source region 501. One end of the second interconnect structure 70 is in contact with the field plate 10, and the other end is connected to the input voltage.

[0057] Specifically, the second interconnect structure 70, through its connection with the input voltage, can provide input voltage to the field board 10 and each resistor 20, thereby ensuring the normal operation of the field board 10 and the resistors 20. At the same time, the second interconnect structure 70, being directly connected to the input voltage, eliminates the need to design additional voltage ports, thus saving layout design area.

[0058] In one example, the semiconductor device structure may further include a dielectric layer (not shown), which may be located on the surface of the substrate 50 and cover the field plate 10 and the field oxide layer 60; the first interconnect structure 30 and the second interconnect structure 70 are both located within the dielectric layer.

[0059] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures), thus allowing for the anticipation of variations in the shown shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the invention.

[0060] Please combine Figure 5 See Figures 1 to 4 The present invention also provides a method for fabricating a semiconductor device structure, comprising the following steps:

[0061] S501, forming the field plate 10;

[0062] S502, multiple resistors 20 are formed outside the field plate 10, and the resistance values ​​of the multiple resistors 20 are not the same; one end of each resistor 20 is electrically connected to a different position on the surface of the field plate 10, and the other end is connected to the source voltage.

[0063] The method for fabricating the semiconductor device structure provided in this embodiment can be used to fabricate... Figures 1 to 4 For details on the semiconductor device structure and its technical effects in the embodiments, please refer to [link / reference needed]. Figures 1 to 5 The relevant textual descriptions will not be repeated here.

[0064] In one embodiment, after forming the field plate 10 and before forming the resistor 20, the method further includes:

[0065] Multiple first interconnect structures 30 are formed on the surface of the field plate 10 with a first interval. One end of each first interconnect structure 30 is connected to a resistor 20 in a one-to-one correspondence, and the other end is located at different positions on the surface of the field plate 10.

[0066] In one embodiment, after forming the first interconnect structure 30 and before forming the resistor 20, the method further includes:

[0067] Multiple metal interconnect layers 40 are formed between the first interconnect structure 30 and the resistor 20; the metal interconnect layers 40 are connected to the first interconnect structure 30 and the resistor 20 in a one-to-one correspondence.

[0068] The method for fabricating the semiconductor device structure provided in this embodiment is similar in principle and technical effect to the above-described embodiment of the semiconductor device structure, and will not be repeated here.

[0069] In one embodiment, please combine Figure 6 See Figure 6 Before forming the field plate 10, it also includes:

[0070] Substrate 50 is provided;

[0071] A source region 501 and a drain region 502 are formed in the substrate 50, with the source region 501 and the drain region 502 being adjacent to each other;

[0072] A field oxide layer 60 is formed on the surface of the substrate 50, extending from the surface of the source region 501 to the surface of the drain region 502.

[0073] Optionally, the source region 501 and the drain region 502 can be separated by the field oxide layer 60.

[0074] That is, Figure 5 As shown, the method for fabricating the semiconductor device structure in this embodiment includes the following steps:

[0075] S601, providing substrate 50;

[0076] S602, a source region 501 and a drain region 502 are formed in the substrate 50, with the source region 501 and the drain region 502 being adjacent to each other;

[0077] S603, the field oxide layer 60 is formed on the surface of the substrate 50, extending from the surface of the source region 501 to the surface of the drain region 502;

[0078] S604, forming plate 10;

[0079] S605, multiple resistors 20 are formed outside the field plate 10, and the resistance values ​​of the multiple resistors 20 are not the same; one end of each resistor 20 is electrically connected to a different position on the surface of the field plate 10, and the other end is connected to the source voltage.

[0080] The method for fabricating the semiconductor device structure provided in this embodiment is similar in principle and technical effect to the above-described embodiment of the semiconductor device structure, and will not be repeated here.

[0081] In one embodiment, while a plurality of first interconnect structures 30 arranged at first intervals are formed on the surface of the field plate 10, a second interconnect structure 70 is also formed on the surface of the field plate 10. The second interconnect structure 70 is located on the side of the plurality of first interconnect structures 30 away from the source region 501, with one end in contact with the field plate 10 and the other end connected to the input voltage.

[0082] In one example, after forming the field plate 10 and before forming the first interconnect structure 30, the following may be included:

[0083] A dielectric layer (not shown) is formed on the surface of the substrate 50;

[0084] A first interconnect via and a second interconnect via are formed within the dielectric layer, both of which expose a portion of the field plate 10.

[0085] The first interconnect structure 30 is formed in the first interconnect via, and the second interconnect structure 70 is formed in the second interconnect via. The first interconnect structure 30 and the second interconnect structure 70 can be obtained by forming conductive layers in the first interconnect via and the second interconnect via.

[0086] The method for fabricating the semiconductor device structure provided in this embodiment is similar in principle and technical effect to the above-described embodiment of the semiconductor device structure, and will not be repeated here.

[0087] It should be understood that, although Figure 6 as well as Figure 5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders.Figure 6 and ​ At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0088] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0089] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor device structure, characterized in that, The semiconductor device structure includes: Field board; Multiple resistors, each with a different resistance value; one end of each resistor is electrically connected to a different position on the surface of the field plate, and the other end is connected to a source voltage; the potential at the connection point between each resistor and the field plate varies due to the different resistance values ​​of each resistor. Multiple first interconnect structures are arranged at intervals, with one end of each of the multiple first interconnect structures being connected to the resistor in a one-to-one correspondence, and the other end being located at different positions on the surface of the field plate. A substrate in which adjacent source and drain regions are formed; A field oxide layer is located on the surface of the substrate and extends from the surface of the source region to the surface of the drain region; wherein the field plate extends from the surface of the source region to the surface of the field oxide layer away from the substrate; The second interconnect structure is located on the side of the plurality of first interconnect structures away from the source region, with one end in contact with the field plate and the other end connected to the input voltage.

2. The semiconductor device structure according to claim 1, characterized in that, The semiconductor device structure further includes multiple metal interconnect layers; the metal interconnect layers are located between the first interconnect structure and the resistor, and are connected to the first interconnect structure and the resistor in a one-to-one correspondence.

3. The semiconductor device structure according to claim 1, characterized in that, Multiple first interconnect structures are arranged at equal intervals.

4. A method for fabricating a semiconductor device structure, characterized in that, The method for fabricating the semiconductor device structure includes: Provide substrate; A source region and a drain region are formed within the substrate, wherein the source region and the drain region are adjacent to each other; A field oxide layer is formed on the surface of the substrate, extending from the surface of the source region to the surface of the drain region; Forming a field plate; A plurality of first interconnect structures are formed on the surface of the field plate at first intervals, and a second interconnect structure is formed simultaneously on the surface of the field plate. The second interconnect structure is located on the side of the plurality of first interconnect structures away from the source region, with one end in contact with the field plate and the other end connected to the input voltage. Multiple resistors are formed on the outside of the field plate, and the resistance values ​​of the multiple resistors are not exactly the same; one end of each resistor is electrically connected to a different position on the surface of the field plate, and the other end is connected to the source voltage. The potential at the connection point between each resistor and the field plate is different due to the different resistance values ​​of each resistor; wherein, one end of the first interconnection structure is connected to each of the resistors in a corresponding manner, and the other end is located at a different position on the surface of the field plate.

5. The method for fabricating a semiconductor device structure according to claim 4, characterized in that, After forming the first interconnect structure and before forming the resistor, the method further includes: Multiple metal interconnect layers are formed between the first interconnect structure and the resistor; each metal interconnect layer is connected to the first interconnect structure and the resistor in a one-to-one correspondence.

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