Array substrate, preparation method of array substrate, and electronic paper display device

Abstract

An embodiment of the present application discloses an array substrate, a preparation method of the array substrate, and an electronic paper display device. The array substrate includes a substrate; a pixel structure disposed on the substrate, the pixel structure including a first metal layer, a second metal layer, a third metal layer, and a thin film layer that are sequentially and spaced apart. Among them, the first metal layer and the third metal layer are common electrodes, the second metal layer and the thin film layer are pixel electrodes, the first metal layer and the second metal layer form a first storage capacitor, the second metal layer and the third metal layer form a second storage capacitor, and the third metal layer and the thin film layer form a third storage capacitor. In the array substrate provided by the present application, the pixel structure forms three storage capacitors, increasing the capacitance value of the storage capacitor without changing the pixel structure space and without increasing the stray capacitance, and reducing the influence of pixel structure leakage.

Description

Technical Field

[0001] This application belongs to the field of display technology, and particularly relates to an array substrate, a preparation method of the array substrate, and an electronic paper display device. Background Art

[0002] With the continuous development of technology, the frequency of replacement of electronic digital products is getting higher and higher, and various new products are constantly developed. The electronic paper display device is a new type of display device, mainly used in devices such as electronic tags, billboards, and e-readers. The display effect of the electronic paper display device is close to that of natural paper, which can reduce visual fatigue during reading. Since the pixel structure in the electronic paper display device has a long retention time, a large storage capacitor design is required to reduce the influence of pixel leakage.

[0003] In the related art of electronic paper display devices, due to the small pixel structure, there is limited space to increase the pixel electrode and the common electrode in the pixel structure with high pixel density, and there is also a risk of increasing other stray capacitances. Summary of the Invention

[0004] The embodiments of this application provide an array substrate, a preparation method of the array substrate, and an electronic paper display device, which increase the capacitance value of the storage capacitor and reduce the influence of pixel structure leakage.

[0005] In a first aspect, the embodiments of this application provide an array substrate, including:

[0006] A substrate;

[0007] A pixel structure disposed on the substrate, the pixel structure including a first metal layer, a second metal layer, a third metal layer, and a thin film layer that are sequentially spaced apart, wherein the first metal layer and the third metal layer are common electrodes, the second metal layer and the thin film layer are pixel electrodes, the first metal layer and the second metal layer form a first storage capacitor, the second metal layer and the third metal layer form a second storage capacitor, and the third metal layer and the thin film layer form a third storage capacitor.

[0008] Optionally, in some embodiments, an insulating layer is disposed between the first metal layer and the second metal layer in the pixel structure, a first planarization layer and a passivation layer are disposed between the second metal layer and the third metal layer, the first planarization layer is disposed on the second metal layer, the passivation layer is disposed on the first planarization layer, and a second planarization layer is disposed between the third metal layer and the thin film layer.

[0009] Optionally, in some embodiments, the pixel structure includes a first pixel region and a second pixel region arranged adjacent to each other. The first pixel region includes a first portion of the first metal layer, the second metal layer, a first portion of the third metal layer, and a first portion of the thin film layer. The second pixel region includes a second portion of the first metal layer, a second portion of the third metal layer, and a second portion of the thin film layer. The first portion of the first metal layer and the second metal layer form the first storage capacitor. The second metal layer and the first portion of the third metal layer form the second storage capacitor. The first portion of the third metal layer and the first portion of the thin film layer, and the second portion of the third metal layer and the second portion of the thin film layer form the third storage capacitor.

[0010] Optionally, in some embodiments, a first via hole is provided in the first pixel region. The first via hole sequentially penetrates through the second planarization layer, the third metal layer, the passivation layer, and the first planarization layer and extends to the upper surface of the second metal layer. The first via hole and the second metal layer form a first groove. A portion of the thin film layer covers the bottom and side walls of the first groove, so that the pixel electrode corresponding to the thin film layer contacts the pixel electrode corresponding to the second metal layer.

[0011] Optionally, in some embodiments, a second via hole is provided in the second pixel region. The second via hole sequentially penetrates through the passivation layer, the first planarization layer, and the insulating layer and extends to the upper surface of the first metal layer. The second via hole and the first metal layer form a second groove. A portion of the third metal layer covers the bottom and side walls of the second groove, so that the common electrode corresponding to the third metal layer contacts the common electrode corresponding to the first metal layer.

[0012] Optionally, in some embodiments, the first portion of the first metal layer in the first pixel region and the second portion of the first metal layer in the second pixel region are made by the same process. The first portion of the third metal layer in the first pixel region and the second portion of the third metal layer in the second pixel region are made by the same process. The first portion of the thin film layer in the first pixel region and the second portion of the thin film layer in the second pixel region are made by the same process.

[0013] In a second aspect, an embodiment of the present application further provides a method for manufacturing an array substrate, including:

[0014] Providing a substrate;

[0015] Forming a first metal layer on the substrate, and forming an insulating layer on the first metal layer;

[0016] A second metal layer is formed on the insulating layer, and a first planarization layer is formed on the second metal layer;

[0017] A passivation layer is formed on the first planarization layer, and a third metal layer is formed on the passivation layer;

[0018] A second planarization layer is formed on the third metal layer, and a thin film layer is formed on the second planarization layer; wherein,

[0019] The first metal layer and the third metal layer are common electrodes, the second metal layer and the thin film layer are pixel electrodes, the first metal layer and the second metal layer form a first storage capacitor, the second metal layer and the third metal layer form a second storage capacitor, and the third metal layer and the thin film layer form a third storage capacitor.

[0020] Optionally, in some embodiments, the array substrate includes a first pixel region and a second pixel region arranged adjacent to each other. Forming the second planarization layer on the third metal layer and forming the thin film layer on the second planarization layer includes:

[0021] A first via hole is formed in the first pixel region, penetrating through the second planarization layer, the third metal layer, the passivation layer, and the first planarization layer and extending to the upper surface of the second metal layer. Wherein, the first via hole and the second metal layer form a first groove;

[0022] The thin film layer is formed on the bottom and side walls of the first groove and the second planarization layer, so that the pixel electrode corresponding to the thin film layer is in contact with the pixel electrode corresponding to the second metal layer.

[0023] Optionally, in some embodiments, the array substrate includes a first pixel region and a second pixel region arranged adjacent to each other. Forming the passivation layer on the first planarization layer and forming the third metal layer on the passivation layer includes:

[0024] A second via hole is formed in the second pixel region, penetrating through the passivation layer, the first planarization layer, and the insulating layer and extending to the upper surface of the first metal layer. Wherein, the second via hole and the first metal layer form a second groove;

[0025] The third metal layer is formed on the bottom and side walls of the second groove and the passivation layer, so that the common electrode corresponding to the third metal layer is in contact with the common electrode corresponding to the first metal layer.

[0026] In a third aspect, an embodiment of the present application further provides an electronic paper display device, including:

[0027] An array substrate, including the array substrate as described in any one of the above;

[0028] A cover plate, the cover plate being disposed opposite to the array substrate;

[0029] An electrophoresis layer, the electrophoresis layer being disposed between the array substrate and the cover plate.

[0030] The array substrate provided by the embodiment of the present application includes a substrate; a pixel structure disposed on the substrate, the pixel structure including a first metal layer, a second metal layer, a third metal layer, and a thin film layer. Among them, the first metal layer and the third metal layer are common electrodes, the second metal layer and the thin film layer are pixel electrodes, the first metal layer and the second metal layer form a first storage capacitor, the second metal layer and the third metal layer form a second storage capacitor, and the third metal layer and the thin film layer form a third storage capacitor. In the array substrate provided by the present application, by changing the manufacturing process sequence of the third metal layer, a third storage capacitor is formed between the thin film layer and the third metal layer, so that the pixel structure forms three storage capacitors. The total storage capacitance value in the array substrate is the sum of the capacitance values of the first storage capacitor, the capacitance value of the second storage capacitor, and the capacitance value of the third storage capacitor. Therefore, without changing the pixel structure space and without increasing stray capacitance, the capacitance value of the storage capacitor is increased, which not only reduces the influence of pixel leakage, but also improves the display effect of the electronic paper display device using the array substrate. Description of the Drawings

[0031] The following combines the drawings and details the specific implementation manners of the present application, and the technical solutions and their beneficial effects of the present application will be obvious.

[0032] Figure 1 It is a schematic structural diagram of an array substrate in the prior art provided by the embodiment of the present application.

[0033] Figure 2 It is a schematic structural diagram of an array substrate provided by the embodiment of the present application.

[0034] Figure 3 It is a top view of a pixel structure provided by the embodiment of the present application

[0035] Figure 4 is Figure 3 A schematic cross-sectional structural diagram of the pixel structure shown in the A-A direction.

[0036] Figure 5 is Figure 3 A schematic cross-sectional structural diagram of the pixel structure shown in the B-B direction.

[0037] Figure 6 It is a schematic flow diagram of a preparation method of an array substrate provided by the embodiment of the present application. Detailed Description of the Invention

[0038] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0039] Unless otherwise defined, the technical terms or scientific terms used in the present application shall have the ordinary meanings understood by those of ordinary skill in the art to which the present application pertains. The terms "first", "second" and similar words used in the present application do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. Words such as "comprising" or "including" mean that the elements or items appearing before the word cover the elements or items listed after the word and their equivalents, without excluding other elements or items.

[0040] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of an array substrate in the related art provided by the embodiments of the present application. Among them, the array substrate 100 may include a substrate 101, and a pixel structure is formed on the substrate 101. The pixel structure may be formed on the substrate 101 by using a mask process in sequence to form a first metal layer 102, an insulating layer 103, a semiconductor layer 104, a second metal layer 105, a first planar layer 106, a passivation layer 107, a second planar layer 108, a third metal layer 109, and a thin film layer 110.

[0041] Among them, two storage capacitors can be formed in the pixel structure through the first metal layer 102, the second metal layer 105, and the third metal layer 109. Specifically, the first metal layer 102 and the third metal layer 109 can serve as pixel electrodes of the pixel structure, the second metal layer 105 can serve as a common electrode of the pixel structure, and a first storage capacitor can be formed between the first metal layer 102 and the second metal layer 105, and a second storage capacitor can be formed between the second metal layer 105 and the third metal layer 109.

[0042] It should be noted that the holding time of the pixel structure in the electronic paper display device is relatively long, and a larger storage capacitor design is required to reduce the influence of pixel leakage. However, in the array substrate of the electronic paper display device disclosed in the related art, there are two storage capacitors, so that the capacitance value of the storage capacitor in the array substrate is small, and the effect of reducing pixel structure leakage is limited.

[0043] However, the pixel structure in the electronic paper display device is relatively small, and there is limited space to increase the space between the pixel electrode and the common electrode in the pixel structure with high pixel density. Moreover, it will also increase the risk of other stray capacitances.

[0044] To solve the problem that the capacitance value of the storage capacitor in the prior art is small within the limited pixel structure space of the electronic paper display device, the embodiments of the present application provide an array substrate, a preparation method of the array substrate, and an electronic paper display device. Please refer to Figure 2 , Figure 2 FIG. 1 is a schematic structural diagram of the array substrate provided by the embodiment of the present application. Among them, the array substrate 100 may include a substrate 101 and a pixel structure 200. The pixel structure 200 is disposed on the substrate 101, and the pixel structure 200 may include a first metal layer 201, a second metal layer 202, a third metal layer 203, and a thin film layer 204.

[0045] Among them, the first metal layer 201, the second metal layer 202, and the third metal layer 203 may be made of metal materials such as molybdenum, aluminum, copper, and titanium, and have a certain pattern. The pattern may be prepared by a single patterning process. The single patterning process may include: photoresist coating, exposure, development, etching, and photoresist stripping, etc. That is, the orthographic projections of the first metal layer 201, the second metal layer 202, and the third metal layer 203 on the substrate 101 do not occupy the entire area of the substrate 101, but are disposed on the substrate 101 in the form of a certain pattern.

[0046] The difference between the array substrate 100 provided in this embodiment and the array substrate 100 in the related art is that: the first metal layer 201 and the third metal layer 203 serve as the common electrodes of the pixel structure 200, while the second metal layer 202 and the thin film layer 204 serve as the pixel electrodes of the pixel structure 200.

[0047] Specifically, a first storage capacitor may be formed between the first metal layer 201 and the second metal layer 202, a second storage capacitor may be formed between the second metal layer 202 and the third metal layer 203, and a third storage capacitor may be formed between the third metal layer 203 and the thin film layer 204.

[0048] Optionally, the pixel structure 200 is arranged on the substrate 101 in the order of the first metal layer 201, the second metal layer 202, the third metal layer 203, and the thin film layer 204. The first metal layer 201 and the second metal layer 202 are spaced apart, the second metal layer 202 and the third metal layer 203 are spaced apart, and the third metal layer 203 and the thin film layer 204 are spaced apart. Among them, the thin film layer 204 can be an indium tin oxide thin film material. Indium tin oxide thin film is a mixture, mainly used for making liquid crystal displays, flat panel displays, plasma displays, touch screens, electronic papers, organic light emitting diodes, solar cells, antistatic coatings, various optical coatings, etc. Indium tin oxide thin film has the characteristics of electrical conduction and optical transparency. The thin film layer 204 can not only be used as the pixel electrode in the storage capacitor, but also play a protective role for the pixel structure 200.

[0049] In the array substrate provided in this embodiment, by changing the manufacturing process sequence of the third metal layer 203, a third storage capacitor is formed between the thin film layer 204 and the third metal layer 203, so that the pixel structure forms three storage capacitors. The total storage capacitance value in the array substrate is the sum of the capacitance values of the first storage capacitor, the second storage capacitor, and the third storage capacitor. Therefore, without changing the space of the pixel structure 200 and without increasing the stray capacitance, the capacitance value of the storage capacitor in the entire pixel structure 200 is increased, which not only reduces the influence of pixel leakage, but also improves the display effect of the electronic paper display device using the array substrate 100.

[0050] Further, please continue to refer to Figure 2 , the pixel structure 200 is sequentially provided with a first metal layer 201, an insulating layer 205, a semiconductor layer 206, a second metal layer 202, a first planarization layer 207, a passivation layer 208, a third metal layer 203, a second planarization layer 209, and a thin film layer 204 on the substrate 101. Among them, the first metal layer 201, the insulating layer 205, the semiconductor layer 206, the second metal layer 202, the passivation layer 208, the third metal layer 203, the second planarization layer 209, and the thin film layer 204 can all be prepared by a mask process, that is, the pixel structure 200 is prepared by an eight-time mask process. Among them, the insulating layer 205 is arranged between the first metal layer 201 and the second metal layer 202, the first planarization layer 207 and the passivation layer 208 are arranged between the second metal layer 202 and the third metal layer 203, and the passivation layer 208 is arranged on the first planarization layer 207, and the second planarization layer 209 is arranged between the third metal layer 203 and the thin film layer 204.

[0051] Specifically, a first metal layer 201 can be deposited on the substrate 101 and patterned; an insulating layer 205 is deposited on the first metal layer 201; a semiconductor layer 206 is deposited on the insulating layer 205; a second metal layer 202 is deposited on the semiconductor layer 206, and a part of the second metal layer 202 is disposed on the insulating layer 205; a first planarization layer 207 is deposited on the second metal layer 202; a passivation layer 208 is deposited on the first planarization layer 207; a third metal layer 203 is deposited on the passivation layer 208; a second planarization layer 209 is deposited on the third metal layer 203; finally, a thin film layer 204 is deposited on the second planarization layer 209, and the thin film layer 204 protects the entire pixel structure. The difference between the process of fabricating the pixel structure 200 in this embodiment and the prior art is that: in the prior art, the second planarization layer 108 is deposited on the passivation layer 107 first, then the third metal layer 109 is deposited on the second planarization layer 108, and finally the thin film layer 110 is deposited on the third metal layer 109. It can be seen that the fabrication sequence of the second planarization layer 209 and the third metal layer 203 is changed in this embodiment. Since the third metal layer 109 and the thin film layer 110 are in direct contact in the prior art, a storage capacitor cannot be formed therebetween. However, in this embodiment, by disposing the second planarization layer 209 between the third metal layer 203 and the thin film layer 204, the third metal layer 203 and the thin film layer 204 form a third storage capacitor, thereby increasing the capacitance value of the overall storage capacitor of the pixel structure 200.

[0052] Please refer to Figures 3 to 5 , Figure 3 which is a top view of the pixel structure provided by an embodiment of the present application, Figure 4 and Figure 3 is a schematic cross-sectional structure diagram of the pixel structure shown in Figure 5 along the A-A direction, Figure 3 and

[0053] is a schematic cross-sectional structure diagram of the pixel structure shown in

[0054] along the B-B direction. Wherein, the pixel structure 200 can include a first pixel region 220 and a second pixel region 240, and the first pixel region 220 and the second pixel region 240 are adjacently arranged.

[0053] Among them, the first pixel region 220 can include a first part 2011 of the first metal layer, the second metal layer 202, a first part 2031 of the third metal layer, and a first part 2041 of the thin film layer. A first storage capacitor is formed between the first part 2011 of the first metal layer and the second metal layer 202, a second storage capacitor is formed between the second metal layer 202 and the first part 2031 of the third metal layer, and a third storage capacitor is formed between the first part 2031 of the third metal layer and the first part 2041 of the thin film layer.

[0054] Optionally, in the first pixel region 220, a first portion 2011 of the first metal layer, an insulating layer 205, a second metal layer 202, a first planarization layer 207, a passivation layer 208, a first portion 2031 of the third metal layer, a second planarization layer 209, and a first portion 2041 of the thin film layer are sequentially disposed on the substrate 101.

[0055] It should be noted that, please continue to refer to Figure 3 , the first pixel region 220 is provided with a first via 221, and the first via 221 can sequentially penetrate through the second planarization layer 209, the third metal layer 203, specifically the first portion 2031 of the third metal layer, the passivation layer 208, and the first planarization layer 207, and extend to the upper surface of the second metal layer 202, so that a first groove 222 is formed between the first via 221 and the upper surface of the second metal layer 202.

[0056] Specifically, the first planarization layer 207, the passivation layer 208, the first portion 2031 of the third metal layer, and the second planarization layer 209 are defined into patterns through a patterning process, so as to form a first via 221 penetrating through the first planarization layer 207, the passivation layer 208, the first portion 2031 of the third metal layer, and the second planarization layer 209 in the first pixel region 220, so that a part of the first portion 2041 of the thin film layer can cover the bottom and side walls of the first groove 222, so that the pixel electrode corresponding to the first portion 2041 of the thin film layer is in contact with the pixel electrode corresponding to the second metal layer 202, realizing the connection of the two pixel electrodes. In addition, another part of the first portion 2041 of the thin film layer covers the second planarization layer 209.

[0057] Among them, the second pixel region 240 may include a second portion 2012 of the first metal layer, a second portion 2032 of the third metal layer, and a second portion 2042 of the thin film layer. The difference between the second pixel region 240 and the first pixel region 220 is that the second metal layer 202 is not provided on the second pixel region 240, that is, the second metal layer 202 is only provided in the first pixel region 220, and the orthographic projection region of the second metal layer 202 on the substrate 101 is not within the second pixel region 240. Then, the second metal layer 202 can be used as the boundary between the first pixel region 220 and the second pixel region 240. A third storage capacitor is formed between the second portion 2032 of the third metal layer and the second portion 2042 of the thin film layer.

[0058] It should be noted that since the first part 2031 of the third metal layer and the second part 2032 of the third metal layer are in the same layer and are formed by the same process; the first part 2041 of the thin film layer and the second part 2042 of the thin film layer are in the same layer and are formed by the same process. Therefore, the third storage capacitor can be formed by the first part 2031 of the third metal layer and the first part 2041 of the thin film layer, or by the second part 2032 of the third metal layer and the second part 2042 of the thin film layer.

[0059] Optionally, in the second pixel region 240, the second part 2012 of the first metal layer, the insulating layer 205, the first planarization layer 207, the passivation layer 208, the second part 2032 of the third metal layer, the second planarization layer 209, and the second part 2042 of the thin film layer are sequentially disposed on the substrate 101.

[0060] It should be noted that please continue to refer to Figure 3 , the second pixel region 240 is provided with a second via 223, and the second via 223 can sequentially penetrate through the passivation layer 208, the first planarization layer 207, and the insulating layer 205 and extend to the upper surface of the second part 2012 of the first metal layer, so that the second via 223 and the upper surface of the second part 2012 of the first metal layer form a second groove 224.

[0061] Specifically, the insulating layer 205, the first planarization layer 207, and the passivation layer 208 are defined into patterns through a patterning process, so as to form a second via 223 penetrating through the insulating layer 205, the first planarization layer 207, and the passivation layer 208 in the second pixel region 240, so that a part of the second part 2032 of the third metal layer can cover the bottom and side walls of the second groove 224, so that the common electrode corresponding to the second part 2032 of the third metal layer is in contact with the common electrode corresponding to the second part 2012 of the first metal layer, realizing the connection of the two common electrodes. In addition, another part of the second part 2032 of the third metal layer covers the passivation layer 208, the second planarization layer 209 covers the passivation layer and a part of the second planarization layer 209 is located in the second groove 224; the second part 2042 of the thin film layer covers the second planarization layer 209 and a part of the second part 2042 of the thin film layer is located in the second groove 224.

[0062] It should be noted that the first part 2011 of the first metal layer, the first part 2041 of the thin film layer, and the first part 2031 of the third metal layer in the first pixel region 220 and the second part 2012 of the first metal layer, the second part 2042 of the thin film layer, and the second part 2032 of the third metal layer in the second pixel region 240 can be made by the same process, so that the preparation process flow can be reduced, and the use of the same process can ensure that the stacked structures in the first pixel region 220 and the second pixel region 240 are smoother.

[0063] It can be understood that the difference between the array substrate 100 provided in this embodiment and the array substrate 100 in the related art is that by changing the manufacturing process sequence of the second planarization layer 209 and the third metal layer 203, a second planarization layer 209 is provided between the third metal layer 203 and the thin film layer 204, so that a third storage capacitor is formed between the third metal layer 203 and the thin film layer 204, forming three storage capacitors, and the capacitance value of the storage capacitor is increased compared with the related art. In addition, setting the second planarization layer 209 on the third metal layer 203 can also prevent the third metal layer 203 from being corroded.

[0064] As can be seen from the above, in the array substrate 100 provided in this embodiment, by changing the manufacturing process sequence of the third metal layer 203, a third storage capacitor is formed between the thin film layer 204 and the third metal layer 203, so that the pixel structure forms three storage capacitors. The total storage capacitance value in the array substrate is the sum of the capacitance values of the first storage capacitor, the second storage capacitor, and the third storage capacitor. Therefore, without changing the space of the pixel structure 200 and without increasing the stray capacitance, the capacitance value of the storage capacitor is increased. In addition, by opening vias in different pixel regions, the two pixel electrodes and the two common electrodes are connected to each other, which not only reduces the influence of pixel leakage, but also improves the display effect of the electronic paper display device using the array substrate 100.

[0065] In addition, only by changing the manufacturing process sequence between the second planarization layer 209 and the third metal layer 203, the manufacturing process and cost are not increased, and the technical effect of reducing the leakage of the pixel structure is achieved in a simple manner.

[0066] The embodiment of the present application also provides a method for manufacturing an array substrate. Please refer to Figure 6 , Figure 6 which is a schematic flow chart of the method for manufacturing the array substrate provided by the embodiment of the present application. Among them, the array substrate can be applied to an electronic paper display device, and the specific steps of the method for manufacturing the array substrate are as follows:

[0067] 301, provide a substrate.

[0068] Provide a substrate, which can be a glass substrate or a substrate made of a transparent material.

[0069] 302. Form a first metal layer on the substrate, and form an insulating layer on the first metal layer.

[0070] Form a first metal layer on the substrate. The first metal layer is prepared by a single patterning process, that is, the orthographic projection area of the first metal layer on the substrate does not occupy the entire area of the substrate, but is arranged on the substrate in the form of a certain pattern. Deposit and form an insulating layer on the first metal layer.

[0071] 303. Form a second metal layer on the insulating layer, and form a first planarization layer on the second metal layer.

[0072] 304. Form a passivation layer on the first planarization layer, and form a third metal layer on the passivation layer.

[0073] 305. Form a second planarization layer on the third metal layer, and form a thin film layer on the second planarization layer.

[0074] Among them, the first metal layer and the third metal layer are common electrodes, the second metal layer and the thin film layer are pixel electrodes. The first metal layer and the second metal layer are arranged at intervals, the second metal layer and the third metal layer are arranged at intervals, and the third metal layer and the thin film layer are arranged at intervals. The first metal layer and the second metal layer form a first storage capacitor, the second metal layer and the third metal layer form a second storage capacitor, and the third metal layer and the thin film layer form a third storage capacitor.

[0075] In the pixel structure, a first metal layer 201, an insulating layer 205, a semiconductor layer 206, a second metal layer 202, a first planarization layer 207, a passivation layer 208, a third metal layer 203, a second planarization layer 209, and a thin film layer 204 are sequentially arranged on the substrate 101. Among them, the first metal layer 201, the insulating layer 205, the semiconductor layer 206, the second metal layer 202, the passivation layer 208, the third metal layer 203, the second planarization layer 209, and the thin film layer 204 can all be prepared by a mask process, that is, the pixel structure 200 is prepared by an eight-time mask process. Among them, the insulating layer 205 is arranged between the first metal layer 201 and the second metal layer 202, the first planarization layer 207 and the passivation layer 208 are arranged between the second metal layer 202 and the third metal layer 203, and the passivation layer 208 is arranged on the first planarization layer 207, and the second planarization layer 209 is arranged between the third metal layer 203 and the thin film layer 204.

[0076] Specifically, a first metal layer 201 can be deposited on the substrate 101 and patterned; an insulating layer 205 is deposited on the first metal layer 201; a semiconductor layer 206 is deposited on the insulating layer 205; a second metal layer 202 is deposited on the semiconductor layer 206, and a part of the second metal layer 202 is disposed on the insulating layer 205; a first planarization layer 207 is deposited on the second metal layer 202; a passivation layer 208 is deposited on the first planarization layer 207; a third metal layer 203 is deposited on the passivation layer 208; a second planarization layer 209 is deposited on the third metal layer 203; finally, a thin film layer 204 is deposited on the second planarization layer 209, and the thin film layer 204 protects the entire pixel structure. The difference between the preparation process of the pixel structure 200 in this embodiment and the prior art is that: in the prior art, the second planarization layer 108 is first deposited on the passivation layer 107, then the third metal layer 109 is deposited on the second planarization layer 108, and finally the thin film layer 110 is deposited on the third metal layer 109. It can be seen that the preparation order of the second planarization layer 209 and the third metal layer 203 is changed in this embodiment. Since the third metal layer 109 and the thin film layer 110 are in direct contact in the prior art, a storage capacitor cannot be formed therebetween. However, in this embodiment, by providing the second planarization layer 209 between the third metal layer 203 and the thin film layer 204, the third metal layer 203 and the thin film layer 204 form a third storage capacitor, thereby increasing the capacitance value of the overall storage capacitor of the pixel structure 200.

[0077] Among them, the pixel structure 200 may include a first pixel region 220 and a second pixel region 240, and the first pixel region 220 and the second pixel region 240 are disposed adjacent to each other.

[0078] Among them, the first pixel region 220 may include a first part 2011 of the first metal layer, the second metal layer 202, a first part 2031 of the third metal layer, and a first part 2041 of the thin film layer. A first storage capacitor is formed between the first part 2011 of the first metal layer and the second metal layer 202, a second storage capacitor is formed between the second metal layer 202 and the first part 2031 of the third metal layer, and a third storage capacitor is formed between the first part 2031 of the third metal layer and the first part 2041 of the thin film layer.

[0079] Optionally, in the first pixel region 220, the first part 2011 of the first metal layer, the insulating layer 205, the second metal layer 202, the first planarization layer 207, the passivation layer 208, the first part 2031 of the third metal layer, the second planarization layer 209, and the first part 2041 of the thin film layer are sequentially disposed on the substrate 101.

[0080] The first pixel region 220 is provided with a first via 221, and the first via 221 can sequentially penetrate through the second planarization layer 209, the third metal layer 203, specifically the first part 2031 of the third metal layer, the passivation layer 208, and the first planarization layer 207, and extend to the upper surface of the second metal layer 202, so that a first groove 222 is formed between the first via 221 and the upper surface of the second metal layer 202.

[0081] Specifically, the first planarization layer 207, the passivation layer 208, the first part 2031 of the third metal layer, and the second planarization layer 209 are defined into patterns through a patterning process, so as to form a first via 221 penetrating through the first planarization layer 207, the passivation layer 208, the first part 2031 of the third metal layer, and the second planarization layer 209 in the first pixel region 220, so that a part of the first part 2041 of the thin film layer can cover the bottom and side walls of the first groove 222, so that the pixel electrode corresponding to the first part 2041 of the thin film layer is in contact with the pixel electrode corresponding to the second metal layer 202, realizing the connection of the two pixel electrodes. In addition, another part of the first part 2041 of the thin film layer covers the second planarization layer 209.

[0082] Wherein, the second pixel region 240 may include a second part 2012 of the first metal layer, a second part 2032 of the third metal layer, and a second part 2042 of the thin film layer. The difference between the second pixel region 240 and the first pixel region 220 is that the second metal layer 202 is not provided on the second pixel region 240, that is, the second metal layer 202 is only provided in the first pixel region 220, and the orthographic projection region of the second metal layer 202 on the substrate 101 is not within the second pixel region 240, so the second metal layer 202 can be used as the boundary between the first pixel region 220 and the second pixel region 240. A third storage capacitor is formed between the second part 2032 of the third metal layer and the second part 2042 of the thin film layer.

[0083] It should be noted that since the first part 2031 of the third metal layer and the second part 2032 of the third metal layer are in the same layer and are made by the same process; the first part 2041 of the thin film layer and the second part 2042 of the thin film layer are in the same layer and are made by the same process, therefore, the third storage capacitor can be formed by the first part 2031 of the third metal layer and the first part 2041 of the thin film layer, or can be formed by the second part 2032 of the third metal layer and the second part 2042 of the thin film layer.

[0084] Optionally, in the second pixel region 240, the second part 2012 of the first metal layer, the insulating layer 205, the first planarization layer 207, the passivation layer 208, the second part 2032 of the third metal layer, the second planarization layer 209, and the second part 2042 of the thin film layer are sequentially arranged on the substrate 101.

[0085] As can be seen from the above, in the array substrate provided in this embodiment, the manufacturing sequence of the third metal layer is changed, and a third storage capacitor is formed between the thin film layer and the third metal layer, so that the pixel structure has three storage capacitors. The total storage capacitance value in the array substrate is the sum of the capacitance values of the first storage capacitor, the second storage capacitor, and the third storage capacitor. Therefore, without changing the space of the pixel structure 200 and without increasing the stray capacitance, the capacitance value of the storage capacitor is increased. In addition, by opening vias in different pixel regions, two pixel electrodes and two common electrodes are connected to each other, which not only reduces the influence of pixel leakage, but also improves the display effect of the electronic paper display device using this array substrate.

[0086] It should be noted that the second pixel region 240 is provided with a second via 223. The second via 223 can sequentially penetrate the passivation layer 208, the first planarization layer 207, and the insulating layer 205, and extend to the upper surface of the second part 2012 of the first metal layer, so that the second via 223 forms a second groove 224 with the upper surface of the second part 2012 of the first metal layer.

[0087] Specifically, the insulating layer 205, the first planarization layer 207, and the passivation layer 208 are defined into patterns through a patterning process, so as to form a second via 223 that penetrates the insulating layer 205, the first planarization layer 207, and the passivation layer 208 in the second pixel region 240, so that a part of the second part 2032 of the third metal layer can cover the bottom and side walls of the second groove 224, so that the common electrode corresponding to the second part 2032 of the third metal layer contacts the common electrode corresponding to the second part 2012 of the first metal layer, realizing the connection of the two common electrodes. In addition, another part of the second part 2032 of the third metal layer covers the passivation layer 208, the second planarization layer 209 covers the passivation layer, and a part of the second planarization layer 209 is located in the second groove 224; the second part 2042 of the thin film layer covers the second planarization layer 209, and a part of the second part 2042 of the thin film layer is located in the second groove 224.

[0088] It should be noted that the first part 2011 of the first metal layer, the first part 2041 of the thin film layer, and the first part 2031 of the third metal layer in the first pixel region 220 and the second part 2012 of the first metal layer, the second part 2042 of the thin film layer, and the second part 2032 of the third metal layer in the second pixel region 240 can be made by the same process, so as to reduce the manufacturing process flow, and using the same process for manufacturing can ensure that the stacked structures in the first pixel region 220 and the second pixel region 240 are flatter.

[0089] It can be understood that the difference between the array substrate 100 provided in this embodiment and the array substrate 100 in the related art is that by changing the manufacturing process sequence of the second planarization layer 209 and the third metal layer 203, a second planarization layer 209 is provided between the third metal layer 203 and the thin film layer 204, thereby forming a third storage capacitor between the third metal layer 203 and the thin film layer 204, and three storage capacitors are formed, increasing the capacitance value of the storage capacitor compared with the related art. In addition, setting the second planarization layer 209 on the third metal layer 203 can also prevent the third metal layer 203 from being corroded.

[0090] In addition, only by changing the manufacturing process sequence between the second planarization layer and the third metal layer, the manufacturing process and cost are not increased, and the technical effect of reducing the leakage of the pixel structure is achieved in a simple manner.

[0091] The embodiment of the present application further provides an electronic paper display device. The electronic paper display device can be a wearable device such as a watch or a bracelet, or the display device can be an electronic device such as a mobile phone or a tablet computer, or the display device can be a product or component with a display function such as a television, a monitor, a notebook computer, a digital photo frame or a navigator, etc.

[0092] The electronic paper display device may include an array substrate 100, a cover plate, and an electrophoretic layer. Among them, the cover plate is disposed opposite to the array substrate 100; the electrophoretic layer is disposed between the array substrate and the cover plate. The array substrate 100 has a plurality of pixel structures arranged in an array, and each pixel structure includes a pixel electrode and a common electrode. The pixel electrode and the common electrode can form at least three storage capacitors to maintain the stability of the voltage applied to the pixel electrode by forming the storage capacitors.

[0093] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0094] The above has introduced in detail the array substrate, the preparation method of the array substrate, and the electronic paper display device provided by the embodiments of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The descriptions of the above embodiments are only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. An array substrate, characterized in that, comprising: a substrate; a pixel structure disposed on the substrate, the pixel structure including a first metal layer, a second metal layer, a third metal layer, and a thin film layer which are sequentially arranged at intervals, wherein the first metal layer and the third metal layer are common electrodes, the second metal layer and the thin film layer are pixel electrodes, a first storage capacitor is formed between the first metal layer and the second metal layer, a second storage capacitor is formed between the second metal layer and the third metal layer, and a third storage capacitor is formed between the third metal layer and the thin film layer; wherein the pixel structure includes a first pixel region and a second pixel region which are adjacently arranged, the first pixel region includes a first part of the first metal layer, the second metal layer, a first part of the third metal layer, and a first part of the thin film layer, the second pixel region includes a second part of the first metal layer, a second part of the third metal layer, and a second part of the thin film layer, the first part of the first metal layer and the second metal layer form the first storage capacitor, the second metal layer and the first part of the third metal layer form the second storage capacitor, the first part of the third metal layer and the first part of the thin film layer as well as the second part of the third metal layer and the second part of the thin film layer form the third storage capacitor; a first via hole is provided in the first pixel region, and the pixel electrode corresponding to the thin film layer contacts the pixel electrode corresponding to the second metal layer through the first via hole; a second via hole is provided in the second pixel region, and the common electrode corresponding to the third metal layer contacts the common electrode corresponding to the first metal layer.

2. The array substrate according to claim 1, characterized in that, an insulating layer is provided between the first metal layer and the second metal layer in the pixel structure, a first planarization layer and a passivation layer are provided between the second metal layer and the third metal layer, the first planarization layer is disposed on the second metal layer, the passivation layer is disposed on the first planarization layer, and a second planarization layer is provided between the third metal layer and the thin film layer.

3. The array substrate according to claim 2, characterized in that, the first via hole sequentially penetrates through the second planarization layer, the third metal layer, the passivation layer, and the first planarization layer and extends to the upper surface of the second metal layer, the first via hole forms a first groove with the second metal layer, and a part of the thin film layer covers the bottom and side walls of the first groove.

4. The array substrate according to claim 2, characterized in that, the second via hole sequentially penetrates through the passivation layer, the first planarization layer, and the insulating layer and extends to the upper surface of the first metal layer, the second via hole forms a second groove with the first metal layer, and a part of the third metal layer covers the bottom and side walls of the second groove.

5. The array substrate according to claim 2, characterized in that, The first part of the first metal layer in the first pixel region and the second part of the first metal layer in the second pixel region are formed by the same process. The first part of the third metal layer in the first pixel region and the second part of the third metal layer in the second pixel region are formed by the same process. The first part of the thin film layer in the first pixel region and the second part of the thin film layer in the second pixel region are formed by the same process.

6. A method for manufacturing an array substrate, characterized in that, comprising: providing a substrate; forming a first metal layer on the substrate, and forming an insulating layer on the first metal layer; forming a second metal layer on the insulating layer, and forming a first planarization layer on the second metal layer; forming a passivation layer on the first planarization layer, and forming a third metal layer on the passivation layer; forming a second planarization layer on the third metal layer, and forming a thin film layer on the second planarization layer; wherein, the first metal layer and the third metal layer are common electrodes, the second metal layer and the thin film layer are pixel electrodes, the first metal layer and the second metal layer form a first storage capacitor, the second metal layer and the third metal layer form a second storage capacitor, the third metal layer and the thin film layer form a third storage capacitor, and the material of the thin film layer includes indium tin oxide; wherein, the array substrate includes a first pixel region and a second pixel region arranged adjacent to each other. Forming a second planarization layer on the third metal layer and forming a thin film layer on the second planarization layer includes: forming a first via hole in the first pixel region that penetrates the second planarization layer, the third metal layer, the passivation layer, and the first planarization layer and extends to the upper surface of the second metal layer, and the pixel electrode corresponding to the thin film layer contacts the pixel electrode corresponding to the second metal layer through the first via hole; Forming a passivation layer on the first planarization layer and forming a third metal layer on the passivation layer includes: forming a second via hole in the second pixel region that penetrates the passivation layer, the first planarization layer, and the insulating layer and extends to the upper surface of the first metal layer; the common electrode corresponding to the third metal layer contacts the common electrode corresponding to the first metal layer through the second via hole.

7. The method for manufacturing an array substrate according to claim 6, characterized in that, forming a second planarization layer on the third metal layer and forming a thin film layer on the second planarization layer includes: the first via hole and the second metal layer form a first groove; forming the thin film layer on the bottom and side walls of the first groove and on the second planarization layer.

8. The method for manufacturing an array substrate according to claim 6, characterized in that, forming a passivation layer on the first planarization layer and forming a third metal layer on the passivation layer includes: the second via hole and the first metal layer form a second groove; forming the third metal layer on the bottom and side walls of the second groove and on the passivation layer.

9. An electronic paper display device, characterized in that, comprising: An array substrate, including the array substrate according to any one of claims 1 to 5; A cover plate, the cover plate being disposed opposite to the array substrate; An electrophoretic layer, the electrophoretic layer being disposed between the array substrate and the cover plate.

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