Display panel and display device

Abstract

The present application provides a display panel and a display device. The display panel includes: a substrate; sub-pixels arranged in an array on the substrate, each sub-pixel including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the pixel circuit including a driving transistor, and the light-emitting element including a pixel electrode; at least a part of a plurality of first connection portions are arranged at intervals along a first direction, each pixel electrode is connected to a driving transistor through a first connection portion, and the first connection portion is further configured to connect a signal trace, and the area of each first connection portion arranged along the first direction increases in sequence or the areas of each first connection portion are the same, and the area is the orthographic projection area of the first connection portion on the substrate. By improving the arrangement regularity of the first connection portions on the display panel in the display panel, the present application can improve the uniformity of the sub-pixel display when the pixel circuit drives the sub-pixel to emit light, thereby improving the display effect of the display panel.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and particularly to a display panel and a display device. Background Art

[0002] As a new panel technology, AMOLED display technology is recognized by the industry as the most promising display technology due to its advantages in display aspects such as low power consumption, low cost, wide color gamut, high resolution, and high color saturation, as well as its characteristics such as bendability and easy transformation of form for portable use.

[0003] In a display panel, signal lines for providing signals to sub-pixels are usually provided. The signal lines are connected to driving switches through connection traces. However, for a high-resolution AMOLED display device, when the same power supply voltage is used to supply power to each pixel unit in its display area, due to the irregular wiring method of the connection traces, the emission brightness of the corresponding pixel units is different, resulting in areas with brightness difference (Mura) in the display panel, uneven display, and affecting the display effect of the display panel. Summary of the Invention

[0004] The present application provides a display panel and a display device to solve the problem of uneven display of the display panel.

[0005] On the one hand, the present application provides a display panel, including:

[0006] A substrate;

[0007] Sub-pixels, arranged in an array on the substrate. Each sub-pixel includes a pixel circuit and a light-emitting element. The pixel circuit is used to drive the light-emitting element. The pixel circuit includes a driving transistor, and the light-emitting element includes a pixel electrode;

[0008] A plurality of first connection parts, at least a part of the plurality of first connection parts are arranged at intervals along a first direction. Each pixel electrode is connected to a driving transistor through the first connection part. The first connection part is also used to connect a signal trace. The area of each first connection part arranged along the first direction increases in sequence or the area of each first connection part is the same. The area is the orthographic projection area of the first connection part on the substrate.

[0009] In a possible implementation manner of the present application, the display panel includes a first display area and a fan-out area. The fan-out area coincides with the first display area, and the first connection part is located in the first display area.

[0010] In a possible implementation manner of the present application, the display panel further includes a second display area, the first display area and the second display area are arranged adjacent to each other, the first connection portion is further located in the second display area, and the area of each first connection portion in the first display area is the same as the area of each first connection portion in the second display area.

[0011] In a possible implementation manner of the present application, when the area of each first connection portion arranged along the first direction increases in sequence, the width of each first connection portion is the same, and the length of each first connection portion increases in sequence along the first direction.

[0012] In a possible implementation manner of the present application, at least another part of the plurality of first connection portions is arranged along the second direction, and the orthographic projection area of each first connection portion arranged along the second direction on the substrate is the same, and the first direction and the second direction intersect.

[0013] In a possible implementation manner of the present application, the driving transistor includes:

[0014] An active layer, disposed on one side of the substrate;

[0015] A gate layer, disposed on the active layer;

[0016] A source-drain layer, disposed on the gate layer;

[0017] The display panel further includes a first via hole and a second via hole, and each first connection portion is connected to a source-drain layer through the first via hole and is connected to a pixel electrode through the second via hole.

[0018] In some embodiments, the display panel further includes:

[0019] A plurality of second connection portions, each second connection portion is connected between a pixel electrode and a first connection portion, and the first connection portion and the second connection portion are made of a transparent conductive material.

[0020] In some embodiments, the orthographic projections of the first via hole and the second via hole on the substrate are arranged adjacent to each other, or the orthographic projections of the first via hole and the second via hole on the substrate are arranged at intervals.

[0021] In some embodiments, the driving transistor further includes:

[0022] The first flat layer is disposed on the source-drain layer, the first connection portion is disposed on the first flat layer, the first flat layer is provided with the first via hole, the source-drain layer is exposed in the first via hole, and the first connection portion is electrically connected to the source-drain layer through the first via hole;

[0023] The second flat layer is disposed on the first connection portion, the second connection portion is disposed on the second flat layer, the second flat layer is provided with a second via hole, the first connection portion is exposed in the second via hole, and the second connection portion is electrically connected to the first connection portion through the second via hole.

[0024] In a possible implementation manner of the present application, the driving transistor further includes:

[0025] The bridging layer is disposed between the source-drain layer and the first connection portion, one end of the bridging layer is connected to the first connection portion, and the other end is connected to the source or drain in the source-drain layer.

[0026] On the other hand, the present application further provides a display panel including the display panel.

[0027] In the display panel and the display device provided by the present application, the first connection portion of the display panel is used to connect the driving transistor and the pixel electrode, and is also used to connect the signal trace. By setting the orthographic projection area of the first connection portion along the first direction Y on the substrate to increase in sequence, it is possible to avoid too large a brightness difference in the areas corresponding to different first connection portions, so that in the first direction Y of the display panel, the emission brightness of the sub-pixels corresponding to the first connection portion shows a gradient form, thereby weakening the boundary line of the display brightness in the first direction Y, and thus improving the brightness uniformity of the display panel. Or by setting the orthographic projection area of each first connection portion on the substrate to be the same, the regularity of the distribution of the first connection portion is improved, so that the emission of the sub-pixels corresponding to the first connection portion is regular, thereby improving the overall brightness uniformity of the display panel. In the embodiments of the present application, by improving the arrangement regularity of the first connection portion on the display panel, when the pixel circuit drives the sub-pixels to emit light, the uniformity of the sub-pixel display can be improved, thereby improving the overall display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The following will make the technical solutions and other beneficial effects of the present application obvious by describing the specific embodiments of the present application in detail with reference to the drawings.

[0029] Figure 1 It is a top view structural schematic diagram of the display panel provided by the embodiment of the present application.

[0030] Figure 2 In the embodiment of the present application Figure 1Partial enlarged schematic diagram of part A.

[0031] Figure 3 Top view structural schematic diagram of a display panel provided by another embodiment of the present application.

[0032] Figure 4 In the embodiment of the present application Figure 3 Partial enlarged schematic diagram of part B.

[0033] Figure 5 Structural schematic diagram of each area of a display panel provided by an embodiment of the present application.

[0034] Figure 6 Cross-sectional structural schematic diagram of a display panel provided by an embodiment of the present application.

[0035] Figure 7 Top view structural schematic diagram of a display panel provided by another embodiment of the present application.

[0036] Figure 8 In the embodiment of the present application Figure 7 Partial enlarged schematic diagram of part C. Detailed implementation manners

[0037] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0038] In addition, in the description of the present application, "a plurality of" means two or more unless otherwise clearly and specifically defined. In the present application, unless otherwise clearly defined and limited, the first feature being "above" or "below" the second feature may include direct contact between the first and second features, or may include indirect contact between the first and second features through other features therebetween. Moreover, the first feature being "above", "over" and "on" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the horizontal height of the first feature is higher than that of the second feature. The first feature being "below", "under" and "beneath" the second feature includes the first feature being directly below and obliquely below the second feature, or simply indicating that the horizontal height of the first feature is lower than that of the second feature. In the description of the present application, "a plurality of" means two or more unless otherwise clearly and specifically defined.

[0039] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0040] Embodiments of the present application provide a display panel and a display device, which are introduced in detail below respectively.

[0041] Please refer to Figures 1 - 8 , embodiments of the present application provide a display panel, wherein the display panel is provided with a plurality of sub-pixels 20, and at least one sub-pixel 20 includes a pixel circuit (not shown in the figure) and a light-emitting element 30.

[0042] The pixel circuit is used to drive the connected light-emitting element 30. For example, the pixel circuit is configured to provide a driving current to drive the light-emitting element 30 to emit light. Among them, the pixel circuit may include a plurality of thin-film transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C (3 thin-film transistors and 1 capacitor) structure, a 7T1C (7 thin-film transistors and 1 capacitor) structure, or a 5T1C (5 thin-film transistors and 1 capacitor) structure, etc. Through the pixel circuit, corresponding scan signals, light-emitting driving signals, data signals, etc. can be received to drive the light-emitting element 30 to emit light. The specific principle of the pixel circuit driving the light-emitting element 30 to emit light will not be elaborated here.

[0043] In the embodiments of the present application, the pixel circuit includes a driving transistor 21, and the light-emitting element 30 includes a pixel electrode 31. Among them, the pixel electrode 31 may be the anode of the OLED light-emitting device.

[0044] Among them, the substrate 10 may be a flexible substrate 10 or a rigid substrate 10. Exemplarily, when the substrate 10 is a flexible substrate 10, the substrate 10 may adopt materials such as polyimide (PI), polyethylene naphthalate (PEN), and polyethylene terephthalate (PET); when the substrate 10 is a rigid substrate 10, the substrate 10 may be a rigid material such as glass or quartz. Taking the substrate 10 as a PI substrate as an example, the substrate 10 may adopt a single-layer PI structure, or the substrate 10 may also adopt a double-layer PI structure. As Figure 6 shown, the substrate 10 includes a first PI substrate 11, a first buffer layer 12, a second PI substrate 13, and a second buffer layer 14 sequentially arranged from bottom to top along its thickness direction.

[0045] An array of multiple driving transistors 21 is disposed on a substrate 10, and multiple pixel electrodes 31 are disposed on the driving transistors 21. Herein, in this embodiment, the display panel is taken as an OLED display panel as an example. Correspondingly, the light-emitting element 30 can be an organic light-emitting diode (OLED). The light-emitting element 30 emits red light, green light, blue light, or white light, etc. under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element 30 can be determined as needed. The pixel electrode 31 in the embodiment of the present application can be the anode of the light-emitting element 30. Specifically, the light-emitting element 30 can include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element 30 can be electrically connected to the driving transistor 21 in the corresponding pixel circuit.

[0046] Among them, the display panel further includes a plurality of first connection portions 40 disposed on the substrate 10. At least a part of the plurality of first connection portions 40 are spaced apart along the first direction Y. Each pixel electrode 31 is connected to one driving transistor 21 through the first connection portion 40. The first connection portion 40 corresponds to the sub-pixel array arrangement. Specifically, the first connection portion 40 can be arranged in multiple rows along the first direction Y and multiple rows along the second direction X, for example. Among them, the first connection portions 40 arranged in a row along the second direction X can be referred to as the same row of first connection portions 40, and the first connection portions 40 arranged in a row along the first direction Y can be referred to as the same column of first connection portions 40. Among them, the same column of first connection portions 40 can be electrically connected to one data line. Among them, the first direction Y can be the vertical direction parallel to the display plane of the display panel, and the second direction X can be the horizontal direction parallel to the display plane of the display panel.

[0047] As Figure 2 shown, the area of each first connection portion 40 disposed along the first direction Y increases in sequence, or, as Figure 4As shown, the areas of each of the first connection parts 40 are the same. Exemplarily, for each of the first connection parts 40 arranged along the first direction Y in the display panel, that is, each of the first connection parts 40 in the same column, its area may increase successively from top to bottom in the first direction Y, or alternatively, may increase successively from bottom to top in the first direction Y, that is, the areas of the first connection parts 40 are arranged in a gradient in the first direction Y. Of course, it is also possible that the areas of each of the first connection parts 40 arranged along the first direction Y in the display panel are all the same. The area herein refers to the orthographic projection area of the first connection part 40 on the substrate 10. By improving the regularity of the area distribution of the first connection parts 40, it is possible to prevent, in the setting area of the first connection parts 40, the brightness of the sub-pixels above different first connection parts 40 from being different due to continuous reflection of light caused by different areas of the first connection parts 40, resulting in an obvious mutation in the display brightness at a certain location. That is, by controlling the density of the distribution of the first connection parts 40, the display area where the first connection parts 40 are located plays a role in the transition of the display effect, thereby reducing the problem of uneven display caused by the setting of the first connection parts 40.

[0048] In the embodiment of the present application, the first connection part 40 of the display panel is used to connect the driving transistor 21 and the pixel electrode 31, and is also used to connect the signal trace. By setting the orthographic projection area of the first connection part 40 along the first direction Y on the substrate 10 to increase successively, it is possible to avoid too large a difference in brightness in the areas corresponding to different first connection parts 40, so that the emission brightness of the sub-pixels 20 corresponding to the first connection parts 40 on the display panel is in a gradient form in the first direction Y, thereby weakening the boundary line of the display brightness in the first direction Y, and thus improving the brightness uniformity of the display panel. Or by setting the orthographic projection area of each of the first connection parts 40 on the substrate 10 to be the same, improving the regularity of the distribution of the first connection parts 40, so that the emission brightness of the sub-pixels 20 corresponding to the first connection parts 40 has regularity, thereby improving the overall brightness uniformity of the display panel. In the embodiment of the present application, by improving the arrangement regularity of the first connection parts 40 on the display panel, when the pixel circuit drives the sub-pixels 20 to emit light, the uniformity of the display of the sub-pixels 20 can be improved, thereby improving the overall display effect of the display panel.

[0049] In some embodiments, when the area of each first connection portion 40 arranged along the first direction Y increases in sequence, the widths of each first connection portion 40 are the same, and the lengths of each first connection portion 40 increase in sequence along the first direction Y. In the embodiments of the present application, the first direction Y may be the vertical direction, that is, the length direction of the first connection portion 40. Correspondingly, the second direction Y may be the horizontal direction, that is, the width direction of the first connection portion 40. Due to the space of the display panel, when the first connection portion 40 forms a connection trace, the line width will be controlled within a certain range, requiring relatively high manufacturing precision, and problems such as short circuits are likely to occur during the manufacturing process. For example, the width range of the first connection portion 40 is 0.5-10 mm. Therefore, on the basis that the widths of the first connection portions 40 are the same, the lengths of each first connection portion 40 are set to increase in sequence along the first direction Y, that is, the lengths of the first connection portions 40 are set to change regularly, so as to prevent the brightness of the sub-pixels above different first connection portions 40 from being different due to the continuous reflection of light caused by different areas of the first connection portions 40 in the setting area of the first connection portions 40, resulting in an obvious mutation in the display brightness of a certain row or a certain place. That is, by controlling the density of the distribution of the first connection portions 40, the display area where the first connection portions 40 are located plays a role in the display effect transition, so as to weaken the problem of uneven display caused by the setting of the first connection portions 40.

[0050] In some embodiments, at least another part of the plurality of first connection portions 40 is arranged along the second direction X. The orthographic projection areas of each first connection portion 40 arranged along the second direction X on the substrate 10 are the same. The first direction Y and the second direction X intersect. Along the second direction X, adjacent first connection portions 40 are arranged at intervals. The plurality of first connection portions 40 are arranged in an array. The first connection portions 40 are arranged in rows along the second direction X and in columns along the first direction Y. In the embodiments of the present application, by setting the areas of the first connection portions 40 along the second direction X to be the same, the brightness difference of the sub-pixels 20 in the same row due to the area difference of the first connection portions 40 is avoided, and the luminous brightness uniformity of the sub-pixels 20 corresponding to the first connection portions 40 in the same row is improved, so that the display uniformity of each sub-pixel 20 in the same row can be improved.

[0051] Among them, the first direction Y and the second direction X intersect. The first direction Y and the second direction X can be set to be parallel to the same display plane of the display panel. Specifically, in this embodiment, the first direction Y and the second direction X can be perpendicular to each other. When the first direction Y is the vertical direction, the second direction X can be the horizontal direction. It should be noted that parallel means that the angle formed by two straight lines is more than -10° and less than 10°. Therefore, it also includes the state where the angle is more than -5° and less than 5°. In addition, "perpendicular" means that the angle formed by two straight lines is more than 80° and less than 100°. Therefore, it also includes the state of the angle more than 85° and less than 95°.

[0052] In some embodiments, as Figure 5 shown, the display panel includes a first display area 101 and a fan-out area 103. Among them, the fan-out area 103 coincides with the first display area 101, that is, the first display area 101 includes the fan-out area 103. The first connection part 40 is located in the first display area 101, that is, the first connection part 40 is also located in the fan-out area 103.

[0053] Among them, the first display area 101 is the area where the display panel actually displays images. The fan-out area 103 refers to the area where multiple data lines of the display panel converge in a fan shape. One end of the fan-out area 103 is electrically connected to multiple data lines of the display panel, and the other end is electrically connected to the gate driving circuit to enable the gate driving circuit to achieve progressive scanning driving. Generally, the fan-out area 103 is located in the non-display area of the display panel, which is not conducive to the realization of the narrow border or borderless of the display panel. When the fan-out area 103 coincides with the first display area 101 (Fanout in AA, FIAA), that is, along the thickness direction of the display panel, the fan-out area 103 is located below the first display area 101, so that the fan-out area 103 can be reused as the area for displaying images. Exemplarily, the fan-out area 103 can be arranged on the same layer as the gate driving circuit, or can be arranged on a different layer from the gate driving circuit, as long as the fan-out area 103 is located below the first display area 101, and no specific limitation is made. By setting the fan-out area 103 to coincide with the first display area 101, the non-display area of the display panel can be further reduced or eliminated, which is conducive to the realization of the narrow border or borderless of the display panel. At the same time, it is also conducive to improving the horizontal visual display unevenness phenomenon caused by the irregular routing of the first connection part 40 during the display of the fan-out area 103 in the off-screen and on-screen states.

[0054] Among them, the shape of the first display area 101 can be various. Exemplarily, the first display area 101 can be rectangular, such as a rounded rectangle, and the first display area 101 can also be circular or oval. Of course, the first display area 101 can also be other shapes such as rectangular, semi-circular, and pentagonal. No specific limitation is made in this embodiment.

[0055] In some embodiments, in combination with Figure 7 and Figure 8 As shown, the display panel further includes a second display area 102, and the first display area 101 and the second display area 102 are arranged adjacent to each other. The first connection portion 40 is also located within the second display area 102, and the area of each first connection portion 40 in the first display area 101 is the same as the area of each first connection portion 40 in the second display area 102. Among them, regardless of whether the first connection portion 40 is located in the first display area 101 or in the second display area 102, the areas of all the first connection portions 40 are the same. Exemplarily, taking the first connection portion 40 located in the first display area 101 as an example, the length and width of each first connection portion 40 are the same. By setting the areas of each first connection portion 40 located in the first display area 101 and the second display area 102 to be the same, the brightness difference between different first connection portions 40 is reduced, so that the brightness in the direction from the second display area 102 to the first display area 101 of the display panel is the same, weakening the boundary line between the first display area 101 and the second display area 102, preventing the display effect from showing an obvious mutation, and further improving the arrangement regularity of the first connection portion 40 in the second display area 102, so that when the pixel circuit drives the sub-pixel 20 to emit light, the uniformity of the sub-pixels 20 displayed in the second display area 102 can be improved, and further the display uniformity of the first display area 101 and the second display area 102 in the display panel can be improved, which is beneficial to further improving the overall display effect of the display panel.

[0056] Among them, the second display area 102 is the area where the actual display image is located on the display panel. Relative to the first display area 101, the second display area 102 is a conventional display area, that is, the second display area 102 does not coincide with the fan-out area 103. Specifically, the first display area 101 can be located at the exact middle position at the top of the display panel. The second display area 102 can surround the first display area 101 on all sides. However, this embodiment is not limited thereto. Exemplarily, the first display area 101 can be located at the upper left corner or the upper right corner of the display panel or other positions, or the second display area 102 can surround at least one side of the first display area 101. Among them, the shape of the second display area 102 can be various. Exemplarily, the second display area 102 can be a rectangle, such as a rounded rectangle, and the second display area 102 can also be a circle or an ellipse. Of course, the second display area 102 can also be other shapes such as a rectangle, a semi-circle, and a pentagon. This embodiment does not make specific limitations on this.

[0057] In some embodiments, please refer to Figure 6, the display panel further includes a plurality of second connection portions 50. Each second connection portion 50 is connected between a pixel electrode 31 and a first connection portion 40. Among them, the second connection portion 50 can be used to connect voltage signal traces VDD, data traces Data, etc., so as to increase the number of connections between the driving transistor 21 and the driving connection traces, thereby enhancing the display driving ability of the display panel.

[0058] In some embodiments, the first connection portion 40 and the second connection portion 50 are made of a transparent conductive material. Specifically, both the first connection portion 40 and the second connection portion 50 can be formed by any one or several of indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO). Since the grating effect of the transparent conductive material is small, by making the first connection portion 40 and the second connection portion 50 also made of the transparent conductive material, the grating effect of the metal for making the first connection portion 40 and the second connection portion 50 can be effectively reduced, which is beneficial to further improving the display effect of the display panel.

[0059] In some embodiments, please continue to refer to Figure 6 , the driving transistor 21 includes an active layer 211, a gate layer 212, and a source-drain layer 213. Among them, the active layer 211 is disposed on one side of the substrate 10, the gate layer 212 is disposed on the active layer 211, and the source-drain layer 213 is disposed on the gate layer 212.

[0060] The display panel further includes a first via 401 and a second via 402. Each first connection portion 40 is connected to a source-drain layer 213 through the first via 401 and is connected to a pixel electrode 31 through the second via 402.

[0061] In some embodiments, as Figure 6 shown, the driving transistor 21 further includes a first planarization layer 215, a second planarization layer 216, and a third planarization layer 217.

[0062] The first planarization layer 215 is disposed on the source-drain layer 213. The first connection portion 40 is disposed on the first planarization layer 215. The first planarization layer 215 is provided with a first via 401, and the source-drain layer 213 is exposed in the first via 401. The first connection portion 40 is electrically connected to the source-drain layer 213 through the first via 401.

[0063] The second flat layer 216 is disposed on the first connection portion 40, the second connection portion 50 is disposed on the second flat layer 216, the second flat layer 216 is provided with a second via hole 402, the first connection portion 40 is exposed in the second via hole 402, and the second connection portion 50 is electrically connected to the first connection portion 40 through the second via hole 402.

[0064] The third flat layer 217 is disposed on the second connection portion 50, the pixel electrode 31 is disposed on the second flat layer 216, the third flat layer 217 is provided with a third via hole 403, the second connection portion 50 is exposed in the third via hole 403, and the pixel electrode 31 is electrically connected to the second connection portion 50 through the third via hole 403.

[0065] In some embodiments, the orthographic projections of the first via hole 401 and the second via hole 402 on the substrate 10 may be spaced apart, or the orthographic projections of the first via hole 401 and the second via hole 402 on the substrate 10 may also be adjacent. Among them, the length of the distance between the first via hole 401 and the second via hole 402 on the substrate 10 will also affect the length of the second connection portion 50. Specifically, the longer the distance between the first via hole 401 and the second via hole 402 on the substrate 10, the longer the routing length of the second connection portion 50, and the shorter the distance between the first via hole 401 and the second via hole 402 on the substrate 10, the shorter the routing length of the second connection portion 50.

[0066] Combined Figure 2 and Figure 6 As shown, when the orthographic projections of the first via hole 401 and the second via hole 402 on the substrate 10 are spaced apart, since the first connection portion 40 is located in the first display area 101, specifically, the first connection portion 40 is located in the fan-out area 103, and the orthographic projection area of the first connection portion 40 along the first direction Y on the substrate 10 increases in sequence. By spacing the first via hole 401 and the second via hole 402 apart, the routing of the second connection portion 50 can have a certain length, so that the normal connection between the second connection portion 50 and signal lines such as the voltage signal line VDD can be ensured, and thus the normal display function of the fan-out area 103 can be ensured.

[0067] Combined Figure 8 and Figure 6As shown, when the orthographic projections of the first vias 401 and the second vias 402 on the substrate 10 are adjacent, since the first connection portions 40 are simultaneously located within the first display region 101 and the second display region 102, and the area of each first connection portion 40 within the first display region 101 is the same as the area of each first connection portion 40 within the second display region 102. By arranging the first vias 401 and the second vias 402 adjacent to each other, one end of the first connection portion 40 can be electrically connected to other film layers such as the first connection portion 40 and the source-drain layer 213, and the other end of the first connection portion 40 is connected to signal traces such as the voltage signal trace VDD. Thus, while ensuring that the first connection portion 40 realizes the connection function, the structures of the first vias 401 and the second vias 402 are compact within the region of the sub-pixel 20, which is beneficial to further improving the utilization rate of the area of the sub-pixel 20, beneficial to increasing the accommodating space for the first connection portion 40, and the first connection portion 40 can form a larger projected area on the substrate 10, facilitating the formation of the first connection portion 40 in the process.

[0068] In some embodiments, as Figure 6 shown, the driving transistor 21 further includes a bridging layer 214. The bridging layer 214 is disposed between the source-drain layer 213 and the first connection portion 40. One end of the bridging layer 214 is connected to the first connection portion 40, and the other end is connected to the source or drain in the source-drain layer 213. Among them, the material of the bridging layer 214 can be the same as the material of the source-drain layer 213, and the bridging layer 214 can be used to connect the voltage signal trace VDD, thereby increasing the number of connections between the driving transistor 21 and the signal trace VDD, and thus enhancing the display driving ability.

[0069] It should be noted that in the display panel, film layers such as a light-emitting functional layer, a packaging layer, a touch layer, a polarizing layer, and a cover plate can also be provided on the pixel electrode 31.

[0070] The present application also provides a display device, which includes a display panel. In the display device according to the embodiment of the present application, the first connection portion 40 of the display panel is used to connect the driving transistor 21 and the pixel electrode 31, and is also used to connect the signal trace. By setting the orthographic projection area of the first connection portion 40 along the first direction Y on the substrate 10 to increase successively, it is possible to avoid too large an area difference between different first connection portions 40, so that in the first direction Y of the display panel, the emission brightness of the sub-pixels 20 corresponding to the first connection portion 40 shows a gradient form, thereby weakening the boundary line of the display brightness in the first direction Y, and thus improving the brightness uniformity of the display panel. Or by setting the orthographic projection area of each first connection portion 40 on the substrate 10 to be the same, the regularity of the distribution of the first connection portion 40 is improved, so that the emission brightness of the sub-pixels 20 corresponding to the first connection portion 40 is uniform, thereby improving the brightness uniformity of the display panel. In the embodiment of the present application, by improving the arrangement regularity of the first connection portion 40 on the display panel, when the pixel circuit drives the sub-pixels 20 to emit light, the uniformity of the display of the sub-pixels 20 can be improved, and thus the overall display effect of the display panel can be improved. Since the display device has the above display panel, it has all the same beneficial effects, and thus will not be elaborated herein again.

[0071] In the embodiment of the present application, there is no specific limitation on the application of the display device, and it may be any product or component with a display function, such as a television, a notebook computer, a tablet computer, a wearable display device (such as a smart bracelet, a smart watch, etc.), a mobile phone, a virtual reality device, an augmented reality device, an in-vehicle display, an advertising light box, etc.

[0072] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0073] In specific implementation, the above-mentioned respective units or structures may be implemented as independent entities, or may be combined arbitrarily to be implemented as the same or several entities. For the specific implementation of the above-mentioned respective units or structures, reference may be made to the method embodiments described above, and thus will not be elaborated herein again.

[0074] The above has introduced in detail a display panel and a display device provided by the embodiments of the present application. Specific examples are used herein to elaborate the principles and implementation manners of the embodiments of the present application. The description of the above embodiments is only used to help understand the technical solutions and their core ideas of the embodiments of the present application; those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing respective embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the respective embodiments of the present application.

Claims

1. A display panel, characterized in that, Comprising: A substrate; Sub-pixels, which are arranged in an array on the substrate. Each sub-pixel includes a pixel circuit and a light-emitting element. The pixel circuit is used to drive the light-emitting element. The pixel circuit includes a driving transistor, and the light-emitting element includes a pixel electrode; A plurality of first connection parts, at least a part of the plurality of first connection parts are arranged at intervals along a first direction. Each pixel electrode is connected to a driving transistor through the first connection part. The first connection part is also used to connect a signal trace. The area of each first connection part arranged along the first direction increases in sequence. The area is the orthographic projection area of the first connection part on the substrate.

2. The display panel according to claim 1, characterized in that, When the area of each first connection part arranged along the first direction increases in sequence, the width of each first connection part is the same, and the length of each first connection part increases in sequence along the first direction.

3. The display panel according to claim 1, characterized in that, The display panel includes a first display area and a fan-out area. The fan-out area coincides with the first display area, and the first connection part is located in the first display area.

4. The display panel according to claim 3, characterized in that, The display panel further includes a second display area. The first display area and the second display area are arranged adjacent to each other. The first connection part is also located in the second display area. The area of each first connection part in the first display area is the same as the area of each first connection part in the second display area.

5. The display panel according to any one of claims 1-4, characterized in that, The driving transistor includes: An active layer, which is arranged on one side of the substrate; A gate layer, which is arranged on the active layer; A source-drain layer, which is arranged on the gate layer; The display panel further includes a first via hole and a second via hole. Each first connection part is connected to a source-drain layer through the first via hole and is connected to a pixel electrode through the second via hole.

6. The display panel according to claim 5, characterized in that, The display panel further includes: A plurality of second connection parts. Each second connection part is connected between a pixel electrode and a first connection part. The first connection part and the second connection part are made of a transparent conductive material.

7. The display panel according to claim 6, characterized in that, The orthographic projections of the first via hole and the second via hole on the substrate are arranged adjacent to each other, or the orthographic projections of the first via hole and the second via hole on the substrate are arranged at intervals.

8. The display panel according to claim 6, characterized in that, The driving transistor further includes: A first planarization layer, which is arranged on the source-drain layer. The first connection part is arranged on the first planarization layer. The first planarization layer is provided with the first via hole, and the source-drain layer is exposed in the first via hole. The first connection part is electrically connected to the source-drain layer through the first via hole; A second planarization layer, which is arranged on the first connection part. The second connection part is arranged on the second planarization layer. The second planarization layer is provided with a second via hole, and the first connection part is exposed in the second via hole. The second connection part is electrically connected to the first connection part through the second via hole.

9. The display panel according to claim 5, characterized in that, The driving transistor further includes: A bridging layer, which is arranged between the source-drain layer and the first connection part. One end of the bridging layer is connected to the first connection part, and the other end is connected to the source or drain in the source-drain layer.

10. A display device, characterized in that, Including the display panel according to any one of claims 1-9.

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