Cold source transistor device and method of making the same

Abstract

The present disclosure provides a cold source transistor device, comprising: a substrate layer; a cold source layer, the cold source layer is arranged on the substrate layer; a strip layer, the strip layer is connected with the cold source layer and is prepared by the same material; a gate dielectric layer, part of the gate dielectric layer is formed on part of the cold source layer, and part of the gate dielectric layer covers part of the strip layer; a gate electrode, the gate electrode is arranged on the gate dielectric layer; wherein, the interface of the cold source layer and the strip layer is formed as a homojunction, and the gate dielectric layer covers the homojunction. The present disclosure also provides a preparation method of the cold source transistor device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a cold-source transistor device and a preparation method thereof, and belongs to the technical field of integrated circuit components. BACKGROUND

[0002] The integrated circuit industry based on silicon-based CMOS (metal-oxide-semiconductor) technology is constantly pursuing high performance, low power consumption and high integration. However, when the device feature size is reduced to 5 nm technology node and below, the performance improvement brought by the size reduction of silicon-based CMOS is far less than the increasing power consumption, so the development trend of integrated circuits gradually changes from pursuing performance and integration improvement to reducing power consumption, and the most effective method to reduce dynamic power consumption is to reduce the operating voltage.

[0003] The most effective method to reduce the operating voltage is to reduce the subthreshold swing (SS), that is, the increment of the gate voltage required for the change of one order of magnitude of the leakage current. The electronic state density of the source material of the silicon-based field effect transistor varies with energy as an increasing function. According to the thermal emission theory, the theoretical limit of the SS of the silicon-based field effect transistor at room temperature is 60 mV / dec, and the integrated circuit requires the transistor to be rapidly turned off from a very high on-state current (such as 1 mA / um) to a very low off-state current (such as 10 nA / um) within the operating voltage (V DD ) range, so the minimum operating voltage is 0.64 V. The International Roadmap for Devices and Systems (IRDS) predicts that by 2034, the CMOS operating voltage will drop to 0.55 V. In order to meet this standard, new materials and new principle devices need to be developed.

[0004] Currently, there are three types of devices that can achieve SS less than 60 mV / dec at room temperature: tunneling transistors, negative capacitance transistors, and cold-source transistors. In the tunneling transistor, the tunneling coefficient is very sensitive to the change of the tunneling junction width (regulated by the gate voltage), so SS less than 60 mV / dec at room temperature can be achieved; however, the tunneling coefficient of the tunneling transistor at the on-state is difficult to approach 1, so the on-state current of the device is extremely low, and the performance is poor, I 60It is difficult to achieve 1uA / um for (SS = 60 mV / dec of source-drain current). The negative capacitance transistor realizes the amplification of the electrical signal by controlling the ferroelectric layer to flip through the gate voltage, so as to realize the characteristic of less than 60 mV / dec, but it is difficult to simultaneously do well in the on-state and hysteresis, and the speed of the ferroelectric layer flip limits its application in the high frequency field; in addition, the flip process of the ferroelectric layer needs energy supply, so the total power consumption of the negative capacitance transistor does not decrease significantly. In the cold source transistor, the state density of the source material decreases with the increase of energy, so that the carrier concentration at the Fermi level decays faster than the Fermi distribution, and the number of high-energy carriers injected into the channel through the channel barrier is reduced, so that the drain current is sharply reduced, and therefore the SS can be less than 60 mV / dec at room temperature.

[0005] The SS of the cold source transistor based on the graphene source-single carbon nanotube channel can achieve 40 mV / dec, and the sub-60 characteristic can span 4 orders of magnitude, I 60 40 , and the working voltage can be reduced to 0.5 V; if the channel material is replaced by a carbon nanotube array, the device performance can theoretically reach the standard of IRDS. However, the graphene cold source and the carbon nanotube (or MoS2 and other two-dimensional semiconductor materials) channel transistor needs to transfer the channel material to the graphene during production, and the process is complex, the controllability is poor, and it is difficult to form an ideal contact interface between the cold source and the channel material, which results in high contact barrier and poor SS of the transistor. SUMMARY

[0006] To solve one of the above technical problems, the present disclosure provides a cold source transistor device and a preparation method thereof.

[0007] According to one aspect of the present disclosure, a cold source transistor device is provided, which comprises:

[0008] a substrate layer,

[0009] a cold source layer disposed on the substrate layer;

[0010] a strip layer connected with the cold source layer and prepared by the same material;

[0011] a gate dielectric layer, part of the gate dielectric layer is formed on part of the cold source layer, and part of the gate dielectric layer covers part of the strip layer;

[0012] a gate electrode disposed on the gate dielectric layer;

[0013] wherein the interface of the cold source layer and the strip layer is formed as a homojunction, and the gate dielectric layer covers the homojunction.

[0014] According to the cold source transistor device of at least one embodiment of the present disclosure, the material of the cold source layer and the strip layer is selected to be an N-type doped two-dimensional cold source material or a P-type doped two-dimensional cold source material.

[0015] According to the cold source transistor device of at least one embodiment of the present disclosure, the cold source layer and the strip layer are further provided with:

[0016] a first electrode, a portion of the first electrode is disposed on the substrate layer, a portion of the first electrode is disposed on the cold source layer, and the first electrode is electrically conductive with the cold source layer; and

[0017] a second electrode, a portion of the second electrode is disposed on the substrate layer, a portion of the second electrode is disposed on the strip layer, and the second electrode is electrically conductive with the strip layer.

[0018] According to the cold source transistor device of at least one embodiment of the present disclosure, the first electrode and the second electrode have a predetermined interval, and most of the area of the cold source layer and most of the area of the strip layer are located in the area between the first electrode and the second electrode.

[0019] According to the cold source transistor device of at least one embodiment of the present disclosure, the first electrode and the gate dielectric layer have a predetermined interval.

[0020] According to the cold source transistor device of at least one embodiment of the present disclosure, the gate dielectric layer covers at least part of the sidewall of the second electrode and / or covers at least part of the upper surface of the second electrode.

[0021] According to the cold source transistor device of at least one embodiment of the present disclosure, the connection direction of the cold source layer and the strip layer is the length direction of the cold source layer and the strip layer, and the cold source layer and the strip layer have the same length or substantially the same length.

[0022] According to the cold source transistor device of at least one embodiment of the present disclosure, along the width direction of the cold source layer and the strip layer, the gate dielectric layer extends beyond both ends of the strip layer, and the width of the gate dielectric layer is greater than the width of the strip layer and the cold source layer.

[0023] According to the cold source transistor device of at least one embodiment of the present disclosure, the two-dimensional cold source material includes: graphene, Cd3C2, T-VTe2, H-VTe2, and H-TaTe2.

[0024] According to another aspect of the present disclosure, a preparation method of a cold source transistor device is provided, which comprises:

[0025] preparing a substrate layer;

[0026] A two-dimensional cold source material is laid on the substrate layer, and a cold source layer and a strip layer are obtained through a patterning and etching process;

[0027] A first electrode is deposited on the substrate layer and the cold source layer, and a second electrode is deposited on the substrate layer and the strip layer;

[0028] A gate dielectric layer is formed on part of the substrate layer and part of the strip layer; and

[0029] A gate metal is grown on the gate dielectric layer, thereby forming a gate electrode.

[0030] The preparation method of the cold source transistor device according to at least one embodiment of the present disclosure defines the patterns of the cold source and the strip layer through a multiple exposure and a phase shift mask process, and realizes the patterning transfer through an etching process to obtain a semiconductor conductive channel with a certain band gap.

[0031] The preparation method of the cold source transistor device according to at least one embodiment of the present disclosure forms a gate dielectric layer through an ALD growth process, or deposits a metal Y or Al to form a gate dielectric layer through oxidation, and makes the gate dielectric layer spaced apart from the first electrode by a preset distance, and makes the gate dielectric layer cover at least part of the sidewall of the second electrode and / or cover at least part of the upper surface of the second electrode. BRIEF DESCRIPTION OF DRAWINGS

[0032] The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the general description of the disclosure given above, and the detailed description of the embodiments below, serve to explain the principles of the present disclosure.

[0033] Figure 1 and Figure 2 is a schematic diagram of the overall structure of a cold source transistor device according to one embodiment of the present disclosure.

[0034] Figure 3 is a schematic diagram of the structure-band correspondence of an NMOS transistor according to one embodiment of the present disclosure.

[0035] Figure 4 is a schematic diagram of the sub-threshold region band of an NMOS transistor according to one embodiment of the present disclosure

[0036] Figure 5 is a schematic diagram of the band of an NMOS transistor in an open state according to one embodiment of the present disclosure.

[0037] Figure 6 is a comparison diagram of the transfer characteristics of a cold source transistor and a conventional transistor according to one embodiment of the present disclosure.

[0038] Figure 7 is a flow chart of a method of preparing a cold source transistor device according to an embodiment of the present disclosure.

[0039] Specifically, the reference signs in the drawings are as follows:

[0040] 100 cold source transistor device

[0041] 110 substrate layer

[0042] 120 cold source layer

[0043] 130 strip layer

[0044] 140 first electrode

[0045] 150 second electrode

[0046] 160 gate dielectric layer

[0047] 170 gate electrode. DETAILED DESCRIPTION

[0048] The present disclosure will be described in further detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only intended to explain the related content, and not to limit the present disclosure. In addition, it should be noted that only parts related to the present disclosure are shown in the drawings for ease of description.

[0049] It should be noted that the embodiments and features in the embodiments of the present disclosure can be combined with each other without conflict. The technical solutions of the present disclosure will be described in detail below with reference to the drawings and in combination with the embodiments.

[0050] Unless otherwise specified, the exemplary embodiments / examples shown will be understood to provide exemplary features of various details that can implement the technical concepts of the present disclosure in practice. Therefore, unless otherwise specified, the features of various embodiments / examples can be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of the present disclosure.

[0051] The use of cross-hatching and / or shading in the drawings is generally used to illustrate the boundaries and / or transitions between adjacent portions of a part. As such, unless specified, the presence or absence of cross-hatching and / or shading is not intended to convey or imply any preference or requirement for specific material, material properties, dimensions, proportions, commonality of the illustrated parts, and / or any other characteristic, attribute, property, etc. of the parts. Moreover, in the drawings, the size and relative sizes of parts can be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be practiced differently, a specific sequence of processes can be performed in a different order than described. For example, two consecutively described processes can be performed substantially simultaneously or in the opposite order to that described. Furthermore, like reference numerals can denote like parts throughout the description.

[0052] When a part is referred to as being "on" or "over" another part, "connected to" or "coupled to" another part, it can be directly on, directly connected to, or directly coupled to the other part, or intervening parts can be present. However, when a part is referred to as being "directly on", "directly connected to", or "directly coupled to" another part, there are no intervening parts. In this regard, the term "connected" can mean physical, electrical, and / or the like, with or without intervening parts.

[0053] For descriptive purposes, the disclosure can use spatial or relative terms, such as "below", "lower", "lowermost", "above", "upper", "uppermost", "over", "on", "side" (e.g., as in "side wall") to describe the relationship between one part and another as illustrated in the figures. The spatial and / or relative terms can be used to describe the orientation of the device in use, operation, and / or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, the part described as "below" or "under" the other part would then be oriented "above" the other part. Therefore, the exemplary term "below" can encompass both the "above" and "below" orientations. Moreover, the device can be oriented in further positions (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptions used herein interpreted accordingly.

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "comprise," "include," "contain," and / or "comprising," "including," and / or "contain" are used in the detailed description and / or claims, such terms are intended to be inclusive in a manner similar to the term "comprise" as an open transition such that they are intended to mean that anything also can be added. It is also noted that the terms "substantially," "approximately," and other similar terms, where used herein, are used in a non-limiting sense and are intended to allow for variations in measurement values, calculations, and / or provided values that would be appreciated by one of ordinary skill in the art.

[0055] Reference is made to Figures 1 to 7 A cold source transistor device and a method of manufacturing the same are described in detail.

[0056] Figure 1 And Figure 2 is a schematic diagram of the overall structure of a cold source transistor device according to an embodiment of the present disclosure.

[0057] Reference is made to Figures 1 to 2 According to an embodiment of the present disclosure, the cold source transistor device 100 of the present disclosure comprises a substrate layer 110, a cold source layer 120, a strip layer 130, a gate dielectric layer 160, and a gate electrode 170.

[0058] In the present disclosure, the substrate layer 110 can be a silicon wafer covered with silicon dioxide, of course, the substrate layer 110 can also be made of glass, quartz, ITO, etc., or flexible PI, PET, etc.

[0059] According to an embodiment of the present disclosure, the cold source layer 120 of the cold source transistor device 100 of the present disclosure is disposed on the substrate layer 110, wherein the cold source layer 120 is made of a two-dimensional cold source material, wherein the two-dimensional cold source material is a cold source material with a carrier state density window that decreases with increasing energy; for example, graphene and the like.

[0060] According to a preferred embodiment of the present disclosure, the strip layer 130 of the cold source transistor device 100 of the present disclosure is disposed on the substrate layer 110, and the strip layer 130 is connected with the cold source layer 120, wherein the strip layer 130 is made of the same two-dimensional cold source material as the cold source layer 120.

[0061] Those skilled in the art should understand that the cold source layer 120 and the strip layer 130 are prepared by using the same material, and the two-dimensional cold source material described above is preferably used in the present disclosure, and other materials can also be used to meet the use requirements, which all fall within the protection scope of the present disclosure.

[0062] Preferably, the cold source layer 120 and the strip layer 130 use the same material, which can not only reduce the process difficulty, but also eliminate the problem of the "contact interface", so that the performance of the cold source transistor device 100 can be further improved.

[0063] Preferably, the cold source layer 120 and the strip layer 130 of the present disclosure use N-type doped two-dimensional cold source material or P-type doped two-dimensional cold source material. Among them, the cold source transistor device 100 is an NMOS transistor device, and the P-type doped two-dimensional cold source material is used; the cold source transistor device 100 is a PMOS transistor device, and the N-type doped two-dimensional cold source material is used.

[0064] According to the preferred embodiment of the present disclosure, the cold source transistor device 100 of the present disclosure takes graphene, a two-dimensional cold source material without band gap, as an example: based on the same piece of graphene, one side is set as the cold source layer 120, and the other side is set as a semiconductor conductive channel with a band gap by etching, that is, the strip layer 130, so that the cold source transistor device 100 has high performance and low power consumption.

[0065] Those skilled in the art should understand that according to the confinement effect, the phenomenon of the two-dimensional cold source material nanometer strip generating a band gap is generally present, and therefore, the present disclosure can also use other two-dimensional cold source materials, such as: cadmium carbide (Cd3C2), octahedral vanadium telluride (T-VTe2), prism-shaped vanadium telluride (H-VTe2), and prism-shaped tantalum telluride (H-TaTe2).

[0066] Reference Figure 1 According to the preferred embodiment of the present disclosure, the connection direction of the cold source layer 120 and the strip layer 130 of the present disclosure is the length direction of the cold source layer 120 and the strip layer 130, and the cold source layer 120 and the strip layer 130 have the same length or approximately the same length.

[0067] Preferably, the interface formed by the connection of the cold source layer 120 and the strip layer 130 of the cold source transistor device 100 of the present disclosure is a homojunction.

[0068] Reference Figure 1 and Figure 2 According to one embodiment of the present disclosure, the cold source transistor device 100 of the present disclosure further comprises a first electrode 140 and a second electrode 150.

[0069] The first electrode 140 is partially disposed on the substrate layer 110 and partially disposed on the cold source layer 120 so that the first electrode 140 and the cold source layer 120 can conduct electricity. More preferably, one end of the cold source layer 120 in the length direction is connected to the strip layer 130, and the first electrode 140 is disposed on the other end of the cold source layer 120 in the length direction.

[0070] More preferably, along the width direction of the cold source layer 120, both ends of the first electrode 140 extend beyond both ends of the cold source layer 120 in the width direction, so that the first electrode 140 can play a role in fixing the cold source layer 120.

[0071] The second electrode 150 is partially disposed on the substrate layer 110 and partially disposed on the strip layer 130 so that the second electrode 150 and the strip layer 130 can conduct electricity. More preferably, one end of the strip layer 130 in the length direction is connected to the cold source layer 120, and the second electrode 150 is disposed on the other end of the strip layer 130 in the length direction.

[0072] More preferably, along the width direction of the strip layer 130, both ends of the second electrode 150 extend beyond both ends of the strip layer 130 in the width direction, so that the second electrode 150 can play a role in fixing the strip layer 130.

[0073] Preferably, the first electrode 140 and the second electrode 150 have a predetermined interval so that most of the area of the cold source layer 120 and most of the area of the strip layer 130 are located in the area between the first electrode 140 and the second electrode 150.

[0074] Preferably, the electrode material of the first electrode 140 and / or the second electrode 150 should be selected as a metal with different work functions in the case of using different doped two-dimensional cold source materials for the cold source layer 120 and the strip layer 130. Specifically, when the cold source transistor device is NMOS, P-type doped graphene is used, and the first electrode and the second electrode are made of low work function metals such as Sc, Y, Al, or Ni; correspondingly, when the cold source transistor device is PMOS, N-type doped graphene is used, and the first electrode and the second electrode are made of high work function metals such as Pd, Au, or Pt.

[0075] Reference Figure 2According to one embodiment of the present disclosure, the gate dielectric layer 160 of the cold source transistor device 100 of the present disclosure is partially formed on part of the cold source layer 120, the gate dielectric layer 160 covers the homojunction formed by the connection of the cold source layer 120 and the strip layer 130, and there is a preset interval between the first electrode 140 and the gate dielectric layer 160, and part of the gate dielectric layer 160 covers part of the strip layer 130.

[0076] Specifically, the gate dielectric layer 160 covers at least part of the sidewall of the second electrode 150 and / or covers at least part of the upper surface of the second electrode 150, and along the width direction of the cold source layer 120 and the strip layer 130, the gate dielectric layer 160 extends beyond both ends of the strip layer 130, and the width of the gate dielectric layer 160 is greater than the width of the strip layer 130 and the cold source layer 120.

[0077] In a preferred embodiment, the cold source layer 120 and the strip layer 130 have the same or substantially the same width.

[0078] In the present disclosure, at least part of the cold source layer 120 is not covered by the first electrode 140 and the gate dielectric layer 160 in the length direction of the cold source layer 120. In one implementation form, the length of the cold source layer 120 not covered by the first electrode 140 and the gate dielectric layer 160 is greater than a first length value and less than a second length value. When the length of the cold source layer 120 not covered by the first electrode 140 and the gate dielectric layer 160 is less than or equal to the first length value, the electrons injected from the metal into the graphene do not have time to reach a steeper distribution, that is, when the length of the cold source layer 120 not covered by the first electrode 140 and the gate dielectric layer 160 is greater than the first length value, the electrons injected from the first electrode 140 into the cold source layer 120 reach a steady-state steep distribution. And when the length of the cold source layer 120 not covered by the first electrode 140 and the gate dielectric layer 160 is greater than or equal to the second length value, the carriers will be thermalized, thereby reducing the SS; that is, when the length of the cold source layer 120 not covered by the first electrode 140 and the gate dielectric layer 160 is less than or equal to the second length value, the carriers will not be significantly thermalized.

[0079] Reference Figure 3 According to one embodiment of the present disclosure, the gate electrode 170 of the cold source transistor device 100 of the present disclosure is arranged on the gate dielectric layer 160, and the projection of the gate electrode 170 on the plane where the cold source layer 120 and the strip layer 130 are located covers at least the strip layer 130 and part of the cold source layer 120, so as to be able to band control the strip layer 130 to realize the switching of the cold source transistor device 100 and enable Klein tunneling in the cold source layer 120 and the strip layer 130.

[0080] In the present disclosure, the first electrode 140 can be formed as a source electrode (source) of the cold source transistor device 100, and the second electrode 150 can be formed as a drain electrode (drain) of the cold source transistor device 100.

[0081] In the present disclosure, the strip layer 130 can include a plurality of parallel strips, wherein the strips can be nanometer strips, so that the strip layer 130 is formed as a nanometer strip array, that is, as a conductive channel of the cold source transistor device 100, and there is a gap between two adjacent strips. For example, when graphene material is confined in one dimension, a material without a band gap will have a band gap.

[0082] The strip layer 130, for example, graphene, is etched into strips to obtain a semiconductor conductive channel with a certain band gap (graphene is confined to less than 10 nm in one dimension, and its band gap is widened to more than 0.15 eV, and the smaller the confinement scale, the greater the band gap). Thus, the strip layer 130 and the cold source layer 120 can be prepared by the same material.

[0083] Reference Figure 4 and Figure 5 For example, the working principle of the cold source transistor device 100 using a two-dimensional cold source material graphene NMOS transistor is described.

[0084] According to one embodiment of the present disclosure, when the voltage V ds of the drain relative to the source is greater than 0 V, the electric field strength is directed from the drain to the source; when the voltage V gs of the gate relative to the source is positively increased to the vicinity of the graphene source Fermi level, the electrons can pass through the graphene nanometer strip without being blocked by the potential barrier, which corresponds to the on state of the cold source transistor device 100.

[0085] That is, the on state of the cold source transistor device 100 of the present disclosure is that the voltage of the second electrode 150 relative to the first electrode 140 is positively increased, so that the electrons in the vicinity of the Fermi level of the cold source layer 120 pass through the strip layer 130 without being blocked by the potential barrier, and the cold source transistor device 100 is turned on.

[0086] On the other hand, for example, when the voltage V gsFrom the gradual negative decrease of the on-state gate voltage, the valence band and the conduction band of the graphene nanobelt in the energy band diagram are gradually raised relative to the Fermi level, so that part of the electrons near the Fermi level of the graphene source need to overcome the potential barrier to enter the conduction band of the channel material through the channel. Since the electronic state density of the graphene source decreases with the increase of energy, the decay rate of the number distribution of electrons in the graphene source with the increase of energy is faster than the decay rate of the E exponential function, so in the subthreshold region, the barrier is raised by 60 meV (ideally) for every 60 mV decrease in gate voltage, and the number of electrons that can pass through the channel decays by more than an order of magnitude, so the source-drain current decays by more than an order of magnitude, and the transistor is quickly turned off.

[0087] That is, the off state of the cold source transistor device 100 of the present disclosure is that the voltage of the gate electrode relative to the first electrode 140 is negatively decreased from the gate voltage in the on state of the cold source transistor device 100, so that the valence band and the conduction band of the belt layer 130 are raised relative to the Fermi level, part of the electrons near the Fermi level of the cold source layer 120 overcome the potential barrier to pass through the belt layer 130, and the number of electrons that can pass through the belt layer 130 decays by more than an order of magnitude, so that the current between the first electrode 140 and the second electrode 150 decays by more than an order of magnitude, and the cold source transistor device 100 is turned off.

[0088] The working principle of the PMOS transistor with graphene as the two-dimensional cold source material is the same as that of the NMOS transistor, which will not be described here.

[0089] The cold source transistor device 100 of the present disclosure can achieve a subthreshold slope SS < 60 mV / dec at room temperature, and make its working voltage less than the limit voltage 0.64 V of the conventional silicon transistor. And because there is a homojunction in the cold source transistor device 100, its performance is better than that of the cold source transistor based on a heterojunction.

[0090] The cold source transistor device 100 of the present disclosure uses the gate electrode to control the nanobelt array and part of the cold source layer adjacent to the belt, and obtains a subthreshold swing that breaks through the theoretical limit (60 mV / dec at room temperature), which is an ultra-low power consumption transistor. Because the homojunction is used between the cold source layer and the channel (nanobelt array), the transistor has a simpler process and better performance (smaller SS, smaller working voltage, larger on-state current, larger I 60 ) than the traditional Dirac source transistor using a heterojunction, and becomes a basic device of future high-energy-efficient (high-performance, ultra-low power consumption) integrated circuits.

[0091] Reference Figure 7 According to one embodiment of the present disclosure, the preparation method S100 of the cold source transistor device of the present disclosure includes the following steps:

[0092] S101, preparing a substrate layer 110;

[0093] S102, laying a two-dimensional cold source material on the substrate layer 110, and obtaining a cold source layer 120 and a strip layer 130 through a patterning and etching process; wherein, when forming the strip layer 130, a multiple photoetching and phase shift mask technology can also be used. In the present disclosure, if the graphene strip is to be opened to a sufficient band gap (a band gap of 0.1 eV corresponds to a width of 10 nm), the width of a single strip in the strip layer is at least less than 5 nm.

[0094] S103, depositing a first electrode 140 on the substrate layer 110 and the cold source layer 120, and depositing a second electrode 150 on the substrate layer 110 and the strip layer 130;

[0095] S104, forming a gate dielectric layer 160 on part of the substrate layer 110 and part of the strip layer 130;

[0096] S105, growing a gate metal on the gate dielectric layer 160 to form a gate electrode 170.

[0097] In step S102, preferably, the patterns of the cold source 120 and the strip layer 130 are defined through a multiple exposure and phase shift mask process, and the patterns are transferred through an etching process to obtain the cold source layer 120 and the strip layer 130, thereby obtaining a semiconductor conductive channel with a certain band gap.

[0098] In step S103, preferably, for an NMOS cold source transistor device, the first electrode 140 or the second electrode 150 uses a low work function metal such as Sc, Al, Y, Ni. For a PMOS cold source transistor device, the first electrode or the second electrode uses a high work function metal such as Pd, Pt, Au.

[0099] In step S104, preferably, the gate dielectric layer 160 is formed through an ALD growth process, and the gate dielectric layer 160 is spaced apart from the first electrode 140 by a predetermined distance, and the gate dielectric layer 160 covers at least part of the sidewall of the second electrode 150 and / or covers at least part of the upper surface of the second electrode 150.

[0100] Preferably, from the perspective of dielectric constant, a high dielectric constant material such as hafnium oxide can be selected as the gate dielectric layer to suppress short channel effect and gate leakage.

[0101] In the description of the specification, the description of the terms "one embodiment / way", "some embodiments / ways", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment / way or example are included in at least one embodiment / way or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment / way or example. Also, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments / ways or examples. In addition, the person skilled in the art can combine and combine the different embodiments / ways or examples described in the specification and the features of the different embodiments / ways or examples, without contradiction.

[0102] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0103] The person skilled in the art should understand that the above-mentioned embodiments are only for clearly illustrating the present disclosure, and are not intended to limit the scope of the present disclosure. Based on the above disclosure, other changes or modifications can also be made by those skilled in the art, and these changes or modifications are still within the scope of the present disclosure.

Claims

1. A cold-source transistor device, characterized in that, include: basal layer A cold source layer, wherein the cold source layer is disposed on the substrate layer; A strip layer, which is connected to the cold source layer and is made of the same material; A gate dielectric layer, a portion of which is formed on a portion of the cold source layer, and a portion of which covers a portion of the strip layer; A gate electrode, wherein the gate electrode is disposed on the gate dielectric layer; The interface connecting the cold source layer and the strip layer is formed as a homojunction, and the gate dielectric layer covers the homojunction. Wherein, the line connecting the cold source layer and the strip layer is the length direction of the cold source layer and the strip layer; The materials used to prepare the cold source layer and the strip layer are selected as N-type doped two-dimensional cold source materials or P-type doped two-dimensional cold source materials, including graphene, Cd3C2, T-VTe2, H-VTe2 and H-TaTe2.

2. The cold source transistor device as described in claim 1, characterized in that, Also includes: A first electrode, a portion of which is disposed on the substrate layer and a portion of which is disposed on the cold source layer, such that the first electrode and the cold source layer are electrically conductive; as well as The second electrode has a portion disposed on the substrate layer and a portion disposed on the strip layer, such that the second electrode and the strip layer are conductive.

3. The cold source transistor device as described in claim 2, characterized in that, There is a preset interval between the first electrode and the second electrode, wherein most of the cold source layer and most of the strip layer are located in the area between the first electrode and the second electrode.

4. The cold source transistor device as described in claim 2, characterized in that, There is a predetermined interval between the first electrode and the gate dielectric layer.

5. The cold source transistor device as described in claim 2, characterized in that, The gate dielectric layer covers at least a portion of the sidewall of the second electrode and / or at least a portion of the upper surface of the second electrode.

6. The cold source transistor device as described in claim 1, characterized in that, The cold source layer and the strip layer have approximately the same length.

7. The cold source transistor device as described in claim 6, characterized in that, Along the width direction of the cold source layer and the strip layer, the gate dielectric layer extends beyond both ends of the strip layer, such that the width of the gate dielectric layer is greater than the width of the strip layer and the cold source layer.

8. A method for fabricating a cold-source transistor device, characterized in that, include: Prepare the base layer; A two-dimensional cold source material is laid on the substrate layer, and a cold source layer and a strip layer are obtained through patterning and etching processes. A first electrode is deposited on the substrate layer and the cold source layer, and a second electrode is deposited on the substrate layer and the strip layer; A gate dielectric layer is formed on a portion of the substrate layer and a portion of the strip layer; as well as A gate metal is grown on the gate dielectric layer to form a gate electrode; Wherein, the line connecting the cold source layer and the strip layer is the length direction of the cold source layer and the strip layer; The materials used to prepare the cold source layer and the strip layer are selected as N-type doped two-dimensional cold source materials or P-type doped two-dimensional cold source materials, including graphene, Cd3C2, T-VTe2, H-VTe2 and H-TaTe2.

9. The method for fabricating the cold source transistor device as described in claim 8, characterized in that, The patterns of the cold source and strip layer are defined by multiple exposure and phase-shifting mask processes, and the patterned transfer is achieved by etching process to obtain the cold source layer and strip layer, thereby obtaining a semiconductor conductive channel with a certain band gap.

10. The method for fabricating the cold source transistor device as described in claim 9, characterized in that, The gate dielectric layer is formed by ALD growth process or by depositing metal Y or Al and oxidizing it to form the gate dielectric layer, such that the gate dielectric layer is spaced at a predetermined distance from the first electrode, and the gate dielectric layer covers at least a portion of the sidewall of the second electrode and / or covers at least a portion of the upper surface of the second electrode.

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