A circuit structure and method for improving performance of a DCDC chip

Abstract

This invention proposes a circuit structure and method to improve the performance of DC-DC chips. By setting a comparator and a charge pump after the power transistor, the circuit structure can provide a negative voltage to the gate of the power transistor when the source-drain voltage of the power transistor in the DC-DC chip is detected to be greater than a given threshold voltage. This reduces the on-resistance of the power transistor, thereby solving the problems of slow startup speed caused by excessive power transistor impedance during DC-DC chip startup and low load capacity caused by excessive power transistor impedance at low input voltage.

Description

Technical Field

[0001] This invention belongs to the field of switching power supply technology, specifically relating to a circuit structure and method for improving the performance of DC-DC chips. Background Technology

[0002] Currently, DC-DC chips are increasingly widely used. Their core competitiveness is determined by their performance in various aspects, such as load capacity, startup speed, and conversion efficiency, as well as the cost of their production. During startup, DC-DC chips often experience slow startup speeds and low conversion efficiency due to excessively high on-resistance of the power transistor. After startup, during normal operation, the high on-resistance of the power transistor results in low load capacity at low voltages. Reducing the on-resistance requires increasing the transistor's area, which increases the chip's production cost. Therefore, finding a way to reduce the on-resistance of the power transistor in a DC-DC chip without increasing its area is crucial. Summary of the Invention

[0003] The purpose of this invention is to provide a circuit structure and method for improving the performance of DC-DC chips, thereby solving the problems of slow startup speed, low low-voltage load capacity, and large power transistor area in the prior art.

[0004] To achieve the above objectives, the present invention employs the following technical solution:

[0005] A circuit structure for improving the performance of a DC-DC chip includes a power transistor, a comparator, and a charge pump;

[0006] The source and drain terminals of the power transistor are connected together to the comparator, the output terminal of the comparator is connected to the input terminal of the charge pump, and the output terminal of the charge pump is connected to the gate of the power transistor.

[0007] A further improvement of the present invention is that:

[0008] Preferably, the gate of the power transistor is connected to the output terminal of a level conversion circuit, and the input terminal of the level conversion circuit is connected to a driving circuit.

[0009] Preferably, the input terminal of the level conversion circuit is connected to the output terminal of the charge pump.

[0010] Preferably, the connection between the comparator and the power transistor is connected to the drain terminal of the switching transistor, the source terminal of the switching transistor is grounded, and the gate of the switching transistor is connected to the driving circuit.

[0011] Preferably, when the power transistor is a PMOS transistor, the charge pump is a negative charge pump; when the power transistor is an NMOS transistor, the charge pump is a positive charge pump.

[0012] A method for improving the performance of a DC-DC chip based on any of the circuit structures described above, wherein a comparator compares the source voltage and the drain voltage of a power transistor.

[0013] If the result of subtracting the threshold voltage from the drain voltage is greater than the source voltage, the comparator outputs a control signal to the charge pump. The charge pump outputs a voltage value according to the control signal, and the power transistor turns on according to the voltage value.

[0014] If the result of subtracting the threshold voltage from the drain voltage is less than the source voltage, the comparator outputs a control signal to the charge pump to stop the charge pump from generating voltage, and the charge pump outputs 0 voltage to the power transistor.

[0015] Preferably, the gate of the power transistor is connected to the output terminal of a level conversion circuit, and the input terminal of the level conversion circuit is connected to a driving circuit; the input terminal of the level conversion circuit is connected to the output terminal of the charge pump.

[0016] When the power transistor control signal PD output by the driver circuit is GND, the level conversion circuit outputs a low level to the gate of the power transistor; the comparator compares the source voltage and drain voltage of the power transistor; when the difference between the drain voltage and the source voltage of the power transistor is greater than the threshold voltage, the comparator outputs a high level to the charge pump, the charge pump generates a voltage and inputs it to the level conversion circuit, and the level conversion circuit inputs a low voltage to the gate of the power transistor; when the difference between the drain voltage and the source voltage of the power transistor is less than the threshold voltage, the comparator outputs a low level to the charge pump, the charge pump outputs a low level to the level conversion circuit, and the level conversion circuit outputs a low level to the gate of the power transistor.

[0017] Preferably, when the power transistor control signal PD output by the drive circuit is VCC, the level conversion circuit outputs a high level VCC, and the power transistor is turned off.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] This invention discloses a circuit structure for improving the performance of DC-DC chips. This structure, by placing a comparator and a charge pump after the power transistor, provides a voltage to the gate of the power transistor when the source-drain voltage of the power transistor in the DC-DC chip is detected to be greater than a given threshold voltage. This reduces the on-resistance of the power transistor, thereby solving problems such as slow startup speed due to excessive power transistor impedance during DC-DC chip startup and low load-carrying capacity at low input voltages due to excessive power transistor impedance. Furthermore, under the condition of equal power transistor on-resistance, the power transistor area required by this structure is much smaller than that of traditional structures. This structure can improve low-voltage load-carrying capacity and reduce the size of the power transistor.

[0020] The present invention also discloses a circuit method for improving the performance of a DC-DC chip. The method outputs different voltage values ​​based on the comparison results of the power transistor's far-end voltage and drain voltage, so that the power transistor operates according to different input voltage values, thereby reducing the on-resistance of the power transistor. Attached Figure Description

[0021] Figure 1 This is the schematic diagram of the core circuit of the present invention;

[0022] Figure 2 This is a circuit schematic diagram of an embodiment of the present invention.

[0023] Specifically: 1-Driver circuit; 2-Comparator; 3-Charge pump; 4-Level conversion circuit. Detailed Implementation

[0024] The present invention will now be described in further detail with reference to the accompanying drawings:

[0025] This invention discloses a circuit structure and method for improving the performance of DC-DC chips. See [link to relevant documentation]. Figure 1 The core structure of this structure includes a power transistor M1. The source and drain terminals of the power transistor M1 are both connected to a comparator 2. The output terminal of the comparator 2 is connected to a charge pump 3. The output terminal of the negative voltage charge pump 4 is connected to the gate of the power transistor M1.

[0026] Specifically, the power transistor is a PMOS transistor.

[0027] The working process corresponding to the above structure is as follows: When the circuit is working, the voltages across the source and drain terminals of power transistor M1 are compared by comparator 2. If the value obtained by subtracting the set threshold voltage from the drain voltage is greater than the source voltage, the comparator outputs a control signal to the charge pump circuit, enabling it to operate. The charge pump circuit is a negative voltage charge pump, and its output voltage should be a negative voltage value. This negative voltage value serves as the enable terminal of power transistor M1, controlling the power transistor to conduct. If the value obtained by subtracting the set threshold voltage from the drain voltage is less than the source voltage, the control signal output by the comparator controls the charge pump circuit to shut down, stopping voltage generation. At this time, the charge pump output voltage should be zero. This charge pump output voltage is sent to the gate of the power transistor to reduce the on-resistance of the power transistor. If it is not necessary to reduce the on-resistance of the power transistor, the comparator and charge pump circuit can be turned off using the enable signal to save chip power consumption.

[0028] If the DC-DC power transistor is an NMOS transistor, then a positive charge pump is used, and the working principle is the same as described above.

[0029] See Figure 2In one embodiment of this invention, a circuit structure for improving the performance of a DC-DC chip is used. This circuit structure includes a driver circuit 1, a level conversion circuit 4, a comparator 2, a negative charge pump 3, and a power transistor M2 and a switching transistor M3 for the DC-DC circuit. The circuit structure of this invention is mainly suitable for situations requiring reduced on-resistance. The power transistor M2 is a PMOS transistor.

[0030] The specific circuit connection is as follows: The PD signal generated by the driver circuit 1 serves as the input signal for the level conversion circuit 4. The high and low levels of the level conversion circuit 4 are connected to the power supply voltage VCC and the output voltage CP of the negative charge pump. The output terminal of the level conversion circuit is connected to the gate of the power transistor M2. The negative terminal of the comparator 2 circuit is connected to the source terminal of the power transistor, and the positive terminal of the comparator 2 circuit is connected to the drain terminal of the power transistor. Its output terminal serves as the enable control signal for the negative charge pump and is connected to the charge pump circuit. The high level of the charge pump circuit is connected to the power supply voltage (VCC), and the low level is connected to ground (GND). The negative voltage generated at its output terminal is connected to the low level CP of the level conversion circuit. The connection between the positive input terminal of comparator 2 and the drain terminal of the power transistor is also connected to the drain terminal of the switching transistor M3. The source terminal of the switching transistor M3 is grounded, and the ND signal generated by the driver circuit 1 is connected to the gate of the switching transistor M3.

[0031] The specific operation of the embodiment is as follows: When the power transistor control signal PD output by the driving circuit is GND, the power transistor M2 needs to be turned on. At this time, the level conversion circuit 4 outputs a low level, that is, the output voltage CP of the negative charge pump. There are two situations at this time. One is that the on-resistance of the power transistor M2 is large, that is, the difference between the drain voltage SW and the source voltage VOUT of M2 is greater than the set threshold voltage. At this time, the comparator 2 outputs a high level VCC, controlling the negative charge pump 3 to work. The negative charge pump 3 generates a negative voltage CP = -VCC. At this time, the output voltage of the level conversion circuit 4 is -VCC. This voltage is connected to the gate of the power transistor M2, reducing the on-resistance of M2. The other situation is that the on-resistance of M2 is small, that is, the difference between the drain voltage SW and the source voltage VOUT of M2 is less than the set threshold voltage. At this time, the comparator 2 outputs a low level GND, the negative charge pump stops generating negative voltage, and the output voltage CP of the negative charge pump is GND. At this time, the output voltage of the level conversion circuit is GND, and the gate voltage of the power transistor M2 is GND. There is no need to adjust the on-resistance of M2. When the power transistor control signal PD output by the drive circuit 1 is VCC, the power transistor M2 needs to be turned off. At this time, the level conversion circuit 4 outputs a high level VCC, and the gate-source voltage of the power transistor M2 is less than the threshold voltage of M2, so the power transistor M2 is turned off.

[0032] The driving circuit is used to output logic signals to control the power transistor M2 and the switching transistor M3 in the DC-DC chip to turn on and off.

[0033] The level conversion circuit converts the logic signal PD, which has high and low levels VCC and GND, into VCC and CP, and sends them to the gate of the power transistor as the control terminal of the power transistor.

[0034] The comparator circuit determines the voltage difference across the power transistor M2, compares this voltage difference with the threshold voltage generated by the comparator itself, and converts the comparison result into a logic signal. If the difference between the drain voltage and the source voltage of M2 is greater than the comparator threshold voltage, it outputs a high level VCC; otherwise, it outputs a low level GND. This level is then sent to the next stage circuit unit.

[0035] The negative voltage charge pump circuit utilizes the characteristics of a charge pump to generate a negative voltage less than zero during operation, and then transmits this voltage level to the next stage circuit unit. If the generation of voltage stops, the output voltage is zero.

[0036] The circuits involved in each module of this invention are all existing conventional circuit structures, which can achieve their respective functional requirements.

[0037] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A circuit structure for improving performance of a DCDC chip, characterized by, The power tube, the comparator (2) and the charge pump (3) are included; The source end and the drain end of the power tube are connected with the comparator (2) together, the output end of the comparator (2) is connected with the input end of the charge pump (3), and the output end of the charge pump (3) is connected with the gate of the power tube; The gate of the power tube is connected with the output end of the level conversion circuit (4), and the input end of the level conversion circuit (4) is connected with the driving circuit (1); When the power tube is a PMOS tube, the charge pump (3) is a negative voltage charge pump; when the power tube is an NMOS tube, the charge pump (3) is a positive voltage charge pump; The method for improving the performance of the DCDC chip through the above circuit structure is: The comparator (2) compares the source end voltage of the power tube with the drain end voltage of the power tube; If the result obtained by subtracting the threshold voltage from the drain end voltage is greater than the source end voltage, the comparator (2) outputs a control signal to the charge pump (3), the charge pump (3) outputs a voltage value according to the control signal, and the power tube is turned on according to the voltage value; If the result obtained by subtracting the threshold voltage from the drain end voltage is less than the source end voltage, the comparator (2) outputs a control signal to the charge pump (3) to make the charge pump (3) stop generating voltage, and the charge pump (3) outputs 0 voltage to the power tube; The gate of the power tube is connected with the output end of the level conversion circuit (4), and the input end of the level conversion circuit (4) is connected with the driving circuit (1); the input end of the level conversion circuit (4) is connected with the output end of the charge pump (3); When the power tube control signal PD output by the driving circuit (1) is GND, the level conversion circuit (4) outputs a low level to the gate of the power tube; the comparator (2) compares the source end voltage of the power tube with the drain end voltage; when the difference between the drain end voltage and the source end voltage of the power tube is greater than the threshold voltage, the comparator (2) outputs a high level to the charge pump (3), the charge pump (3) generates voltage and inputs to the level conversion circuit (4), and the level conversion circuit (4) inputs low voltage to the gate of the power tube; when the difference between the drain end voltage and the source end voltage of the power tube is less than the threshold voltage, the comparator (2) outputs a low level to the charge pump (3), the charge pump (3) outputs a low level to the level conversion circuit (4), and the level conversion circuit (4) outputs a low level to the gate of the power tube; The output end of the negative voltage charge pump (3) is connected to the low level power supply end of the level conversion circuit (4); When the difference between the drain end voltage and the source end voltage of the power tube is greater than a threshold voltage, the comparator (2) outputs a signal to make the negative voltage charge pump (3) work, so as to provide a negative voltage to the low level power supply end of the level conversion circuit (4); The input end of the level conversion circuit (4) is connected with the output end of the charge pump (3).

2. The circuit structure for improving performance of a DCDC chip according to claim 1, wherein, The connection part of the comparator (2) and the power tube is connected with the drain end of the switch tube, and the source end of the switch tube is grounded.

3. A method for improving the performance of a DCDC chip based on the circuit structure of any one of claims 1-2, characterized in that, The comparator (2) compares the source end voltage of the power tube with the drain end voltage of the power tube; If the result obtained by subtracting the threshold voltage from the drain end voltage is greater than the source end voltage, the comparator (2) outputs a control signal to the charge pump (3), the charge pump (3) outputs a voltage value according to the control signal, and the power tube is turned on according to the voltage value; If the result obtained by subtracting the threshold voltage from the drain end voltage is less than the source end voltage, the comparator (2) outputs a control signal to the charge pump (3) to make the charge pump (3) stop generating voltage, and the charge pump (3) outputs 0 voltage to the power tube; If the result of the drain voltage minus the threshold voltage is less than the source voltage, the comparator (2) outputs a control signal to the charge pump (3) to stop the charge pump (3) from generating a voltage, and the charge pump (3) outputs 0 voltage to the power tube.

4. The method of claim 3, wherein, The gate of the power tube is connected to the output of the level conversion circuit (4), and the input of the level conversion circuit (4) is connected to the driving circuit (1); the input of the level conversion circuit (4) is connected to the output of the charge pump (3); When the power tube control signal PD output by the driving circuit (1) is GND, the level conversion circuit (4) outputs low voltage to the gate of the power tube; the comparator (2) compares the source voltage and the drain voltage of the power tube; when the difference between the drain voltage and the source voltage of the power tube is greater than the threshold voltage, the comparator (2) outputs high voltage to the charge pump (3), the charge pump (3) generates voltage and inputs to the level conversion circuit (4), and the level conversion circuit (4) inputs low voltage to the gate of the power tube; when the difference between the drain voltage and the source voltage of the power tube is less than the threshold voltage, the comparator (2) outputs low voltage to the charge pump (3), the charge pump (3) outputs low voltage to the level conversion circuit (4), and the level conversion circuit (4) outputs low voltage to the gate of the power tube.

5. The method of claim 4, wherein, When the power tube control signal PD output by the driving circuit (1) is VCC, the level conversion circuit (4) outputs high voltage VCC, and the power tube is turned off.

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