Secondary Slope Compensation Circuit for Peak Current Mode Buck Converter

Abstract

The invention discloses a secondary slope compensation circuit suitable for a peak current mode Buck converter, comprising a primary voltage generating circuit and a secondary current generating circuit; whether the primary voltage generating circuit works is determined according to PWM information of the Buck converter, when the main switch tube of the Buck is turned off, the primary voltage generating circuit does not work, and the output current of the secondary current generating circuit is 0; when the main switch tube of the Buck is turned on, the primary voltage generating circuit works normally, and its output is voltage information that changes linearly with time, and the voltage information is used as the input of the secondary current generating circuit, and the secondary current generating circuit outputs a current information that changes quadratically with time according to the input linearly changing voltage, and the current information can be used for slope compensation, which can ensure that the Buck current loop can maintain stability within the full duty cycle range, and at the same time, no over-compensation phenomenon occurs.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuits, and in particular relates to a secondary slope compensation circuit suitable for a peak current mode Buck converter. Background Art

[0002] In a peak current mode controlled buck converter circuit operating in CCM mode with a duty cycle greater than 50%, the small change Δ1 between the inductor current (solid line) and the ideal value (dashed line) will be amplified cycle by cycle. Figure 1 As shown, the system is unstable, which is called subharmonic oscillation. Subharmonic oscillation can be solved by slope compensation, that is, let V COMP The voltage gradually decreases with time during the period when the inductor current rises, that is, let V COMP The voltage minus a voltage that changes with time is called a ramp voltage, such as Figure 2 As shown, or the ramp voltage is superimposed on the output of the inductor current detection module.

[0003] The amount of slope compensation must be appropriate. If it is too small, Figure 3 As shown, subharmonic oscillations will still occur. If the slope compensation is too large, it will lead to overcompensation, turning the buck converter into voltage-mode control, which violates the original intention of current-mode control. Moreover, excessive slope compensation will limit the peak and average currents of the inductor, thereby limiting the buck converter's output power. Therefore, a circuit is needed that can dynamically adjust the slope compensation amount based on the duty cycle. When the duty cycle is small, the slope compensation amount is small, and when the duty cycle is large, the slope compensation amount is large, avoiding overcompensation and undercompensation.

[0004] Figure 4 This is the core circuit diagram of the patent with patent publication number CN108667293. It is also a secondary slope compensation circuit suitable for Buck. The circuit is divided into three parts: adaptive current generation module, primary slope generation module, and secondary slope generation module. The adaptive current generation module uses negative feedback to make the current flowing through R3 proportional to the input voltage. This current is called adaptive current, which will change with the change of VIN. This current is mirrored to Q1 through the MP1 and MP3 current mirrors. When CLK is low, MN2 is turned off, and the adaptive current charges capacitor C through Q1, causing the voltage across the capacitor to increase linearly with time. Due to the action of the Q1 and Q2 current mirrors, the voltage across R4 is equal to the voltage across capacitor C, so that the current flowing through R4 increases linearly with time, that is, a linear current is generated. This current is mirrored to MN3 and MN4 through MP4 and MP5. MN3, MN4, MN5, and MN7 form a translinear loop. These tubes all operate in the subthreshold region, and their I DS With V GSThe linear current, passing through the linear transconductance loop, outputs a quadratic current that changes with time in a squared relationship. This current is converted into a quadratic ramp voltage via R5. However, this circuit structure is overly complex, with numerous circuit design parameters, making it difficult to implement. Furthermore, mismatches in the current mirror and the transistors in the linear transconductance loop can easily cause system errors, resulting in low accuracy. Finally, this circuit has too many paths from the power supply to ground and uses an operational amplifier, resulting in excessive power consumption. Power consumption is crucial for switching power supplies, and switching power supply design should minimize power consumption. This circuit is not suitable for high-efficiency buck converters.

[0005] Patent number CN105896972 discloses another adaptive secondary slope compensation circuit, including an adaptive current generating circuit and a secondary voltage signal generating circuit. The first input of the adaptive current generating circuit is connected to the Buck duty cycle signal, the second input is connected to the reference voltage, and the output is connected to the first input of the secondary voltage signal generating circuit. The second input of the secondary voltage signal generating circuit is connected to the pulse switching signal, and the output is a secondary voltage signal. However, as described in the previous circuit, this circuit is also complex, involving a switched capacitor circuit, complex circuit parameter design, complex structure, and high power consumption. Summary of the Invention

[0006] The object of the present invention is to provide a secondary slope compensation circuit suitable for a peak current mode Buck converter, which adopts a simpler circuit structure, has low circuit power consumption and accurate slope compensation amount.

[0007] The technical solution adopted by the present invention is:

[0008] A secondary slope compensation circuit suitable for a peak current mode Buck converter includes a primary voltage generating circuit and a secondary current generating circuit. Whether the primary voltage generating circuit operates is determined based on the PWM information of the Buck converter. When the Buck converter's main switch is off, the primary voltage generating circuit is inoperative, and the secondary current generating circuit outputs zero current. When the Buck converter's main switch is on, the primary voltage generating circuit operates normally, and its output is voltage information that varies linearly with time. This voltage information serves as input to the secondary current generating circuit, which outputs current information that varies quadratically with time based on the input linearly varying voltage. This current information is used for slope compensation to ensure that the Buck current loop remains stable within the full duty cycle range and that overcompensation is avoided.

[0009] The primary voltage generating circuit includes a first NPN transistor T1, a second NPN transistor T2, a third NPN transistor T3, a fourth NPN transistor T4, a fifth NPN transistor T5, a sixth NPN transistor T6, a resistor R1, an input reference current source I REF, a first PMOS tube M1, a second PMOS tube M2, and a third PMOS tube M3; the secondary current generating circuit includes a fourth PMOS tube M4;

[0010] The base of the first NPN transistor T1 is connected to its collector, and its collector is the input reference current source I REF The input terminal;

[0011] The base of the second NPN transistor T2 is connected to the base of the first NPN transistor T1;

[0012] The base of the third NPN transistor T3 is connected to the base of the first NPN transistor T1;

[0013] The base of the fourth NPN transistor T4 is connected to the emitter of the second NPN transistor T2, the emitter thereof is grounded, and the collector thereof is connected to the emitter of the first NPN transistor T1;

[0014] The base of the fifth NPN transistor T5 is connected to the emitter of the first NPN transistor T1, the collector thereof is connected to the emitter of the second NPN transistor T2, the emitter thereof is connected to the resistor R1, and the other end of the resistor R1 is grounded;

[0015] The base and collector of the sixth NPN transistor T6 are connected, and the collector is connected to the emitter of the third NPN transistor T3, and the emitter is grounded;

[0016] The source of the first PMOS transistor M1 is connected to the power supply VDD, the gate and drain of the first PMOS transistor M1 are connected to the collector of the second NPN transistor T2;

[0017] The source and drain of the second PMOS transistor M2 are connected to the power supply VDD, and the gate thereof is connected to the collector of the third NPN transistor T3;

[0018] The source of the third PMOS transistor M3 is connected to the drain of the first PMOS transistor M1, the drain of the third PMOS transistor M3 is connected to the gate of the second PMOS transistor M2, and the gate of the third PMOS transistor M3 is connected to the input PWM signal;

[0019] The source of the fourth PMOS transistor M4 is connected to the power supply VDD, the gate thereof is connected to the gate of the second PMOS transistor M2, and the drain thereof is the output end of the secondary current generating circuit.

[0020] Furthermore, the second PMOS transistor M2 is replaced by a capacitor, one end of the capacitor is connected to the power supply VDD, and the other end is connected to the collector of the third NPN transistor T3.

[0021] Furthermore, the input reference current source I REF is the current related to the switching frequency.

[0022] The beneficial effects of the present invention are:

[0023] The present invention adopts a simpler circuit structure with low circuit power consumption, which can improve the efficiency of the converter. The circuit is less affected by process parameters and has high portability. Even if the process is changed, the circuit parameters can still be well designed. In addition, the present invention creates a new current mirror circuit with high circuit precision, accurate current mirror ratio, and little influence from the process, so that the slope compensation amount is accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram of subharmonic oscillation;

[0025] Figure 2 is a schematic diagram of a ramp voltage;

[0026] Figure 3 This is a schematic diagram of subharmonic oscillation when the amount of slope compensation is too small;

[0027] Figure 4 This is a secondary slope compensation circuit diagram suitable for Buck;

[0028] Figure 5 This is a simplified diagram of a secondary slope compensation circuit suitable for a peak current mode Buck converter;

[0029] Figure 6 This is a secondary slope compensation circuit diagram suitable for peak current mode Buck converter. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0031] The circuit of the present invention utilizes a simpler circuit structure, resulting in low power consumption and improved converter efficiency. Furthermore, the circuit is less susceptible to process parameters and offers high portability, allowing for easy design of circuit parameters even with process changes. Furthermore, the present invention creates a novel current mirror circuit with high circuit precision, accurate current mirror ratios, and minimal process influence, resulting in precise slope compensation.

[0032] The secondary slope compensation circuit of the present invention is suitable for a peak current mode Buck converter, such as Figure 5As shown, the primary voltage generation circuit and the secondary current generation circuit are included. Whether the primary voltage generation circuit operates is determined by the PWM information of the Buck converter. When the Buck converter's main switch is off, the primary voltage generation circuit is inoperative, and the secondary current generation circuit outputs zero current. When the Buck converter's main switch is on, the primary voltage generation circuit operates normally, and its output is a voltage that varies linearly with time. This voltage information serves as the input of the secondary current generation circuit. Based on the input linearly varying voltage, the secondary current generation circuit outputs a current information that varies quadratically with time. This current information can be used for slope compensation, ensuring that the Buck current loop remains stable over the full duty cycle range without overcompensation.

[0033] The specific circuit implementation is as follows Figure 6 As shown, the primary voltage generating circuit includes a first NPN transistor T1, a second NPN transistor T2, a third NPN transistor T3, a fourth NPN transistor T4, a fifth NPN transistor T5, a sixth NPN transistor T6, a resistor R1, an input reference current source I REF , a first PMOS tube M1, a second PMOS tube M2, and a third PMOS tube M3; the secondary current generating circuit includes a fourth PMOS tube M4.

[0034] The base of the first NPN transistor T1 is connected to its collector, and its collector is the input reference current source I REF The input terminal;

[0035] The base of the second NPN transistor T2 is connected to the base of the first NPN transistor T1;

[0036] The base of the third NPN transistor T3 is connected to the base of the first NPN transistor T1;

[0037] The base of the fourth NPN transistor T4 is connected to the emitter of the second NPN transistor T2, the emitter thereof is grounded, and the collector thereof is connected to the emitter of the first NPN transistor T1;

[0038] The base of the fifth NPN transistor T5 is connected to the emitter of the first NPN transistor T1, the collector thereof is connected to the emitter of the second NPN transistor T2, the emitter thereof is connected to the resistor R1, and the other end of the resistor R1 is grounded;

[0039] The base and collector of the sixth NPN transistor T6 are connected, and the collector is connected to the emitter of the third NPN transistor T3, and the emitter is grounded;

[0040] The source of the first PMOS transistor M1 is connected to the power supply VDD, the gate and drain of the first PMOS transistor M1 are connected to the collector of the second NPN transistor T2;

[0041] The source and drain of the second PMOS transistor M2 are connected to the power supply VDD, and the gate thereof is connected to the collector of the third NPN transistor T3;

[0042] The source of the third PMOS transistor M3 is connected to the drain of the first PMOS transistor M1, the drain of the third PMOS transistor M3 is connected to the gate of the second PMOS transistor M2, and the gate of the third PMOS transistor M3 is connected to the input PWM signal;

[0043] The source of the fourth PMOS transistor M4 is connected to the power supply VDD, the gate thereof is connected to the gate of the second PMOS transistor M2, and the drain thereof is the output end of the secondary current generating circuit.

[0044] Basic principle analysis:

[0045] Step 1: Generate a current proportional to the input reference current source.

[0046] The base voltages of T1, T2, and T3 are:

[0047]

[0048]

[0049]

[0050] Among them, I1 and I2 are the collector currents flowing through T2 and T3 respectively. K is the Boltzmann constant, T is the thermodynamic temperature, q is the electron charge, a is the number of T6 tubes in parallel, that is, the emission junction area coefficient, I s is the saturation current of the NPN tube.

[0051] Combining equations (1.1) and (1.2), we get:

[0052]

[0053] Combining equations (1.2) and (1.3), we get:

[0054]

[0055] Combining equations (1.4) and (1.5), we get:

[0056]

[0057] It can be found that I2 and I REF The ratio is very precise and is minimally affected by process parameters. Furthermore, current flows only through three branches in the circuit of the present invention, resulting in very low circuit power consumption. Furthermore, the magnitude of I2 can be adjusted by adjusting the size of resistor R1 and the emitter junction area of ​​T5, making the circuit of the present invention applicable to various switching frequencies.

[0058] Step 2: Generate a linearly varying voltage controlled by the input PWM signal.

[0059] When the high-side tube is turned off, the PWM signal is low, the M3 tube is turned on, and the M1 tube provides I1 and I2 currents. Its width-to-length ratio (W / L) 1 is very large, much larger than the width-to-length ratio (W / L) 4 of the M4 tube, so |V GS1 |=|V GS2 |=|V GS4 |≈|V THP |, M4 tube works in the subthreshold region, its gate-source voltage |V GS4 | Constant, the secondary ramp current I slope It is very small and can be ignored. When the high-side tube is turned on, the PWM signal is high, the M4 tube is turned off, the M1 tube provides I1 current, and the constant current I2 extracts the gate charge of M2 and M4, making |V GS4 |Decreases linearly over time, that is:

[0060]

[0061] When designing M2 and M4 sizes, select (WL)2÷(WL)4, then C g It can be seen that the equivalent MOS capacitor of M2 tube is C g ≈(WL)2·C ox , C ox is the gate oxide capacitance per unit area, and its size is determined by the process. From formula (1.7), we can find that |V GS4 (t) | Varies linearly with time.

[0062] Step 3: Generate a ramp current that has a quadratic relationship with time.

[0063] When M3 operates in the saturation region, the relationship between its drain-source current and gate-source voltage is:

[0064]

[0065] From equations (1.6), (1.7), and (1.8), we can obtain:

[0066]

[0067] Among them, μ p is the hole mobility. According to formula (1.9), it can be found that the secondary ramp current I slope It has a quadratic relationship with time t.

[0068] The first step utilizes a self-designed circuit structure to generate a precise reference current source mirror current I2, thereby ensuring sufficiently accurate slope compensation. The third step utilizes the quadratic relationship between the drain-source current and the gate-source voltage when the MOSFET operates in its saturation region to design a secondary current generation circuit. This approach is clear and novel, with a simple circuit structure, and can be implemented using only a single MOSFET. The emitter junction area ratio coefficients of all NPN transistors in the circuit diagram of this invention can be modified.

[0069] In addition, the function of M2 tube is equivalent to a capacitor, which can be replaced by a capacitor. Input reference current source I REF It can be changed to a current related to the switching frequency, and the circuit structure can be transformed into an adaptive secondary slope compensation circuit.

[0070] In summary, the overall circuit structure of the present invention is simple, which is conducive to the actual circuit parameter design, has high circuit portability, and has very low power consumption, which effectively improves the efficiency of the Buck converter. REF The proportional I2 current generating circuit is an independently innovative design circuit with a novel structure, simple circuit and high precision. The secondary current generating circuit has a simple and novel structure and can be realized with only one MOSFET. The idea is innovative.

[0071] It will be easily understood by those skilled in the art that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A secondary slope compensation circuit suitable for a peak current mode Buck converter, characterized in that: It includes a primary voltage generating circuit and a secondary current generating circuit; whether the primary voltage generating circuit works is determined according to the PWM information of the Buck converter: when the main switch tube of the Buck is turned off, the primary voltage generating circuit does not work, and the output current of the secondary current generating circuit is 0; when the main switch tube of the Buck is turned on, the primary voltage generating circuit works normally, and its output is voltage information that changes linearly with time. The voltage information is used as the input of the secondary current generating circuit. The secondary current generating circuit outputs a current information that changes quadratically with time according to the input linearly changing voltage. The current information is used for slope compensation to ensure that the Buck current loop can maintain stability within the full duty cycle range, and at the same time, there will be no over-compensation phenomenon; wherein: The primary voltage generating circuit includes a first NPN tube T1, a second NPN tube T2, a third NPN tube T3, a fourth NPN tube T4, a fifth NPN tube T5, a sixth NPN tube T6, a resistor R1, an input reference current source I REF , a first PMOS tube M1, a second PMOS tube M2, and a third PMOS tube M3; the secondary current generating circuit includes a fourth PMOS tube M4; The base of the first NPN transistor T1 is connected to its collector, and its collector is the input reference current source I REF The input terminal; The base of the second NPN transistor T2 is connected to the base of the first NPN transistor T1; The base of the third NPN transistor T3 is connected to the base of the first NPN transistor T1; The base of the fourth NPN transistor T4 is connected to the emitter of the second NPN transistor T2, the emitter thereof is grounded, and the collector thereof is connected to the emitter of the first NPN transistor T1; The base of the fifth NPN transistor T5 is connected to the emitter of the first NPN transistor T1, the collector thereof is connected to the emitter of the second NPN transistor T2, the emitter thereof is connected to the resistor R1, and the other end of the resistor R1 is grounded; The base of the sixth NPN transistor T6 is connected to the collector, the collector is connected to the emitter of the third NPN transistor T3, and the emitter is grounded; The source of the first PMOS tube M1 is connected to the power supply VDD, the gate and drain thereof are connected, and the drain thereof is connected to the collector of the second NPN tube T2; The source and drain of the second PMOS tube M2 are connected to the power supply VDD, and the gate thereof is connected to the collector of the third NPN tube T3; The source of the third PMOS tube M3 is connected to the drain of the first PMOS tube M1, the drain of the third PMOS tube M3 is connected to the gate of the second PMOS tube M2, and the gate of the third PMOS tube M3 is connected to the input PWM signal; The source of the fourth PMOS transistor M4 is connected to the power supply VDD, the gate thereof is connected to the gate of the second PMOS transistor M2, and the drain thereof is the output end of the secondary current generating circuit.

2. The secondary slope compensation circuit suitable for a peak current mode Buck converter according to claim 1, characterized in that: The second PMOS tube M2 is replaced by a capacitor, one end of the capacitor is connected to the power supply VDD, and the other end is connected to the collector of the third NPN tube T3.

3. The secondary slope compensation circuit suitable for a peak current mode Buck converter according to claim 1, characterized in that: Input reference current source I REF is the current related to the switching frequency.

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