Analog-to-digital conversion circuit, image sensing device and operation method thereof

Abstract

The present application relates to an analog-to-digital conversion circuit, an image sensing device, and an operation method thereof. An analog-to-digital conversion circuit includes: a converter configured to perform a first comparison operation for sensing noise based on a reset signal and to perform a second comparison operation for sensing raw data to output data obtained by removing noise from the raw data; and a ramp voltage generator configured to generate a ramp voltage for the first comparison operation and the second comparison operation and output the ramp voltage to the converter. The ramp voltage generator includes: a first current source for providing a bias current for generating a ramp voltage in response to a first control signal; a second current source for providing a boost current for generating a ramp voltage in response to a second control signal; and a generating circuit for generating a ramp voltage based on the bias current and the boost current.

Description

Technical Field

[0001] One or more embodiments described herein relate to a design for a semiconductor device, and more particularly, to a ramp signal generator, an image capture device, and an operating method thereof. Background Art

[0002] An image sensor is a device that captures an image by using the properties of a semiconductor that reacts to light. Image sensors can be classified into an image sensor using a charge coupled device (CCD) and another image sensor using a complementary metal oxide semiconductor (CMOS). Recently, image sensing devices using CMOS have been widely used due to the advantage that analog and digital control circuits can be implemented on a single integrated circuit (IC). Summary of the invention

[0003] According to one aspect of the present disclosure, an analog-to-digital conversion circuit may include: a converter, which is configured to perform a first comparison operation for sensing noise based on a reset signal and to perform a second comparison operation for sensing original data to output data that can be obtained by removing noise from the original data; and a ramp voltage generator, which is configured to generate a ramp voltage for the first comparison operation and the second comparison operation and output the ramp voltage to the converter, wherein the ramp voltage generator may include: a first current source, which is used to provide a bias current for generating the ramp voltage in response to a first control signal; a second current source, which is used to provide a boost current for generating the ramp voltage in response to a second control signal; and a generating circuit, which is used to generate the ramp voltage based on the bias current and the boost current.

[0004] According to another aspect of the present disclosure, an image sensor may include: a pixel array including a plurality of pixels; a driver configured to output a reset signal and a transfer signal to the pixel array; a converter configured to perform a first comparison operation for sensing noise output from the pixel array based on the reset signal, perform a second comparison operation for sensing raw data output from the pixel array based on the transfer signal, and output data obtained by removing noise from the raw data; a ramp voltage generator configured to generate a ramp voltage for the first comparison operation and the second comparison operation and output the ramp voltage to the converter; and a data output circuit configured to collect data output from the converter and generate image data, wherein the ramp voltage may be stabilized to a target level after being raised above the target level.

[0005] According to another aspect of the present disclosure, a method for operating an image sensor includes a ramp voltage generator that provides a ramp voltage to a converter, the converter is configured to perform a first comparison operation for sensing noise transmitted from a pixel array and to perform a second comparison operation for sensing raw data transmitted from the pixel array, the method may include the following steps: generating a bias current for generating the ramp voltage in response to a first control signal; generating a boost current for generating the ramp voltage in response to a second control signal; and generating the ramp voltage based on the bias current and the boost current. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The description herein refers to the drawings, wherein like reference numerals refer to like parts throughout.

[0007] Figure 1 An image sensor according to one embodiment of the present disclosure is illustrated.

[0008] Figure 2 Example Figure 1 An example of a column analog-to-digital conversion (ADC) circuit described in .

[0009] Figure 3 Example Figure 1 to Figure 2 The operation of the image sensor is described in .

[0010] Figure 4 Example Figures 2 to 3 The ramp voltage described in .

[0011] Figure 5 A ramp voltage generator according to another embodiment of the present disclosure is illustrated.

[0012] Figure 6 Example Figure 5 The operation of the ramp voltage generator is described in .

[0013] Figure 7 A ramp voltage generator according to another embodiment of the present disclosure is illustrated.

[0014] Figure 8 Example Figure 7 The operation of the ramp voltage generator is described in .

[0015] Fig. 9 A method for operating an image sensor according to another embodiment of the present disclosure is illustrated. DETAILED DESCRIPTION

[0016] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0017] In the present disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc., are intended to indicate that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiment.

[0018] In this disclosure, the terms "comprises," "included," "includes," and "included" are open ended. As used in the appended claims, these terms specify the presence of the stated elements and do not preclude the presence or addition of one or more other elements. The terms in the claims do not preclude the device from including additional components (e.g., interface units, circuits, etc.).

[0019] In the present disclosure, various units, circuits or other components may be described or claimed as being "configured to" perform one or more tasks. In such a context, "configured to" is used to imply a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. In this way, even when a specified block / unit / circuit / component is not currently operating (e.g., not turned on or activated), the block / unit / circuit / component may be referred to as being configured to perform a task. Blocks / units / circuit / components used with the "configured to" language include hardware, such as memory, circuits, etc. that store executable program instructions to implement operations. Additionally, "configured to" may include a general structure (e.g., a general circuit) that is manipulated by software and / or firmware (e.g., an FPGA or a general processor that executes software) to operate in a manner that can perform the tasks in question. "Configured to" may also include an applicable manufacturing process (e.g., a semiconductor manufacturing facility) to manufacture a device (e.g., an integrated circuit) suitable for implementing or performing one or more tasks.

[0020] As used herein, the terms "first", "second", "third", etc. are used as labels for the nouns that precede them, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms "first" and "second" do not necessarily imply that the first value must be written before the second value. In addition, although the terms may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that otherwise has the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0021] In addition, the term "based on" is used to describe one or more factors that influence a determination. The term does not exclude additional factors that may influence a determination. That is, a determination may be based solely on these factors, or at least in part on these factors. Consider the phrase "A is determined based on B." While in this case, B is a factor that influences the determination of A, such a phrase does not exclude that the determination of A is also based on C. In other cases, A may be determined based solely on B.

[0022] One embodiment of the present disclosure may provide an apparatus and an operating method for enabling an image sensor to have a higher frame rate.

[0023] In addition, one embodiment of the present disclosure may provide an apparatus and an operating method for supporting high-resolution and high-speed operations of an image sensor that is widely used for video recording and included in a portable device such as a mobile phone.

[0024] In an embodiment of the present disclosure, an analog-to-digital conversion circuit may include: a converter configured to perform a first comparison operation for sensing noise based on a reset signal and to perform a second comparison operation for sensing raw data to output data obtained by removing noise from the raw data; and a ramp voltage generator configured to generate a ramp voltage for the first comparison operation and the second comparison operation and output the ramp voltage to the converter. The ramp voltage generator may include: a first current source for providing a bias current for generating a ramp voltage in response to a first control signal; a second current source for providing a boosting current for generating a ramp voltage in response to a second control signal; and a generating circuit for generating a ramp voltage based on the bias current and the boosting current.

[0025] The second current source may provide the boost current until the ramp voltage has a level equal to or higher than a target level.

[0026] The converter may include a comparator for sequentially comparing the ramp voltage with the noise and the original data, a clock controller for generating a clock signal, and a counter for counting the clock signal based on a result output from the comparator.

[0027] The first control signal and the second control signal may be activated simultaneously or sequentially. The activation section of the second control signal may be shorter than the activation section of the first control signal.

[0028] The second control signal may be activated separately before the first comparison operation and the second comparison operation.

[0029] In another embodiment, the image sensor may include: a pixel array including a plurality of pixels; a driver configured to output a reset signal and a transfer signal to the pixel array; a converter configured to perform a first comparison operation for sensing noise output from the pixel array based on the reset signal, perform a second comparison operation for sensing raw data output from the pixel array based on the transfer signal, and output data obtained by removing noise from the raw data; a ramp voltage generator configured to generate a ramp voltage for the first comparison operation and the second comparison operation and output the ramp voltage to the converter; and a data output circuit configured to collect data output from the converter and generate image data. The ramp voltage may be settled to a target level after being raised above the target level.

[0030] The ramp voltage generator may include: a first current source, which is used to provide a bias current for generating a ramp voltage in response to a first control signal; a second current source, which is used to provide a boost current for generating the ramp voltage in response to a second control signal; and a generating circuit, which is used to generate the ramp voltage based on the bias current and the boost current.

[0031] The first control signal and the second control signal may be activated simultaneously or sequentially, and an activation section of the second control signal is shorter than an activation section of the first control signal.

[0032] The second control signal may be activated separately before the first comparison operation and the second comparison operation.

[0033] The converter may include a comparator for sequentially comparing the ramp voltage with the noise and the original data, a clock controller for generating a clock signal, and a counter for counting the clock signal based on a result output from the comparator.

[0034] The pixel array may be configured to output noise and raw data on a column basis. The converter may include a plurality of components for performing a first comparison operation and a second comparison operation to identify noise and raw data output on a column basis. The ramp voltage generator may provide a ramp voltage of a level having a constant slope to the converter.

[0035] In another embodiment, the image sensor may include a ramp voltage generator that provides a ramp voltage to a converter, the converter being configured to perform a first comparison operation for sensing noise transmitted from a pixel array and to perform a second comparison operation for sensing raw data transmitted from the pixel array. A method for operating an image sensor may include: generating a bias current in response to a first control signal for generating a ramp voltage; generating a boost current in response to a second control signal for generating the ramp voltage; and generating the ramp voltage based on the bias current and the boost current.

[0036] The ramp voltage may be stabilized to the target level after being raised above the target level.

[0037] The first control signal and the second control signal may be activated simultaneously or sequentially. The activation section of the second control signal may be shorter than the activation section of the first control signal.

[0038] The second control signal may be activated before each of the first comparison operation and the second comparison operation.

[0039] In another embodiment, the operating method of the image sensor may include raising a ramp voltage to a level for each of a first comparison operation and a second comparison operation after an auto-zero operation; and boosting the ramp voltage raised to the level.

[0040] Embodiments of the present disclosure will now be described with reference to the drawings, wherein like reference numerals refer to like elements.

[0041] Figure 1 An image sensor according to an embodiment of the present disclosure is illustrated. Figure 1 The image sensor (CMOS image sensor, CIS) described in the present invention can be widely used in devices used in various technical fields, such as mobile phones, surveillance security devices, autonomous driving systems, machine vision systems, and Internet of Things (IoT) devices.

[0042] Reference Figure 1 The image sensor may include a pixel array 110, a row decoder 120, a controller 130, an analog-to-digital conversion circuit 140, and a data output circuit 150. According to an embodiment, the image sensor may also include Figure 1 Another module or circuit not shown.

[0043] The pixel array 110 may include a plurality of pixels 112. The pixel array 110 may have a structure in which a plurality of pixels 112 are arranged in horizontal and vertical directions. Each pixel 112 may include a photodiode and four transistors. According to one embodiment, the pixel 112 may include a photodiode and three transistors. In addition, according to another embodiment, the pixel 112 may include a plurality of photodiodes.

[0044] The row decoder 120 (e.g., a driver) may drive the plurality of pixels 112 included in the pixel array 110 on a row basis. When the row decoder 120 drives the plurality of pixels 112 on a row basis, the plurality of pixels 112 may transmit data or signals to the analog-to-digital conversion circuit 140 through each row arranged for each column. The row decoder 120 may be controlled by the controller 130.

[0045] The controller 130 may participate in the overall operation of the image sensor. The controller 130 may control the row decoder 120 , the analog-to-digital conversion circuit 140 , and the data output circuit 150 .

[0046] The signal or information output from the pixel 112 driven by the row decoder 120 is an analog signal. The analog-to-digital conversion circuit 140 may convert the analog signal or information output from the pixel 112 into a digital signal or information. The digital signal or information calculated by the analog-to-digital conversion circuit 140 may be temporarily stored or collected by the data output circuit 150, and the output data DATA_OUTPUT may be transmitted to another device (e.g., an image signal processor, a circuit, a module, etc.) by the controller 130. According to one embodiment, the data output circuit 150 may output raw Bayer data (e.g., a Bayer pattern image or the raw output of a Bayer-filter camera). For example, the Bayer-filter pattern is 50% green, 25% red, and 25% blue, and is therefore also referred to as BGGR, RGBG, GRBG, or RGGB.

[0047] The analog-to-digital conversion circuit 140 included in the image sensor may have a signal reading structure (e.g., a column parallel structure in which units or modules operating on a column basis are arranged in parallel). The analog-to-digital conversion circuit 140 having such a structure can reduce noise and increase bandwidth in the process of reading pixel data output from the pixel array 110. Through this process, the analog-to-digital conversion circuit 140 can read the data output from the pixel array 110 to reduce signal quality deterioration and support the output of the read pixel data at a very high speed.

[0048] As the resolution of the image sensor increases, the size (e.g., plane area or pitch) of the pixels 112 in the pixel array 110 decreases. As the image sensor supports a higher frame rate, the time for the pixels 112 in the pixel array 110 to receive incident light and convert the incident light into an electric charge is shorter. In addition, since the image sensor is mounted on a small device such as a portable terminal or a camera, the size of the image sensor can be limited. For these reasons, the analog-to-digital conversion circuit 140 is arranged in each column at narrow intervals, and the size or amplitude of the signal or information output from the pixel array 110 is reduced, so that the analog-to-digital conversion circuit 140 is designed under very strict constraints.

[0049] Figure 2 Illustrated in Figure 1 An example of a column analog-to-digital conversion (ADC) circuit described in .

[0050] Reference Figure 2 The analog-to-digital conversion circuit 140 may include a ramp voltage generator 142, a clock signal controller 146, a comparator 144, and a counter 148. The plurality of pixels 112 included in the pixel array 110 may be decoded by a row decoder 120 (in Figure 2 The upper portion indicates a driver 120) to drive the pixel information or the original signal V PIX The ramp voltage generator 142 provides the ramp voltage V to the comparator 144. RAMP The comparator 144 converts the ramp voltage V RAMP The pixel information or raw signal V sent from the pixel array 110 PIX The clock signal controller 146 provides a clock signal having a preset period to the counter 148. The counter 148 counts the clock signal in response to the comparison result CMP output from the comparator 144. Through these operations, the pixel information or the original signal V transmitted from the pixel array 110 is PIX (which is an analog value) can be converted into the result output from the counter 148 (counter output, see Figure 3 ), which is a numeric value.

[0051] Figure 2 The analog-to-digital conversion circuit 140 shown in FIG. 1 has a column parallel structure. As described above, the column parallel structure is a structure in which each conversion module corresponding to each column is arranged. In this article, the conversion module is used to convert pixel information or original signal V PIX After a plurality of pixels 112 arranged corresponding to a single row in the pixel array 110 are selected, the pixel information or the original signal V PIX The transmission is performed through a plurality of column lines respectively connected to a plurality of pixels 112 of the selected row. The conversion modules arranged in a column parallel structure convert the corresponding analog information or the original signal V PIX The ramp voltage V outputted from the ramp voltage generator 142 is converted into a corresponding digital value (pixel data). RAMP The ramp voltage generator 142 may be shared with multiple conversion modules arranged in a column parallel structure. According to one embodiment, the ramp voltage generator 142 may be controlled by a control signal (eg, Ramp_En, Boost_En, see Figure 5 and Figure 7Because the conversion module arranged for each column in the analog-to-digital conversion circuit 140 includes a comparator and a counter, the conversion module does not require a large area, so that a plurality of conversion modules in the analog-to-digital conversion circuit 140 can be integrated at narrow intervals.

[0052] In one embodiment, a plurality of pixels 112 included in a pixel array 110 in an image sensor may output fixed pattern noise (FPN), where different information or signals are output in the same environment (e.g., illumination, etc.). The fixed pattern noise FPN may be generated due to mismatch of transistors arranged in columns included in the plurality of pixels 112 and dark current generated in the plurality of pixels 112. The analog-to-digital conversion circuit 140 may perform a correlated double sampling (CDS) operation to remove the fixed pattern noise (FPN). The correlated double sampling (CDS) operation will be described later in Figure 3 Described in.

[0053] As the number and frame rate of pixels in the pixel array 110 included in the image sensor (CIS) increase, the analog-to-digital conversion circuit 140 may be designed differently for quickly reading and converting the outputs of the plurality of pixels 112. According to one embodiment, the analog-to-digital conversion circuit 140 may include a single slope ADC (SS-ADC) having high linearity and occupying a small area (e.g., highly integrated). The single slope ADC (SS-ADC) may have difficulty in achieving short analog-to-digital conversion time and high resolution because the single slope ADC (SS-ADC) uses a large number of clocks for analog-to-digital conversion. In addition, according to the embodiment, in order to overcome the shortcomings of the single slope ADC (SS-ADC), the analog-to-digital conversion circuit 140 may include a delta-sigma conversion circuit (e.g., a delta-sigma ΔΣ ADC), a cyclic conversion circuit (e.g., a cyclic ADC), or a successive approximation register conversion circuit (e.g., a SAR ADC). In this article, the delta-sigma conversion circuit (ΔΣ ADC) and the cyclic conversion circuit (cyclic ADC) may have low noise and short analog-to-digital conversion time. However, a delta-sigma conversion circuit (ΔΣADC) and a cyclic conversion circuit (cyclic ADC) should use an operational amplifier (Op Amp) with high power consumption. A successive approximation register conversion circuit (SARADC) may include a capacitor, a digital-to-analog converter (DAC), SAR logic, and a comparator, which may reduce power consumption and have a short analog-to-digital conversion time, but may have large noise and occupy a large area.

[0054] Figure 3 Example Figure 1 to Figure 2 The operation of the image sensor is described in .

[0055] Reference Figures 1 to 3, can refer to the ramp voltage V output from the ramp voltage generator 142 RAMP , pixel information or raw signal V output from pixel 122 PIX , the comparison result CMP output from the comparator 144, and the result Counter Output output from the counter 148 are used to describe the operation of the image sensor. Specifically, the analog-to-digital conversion circuit 140 can perform two comparison operations. The first comparison operation (in Figure 3 denoted as the "first phase" in the Figure 3 ) may be associated with a correlated double sampling (CDS) operation.

[0056] By the reset signal (RX, see Figure 4 ) The pixel information or raw signal V output from the pixel 122 PIX The analog-to-digital conversion circuit 140 may have a potential indicating a reset state of the pixel 122. When the photoelectric conversion element (e.g., a photodiode) generates charge in response to incident light, the potential may be changed. During the first comparison operation of the comparator 144, the analog-to-digital conversion circuit 140 may compare the potential indicating the reset state output by the reset signal RX with the ramp voltage V RAMP When the ramp voltage V RAMP is lower than the pixel information or raw signal V output from the pixel 122 PIX When , the comparison result CMP changes (eg, from '1' to '0'). The counter 148 may count the clock signal until the comparison result CMP is changed, thereby obtaining a value corresponding to the noise.

[0057] After a photoelectric conversion element (eg, a photodiode) in the pixel 122 generates charge in response to incident light, pixel information or a raw signal V output from the pixel 122 is PIX During the second comparison operation, the comparator 144 may change the pixel information or the original signal V output from the pixel 122. PIX With the ramp voltage V RAMP When the ramp voltage V RAMP is lower than the pixel information or raw signal V output from the pixel 122 PIX, the comparison result CMP is changed again (e.g., from '1' to '0'). The counter 148 may count the clock signal until the comparison result CMP is changed so as to obtain pixel data corresponding to the incident light. When the first value obtained in the first comparison operation is subtracted from the second value obtained in the second comparison operation through a correlated double sampling (CDS) operation, pixel data (Data) with reduced noise or no noise may be obtained, the pixel data corresponding to the amount of charge generated by the pixel 122 in response to the incident light.

[0058] Figure 3 The ramp voltage V RAMP The analog-to-digital conversion circuit 140 may output the pixel information or the original signal V output from the pixel 122. PIX and the ramp voltage V RAMP A digital signal (e.g., a digital code) with the same level or timing corresponding to the time. RAMP The preset constant slope may be related to the resolution of the output image. RAMP When the slope of does not change but remains constant, the linearity of analog-to-digital conversion performed by the analog-to-digital conversion circuit 140 can be improved even though some factors such as parasitic capacitors may adversely affect.

[0059] Figure 4 Illustrated in Figures 2 to 3 The ramp voltage V RAMP .

[0060] Reference Figure 4 , ramp voltage V RAMP The first comparison operation and the second comparison operation ( Figure 3 The comparator 144 can convert the pixel information or the original signal V output from the pixel 122 into a preset target level or potential before the first stage and the second stage shown in FIG. PIX With the ramp voltage V RAMP In addition, during each of the first comparison operation and the second comparison operation, the ramp voltage V RAMP The ramp enable signal Ramp_En can be used to generate a ramp voltage V RAMP ,like Figure 5 and 7 After the auto-zero operation, the ramp enable signal Ramp_En may be activated from the beginning of the first boost section to the end of the second comparison operation.

[0061] According to one embodiment, the image sensor may output data DATA_OUTPUT (eg, Figure 1 During the auto-zero operation according to the auto-zero signal AZ, the image sensor can ramp the voltage V RAMP The level of the pixel information or the original signal V output from the pixel 122 PIX During the first comparison operation (first phase), the image sensor may measure the potential (e.g., voltage level) remaining in the pixel 122 as a reference for obtaining accurate pixel data without noise. The voltage level measured during the first comparison operation (first phase) may be different for each pixel 122. During the second comparison operation (second phase), the image sensor may obtain pixel information or a raw signal V based on the amount of charge generated in response to the incident light. PIX Convert to digital value to output data DATA_OUTPUT.

[0062] Reference Figure 4 , in the auto-zero (AZ) operation and the first comparison operation (ie, Figure 3 During the first rising section between the first comparison operation ( Figure 3 The "first stage") and the second comparison operation (i.e., Figure 3 During the second boosting section between the "second stage" and the "second stage", the ramp voltage VRAMP also increases to a preset target level. RAMP The level of V increases faster, that is, during the first and second boost sections, the ramp voltage V RAMP The first and second boost sections rising to the preset target level can be shortened so that the first comparison operation (first stage) and the second comparison operation (second stage) can be performed earlier. By this, the frame rate of the image sensor can be increased.

[0063] Figure 5 A ramp voltage generator 142A according to one embodiment of the present disclosure is illustrated.

[0064] Reference Figure 5 The ramp voltage generator 142A may include a signal for generating a ramp voltage V in response to a ramp enable signal Ramp_En. RAMP The first current circuit 362 for providing a bias current for generating a ramp voltage V in response to an enable signal Ramp_En. RAMPA second current circuit 364A for boosting the current, and a circuit for generating a ramp voltage V based on the bias current and the boosting current RAMP According to one embodiment, the first current circuit 362 and the second current circuit 364A may include current sources separately. The generating circuit 366 may include a variable resistor. Figure 5 The current source and the variable resistor shown in FIG. 1 are given as examples, and according to one embodiment, the configurations of the first current circuit 362 , the second current circuit 364A, and the generating circuit 366 included in the ramp voltage generator 142A may be different.

[0065] Figure 6 Illustrated in Figure 5 The operation of the ramp voltage generator 142A is described in .

[0066] Reference Figure 5 and Figure 6 , the ramp voltage V output from the ramp voltage generator 142A RAMP can be preset to have a target level 202. However, when the ramp voltage generator 142A includes the first current circuit 362 for generating the bias current but does not include the second current circuit 364A for generating the boost current, the ramp voltage VRAMP can actually have a value such as Figure 6 The first potential 204 slowly reaches the target level 202 as shown by the dashed curve segment in FIG. Compared with the designed target level 202, the first potential 204 takes a longer time to rise to the preset target level. In one embodiment, when the ramp voltage generator 142A uses the first current circuit 362 and the second current circuit 364A, a larger amount of current can be quickly provided so that the ramp voltage V RAMP can increase faster or can be boosted like the second potential 206. That is, because the second current circuit 364A provides boosted current, the ramp voltage V RAMP The second potential 206 may rise to the preset target level 202 in a faster time than the first potential 204. RAMP The time required to reach the preset target level is much faster, so the Figure 4 The lifting section described in .

[0067] Figure 7 A ramp voltage generator 142B according to another embodiment of the present disclosure is illustrated.

[0068] Reference Figure 7 , the ramp voltage generator 142B may include: a first current circuit 362 for providing a current for generating a ramp voltage V in response to a ramp enable signal Ramp_En RAMPA bias current; a second current circuit 364B, which is used to provide a ramp voltage V for generating a ramp voltage in response to the boost enable signal Boost_En. RAMP and a generating circuit 366 for generating a ramp voltage V based on the bias current and the boost current RAMP According to one embodiment, the first current circuit 362 and the second current circuit 364B may include a current source. The generating circuit 366 may include a variable resistor. Figure 7 The current source and the variable resistor shown in FIG. 1 are given as examples, and according to one embodiment, the configurations of the first current circuit 362, the second current circuit 364B, and the generating circuit 366 included in the ramp voltage generator 142B may be different.

[0069] When the general Figure 5 and Figure 7 When the ramp voltage generators 142A, 142B described in FIG. 1 are compared to each other, there are differences between the second current circuits 364A, 364B. Figure 5 The second current circuit 364A described in the above may be controlled by the ramp enable signal Ramp_En which is also applied to the first current circuit 362. However, Figure 7 The second current circuit 364B described in the embodiment of the present invention can be controlled by a boost enable signal Boost_En, which is different and distinguishable from the ramp enable signal Ramp_En applied to the first current circuit 362. The boost enable signal Boost_En can be activated at the same time as the ramp enable signal Ramp_En. However, in one embodiment, the boost enable signal Boost_En can be activated in a shorter section than the ramp enable signal Ramp_En. In the ramp voltage generator 142B, the second current circuit 364B can be used only in a portion of the duration of the boost section and may not be activated in other operating sections.

[0070] According to one embodiment, the boost enable signal Boost_En and the ramp enable signal Ramp_En may be activated sequentially. Even if the boost enable signal Boost_En and the ramp enable signal Ramp_En are activated sequentially, an activation section of the boost enable signal Boost_En may overlap with an activation section of the ramp enable signal Ramp_En.

[0071] Figure 8 Example Figure 7 The operation of the ramp voltage generator 142B is described in .

[0072] Reference Figure 7 and Figure 8 , the ramp voltage V output from the ramp voltage generator 142B RAMPcan be preset to have a target level 212. However, when the ramp voltage generator 142B includes the first current circuit 362 for generating the bias current but does not include the second current circuit 364B for generating the boost current, the ramp voltage V RAMP In fact, it can have Figure 8 The first potential 214 slowly reaches the target level 212 as shown by the dashed curve segment in FIG. Compared with the designed target level 212, the first potential 214 takes a longer time to rise to the preset target level.

[0073] In one embodiment, when the ramp voltage generator 142B uses the first current circuit 362 and the second current circuit 364B, a larger amount of current can be quickly provided so that the ramp voltage V RAMP can increase faster than the second potential 216. That is, because the second current circuit 364B provides a boost current, in this embodiment, the ramp voltage V RAMP The second current circuit 364B may have a second potential 216 temporarily raised above the preset target level 212. The second current circuit 364B may induce a temporary overvoltage condition, wherein the ramp voltage V RAMP The overvoltage condition can be helpful to quickly reach the preset target level 212 during the boost section. Therefore, the ramp voltage V RAMP The potential can be increased to the preset level more quickly and the time required to Figure 4 The lifting section described in .

[0074] Fig. 9 A method for operating an image sensor according to another embodiment of the present disclosure is illustrated. Figures 1 to 8 The image sensor may include a pixel array 110, the pixel array 110 including a plurality of pixels 112. The image sensor may further include: an analog-to-digital conversion circuit 140 configured to perform a first comparison operation (first phase) to detect noise transmitted from the pixel 112 and to perform a second comparison operation (second phase) to detect raw data; and a ramp voltage generator 142 configured to generate a ramp voltage V RAMP Provided to the analog-to-digital conversion circuit 140.

[0075] Reference Fig. 9 The method for operating an image sensor may include (at step 282) generating a ramp voltage V in response to a first control signal RAMP The bias current is provided (at step 284) in response to the second control signal for generating a ramp voltage V RAMP The boost current is then generated, and (at step 286) a ramp voltage V is generated based on the bias current and the boost current. RAMP .

[0076] According to one embodiment, the bias current can be used to maintain or adjust the ramp voltage V RAMP potential, and the boost current can be used in a short time to boost the ramp voltage V RAMP The potential of Figure 8 In one embodiment, due to the boost current, the ramp voltage V RAMP can be raised until it has a potential equal to or higher than a preset target level, just like Figure 8 When no boost current is applied, the ramp voltage V RAMP Can be stabilized to a preset target level.

[0077] According to one embodiment, the second control signal and the first control signal may be activated at the same time, but the second control signal may have a shorter activation section than the first control signal. The second control signal may be deactivated earlier than the first control signal. For example, referring to Figure 7 , the first control signal may be a ramp enable signal Ramp_En, and the second control signal may be a boost enable signal Boost_En. Figure 4 , based on the pixel information or the original signal V outputted from the pixel 112 through the analog-to-digital conversion circuit 140 PIX In the process of outputting the output data DATA_OUTPUT, the second control signal may be activated twice before the first comparison operation and the second comparison operation. According to one embodiment, the second control signal and the first control signal may be activated in sequence.

[0078] According to one embodiment of the present disclosure, an image sensor can reduce the time taken to stabilize a ramp signal, so that the image sensor can reduce the time taken to convert a pixel signal into a digital signal.

[0079] Furthermore, since the image sensor according to one embodiment of the present disclosure can support a high frame rate, the image sensor can be embedded in a wider variety of devices for various purposes.

[0080] While the present teachings have been illustrated and described with respect to the particular embodiments, it will be apparent to those skilled in the art from this disclosure that various changes and modifications can be made without departing from the spirit and scope of the present disclosure as defined in the following claims.

[0081] CROSS-REFERENCE TO RELATED APPLICATIONS

[0082] This patent application claims the benefit of Korean Patent Application No. 10-2021-0014790, filed on February 2, 2021, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An analog-to-digital conversion circuit, the analog-to-digital conversion circuit comprising: a converter that performs a first comparison operation for sensing noise based on a reset signal and performs a second comparison operation for sensing raw data to output data obtained by removing the noise from the raw data; as well as a slope voltage generator that generates a slope voltage for the first comparison operation and the second comparison operation and outputs the slope voltage to the converter, Wherein, the ramp voltage generator comprises: a first current source, the first current source being configured to provide a bias current for generating the ramp voltage in response to a first control signal; a second current source for providing a boost current for generating the ramp voltage in response to a second control signal; and a generating circuit configured to generate the ramp voltage based on the bias current and the boost current, The second current source provides the boost current until the ramp voltage has a level higher than a target level.

2. The analog-to-digital conversion circuit according to claim 1, wherein: The converter comprises: A comparator, the comparator being used to compare the ramp voltage with the noise and the original data in sequence; a clock controller, the clock controller being configured to generate a clock signal; and A counter is configured to count the clock signal based on a result output from the comparator.

3. The analog-to-digital conversion circuit according to claim 1, wherein: The first control signal and the second control signal are activated simultaneously or sequentially, and an activation section of the second control signal is shorter than an activation section of the first control signal.

4. The analog-to-digital conversion circuit according to claim 3, wherein: The second control signal is individually activated before the first comparison operation and the second comparison operation.

5. An image sensor, comprising: A pixel array, the pixel array comprising a plurality of pixels; A driver, the driver outputting a reset signal and a transmission signal to the pixel array; a converter that performs a first comparison operation for sensing noise output from the pixel array based on the reset signal, performs a second comparison operation for sensing raw data output from the pixel array based on the transmission signal, and outputs data obtained by removing the noise from the raw data; a slope voltage generator that generates a slope voltage for the first comparison operation and the second comparison operation and outputs the slope voltage to the converter; as well as a data output circuit that collects the data output from the converter and generates image data, The ramp voltage is stabilized to the target level after being boosted above the target level by a boost current, and the boost current is provided until the ramp voltage has a level higher than the target level.

6. The image sensor according to claim 5, wherein: The ramp voltage generator comprises: a first current source, the first current source being configured to provide a bias current for generating the ramp voltage in response to a first control signal; a second current source for providing the boost current for generating the ramp voltage in response to a second control signal; and A generating circuit is configured to generate the ramp voltage based on the bias current and the boost current.

7. The image sensor according to claim 6, wherein: The first control signal and the second control signal are activated simultaneously or sequentially, and an activation section of the second control signal is shorter than an activation section of the first control signal.

8. The image sensor according to claim 6, wherein: The second control signal is activated before the first comparison operation and the second comparison operation, respectively.

9. The image sensor according to claim 5, wherein: The converter comprises: A comparator, the comparator being used to compare the ramp voltage with the noise and the original data in sequence; a clock controller, the clock controller being configured to generate a clock signal; and A counter is configured to count the clock signal based on a result output from the comparator.

10. The image sensor according to claim 5, in, The pixel array outputs the noise and the raw data on a column basis, wherein the converter includes a plurality of components for performing the first comparison operation and the second comparison operation to identify the noise and the original data based on the column output, and The ramp voltage generator provides the ramp voltage with a level having a constant slope to the converter.

11. A method for operating an image sensor, the image sensor comprising a ramp voltage generator providing a ramp voltage to a converter, the converter performing a first comparison operation for sensing noise transmitted from a pixel array and performing a second comparison operation for sensing raw data transmitted from the pixel array, the method comprising the following steps: generating a bias current for generating the ramp voltage in response to a first control signal; generating a boost current for generating the ramp voltage in response to a second control signal; as well as generating the ramp voltage based on the bias current and the boost current, The boost current is provided until the ramp voltage has a level higher than a target level, and the ramp voltage is stabilized to the target level after being boosted above the target level.

12. The method according to claim 11, wherein: The first control signal and the second control signal are activated simultaneously or sequentially, and an activation section of the second control signal is shorter than an activation section of the first control signal.

13. The method according to claim 11, wherein: The second control signal is activated before each of the first comparison operation and the second comparison operation.

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