Resistive random access memory cell integrated with a shared gate vertical field effect transistor

Abstract

A two-transistor two-resistor (2T2R) resistive random access memory (ReRAM) structure and a method of forming the same, including two vertical field effect transistors (VFETs) formed on a substrate (102), each VFET including an epitaxial region (410) located above a channel region (302) and below a dielectric cap (308). The epitaxial region (410) includes two opposite triangular protruding regions that horizontally extend beyond the channel region (302). A metal gate material (602) is disposed on and around the channel region (302). A portion of the metal gate material (602) is located between the two VFETs. A ReRAM stack is deposited in two openings (1010) adjacent to a side of each VFET opposite to the portion of the metal gate material (602) located between the two VFETs. A portion of the epitaxial region (410) that directly contacts the ReRAM stack serves as a bottom electrode of the ReRAM structure.

Description

Technical Field

[0001] The present invention generally relates to the field of magnetic storage devices, and more particularly to integrating resistive random access memory (ReRAM) devices with vertical field effect transistors (VFETs) having a shared gate. Background Art

[0002] ReRAM is one of the most promising technologies for non-volatile memory devices. Due to low power and high-speed operation, high-density CMOS-compatible integration, and high cycling durability, ReRAM technology is becoming the mainstream choice for high-density storage arrays and new in-memory computing systems.

[0003] The basic ReRAM mechanism is based on the formation and rupture of nanoscale conductive filaments typically formed between two electrodes, which results in repeatable resistance switching between a high-resistance state and a low-resistance state. A disadvantage of the ReRAM mechanism is that it relies on randomness and the position of the conductive filaments is not under control. Therefore, improved designs and techniques for forming ReRAM devices are needed. Summary of the Invention

[0004] The disadvantages of the prior art are overcome and additional advantages are provided by providing a method for forming a semiconductor device that includes forming two vertical field effect transistors on a substrate, each vertical field effect transistor including an epitaxial region located above a channel region and below a dielectric cap. The epitaxial region includes two opposing triangular protrusions that horizontally extend beyond the channel region. A metal gate material is disposed on and around the channel region, and a portion of the metal gate material is located between the two vertical field effect transistors. An interlayer dielectric layer above the metal gate material is recessed to form two openings, each opening adjacent to a side of each vertical field effect transistor that is opposite to the portion of the metal gate material located between the two vertical field effect transistors. Each opening exposes a portion of the epitaxial region of each vertical field effect transistor. A resistive random access memory stack is deposited in each opening, the resistive random access memory stack including an oxide layer directly above the exposed portion of the epitaxial region, a top electrode layer directly above the oxide layer, and a metal fill above the top electrode layer. The exposed portion of the epitaxial region serves as the bottom electrode of the resistive random access memory stack.

[0005] Another embodiment of the present invention provides a method of forming a semiconductor device, which includes forming a doped source on a substrate, forming a dummy gate on the doped source, and the dummy gate is disposed between a first spacer disposed on the doped source and a second spacer disposed on the dummy gate. Two trenches are formed in the dummy gate, the first spacer, and the second spacer to expose the doped source and grow an epitaxial layer away from the doped source in each trench to form two fins. Each fin includes a channel region extending from the doped source electrode and passing through the dummy gate. The top portion of each fin is recessed to form a dielectric cap. An epitaxial region is grown on a portion of the fin to form source / drain regions above the dummy gate and below the dielectric cap, and the epitaxial region includes two opposite triangular protruding regions that horizontally extend beyond the fin. The dummy gate is replaced with a gate stack including a metal gate material surrounding the channel region, and a portion of the gate stack is located between the two fins. The metal gate material is etched to expose the epitaxial region. An interlayer dielectric layer is formed to separate the epitaxial region from the metal gate material. Then, the interlayer dielectric layer is recessed to form two openings, and each opening exposes a portion of the epitaxial region opposite to the portion of the gate stack located between the two fins. An oxide layer is conformally deposited in each opening, and a top electrode layer is formed directly above the oxide layer.

[0006] Another embodiment of the present invention provides a semiconductor device, which includes two vertical field-effect transistors, and each vertical field-effect transistor includes an epitaxial region located above the channel region and below the dielectric cap. The epitaxial region includes two opposite triangular protruding regions that horizontally extend beyond the channel region. A metal gate material is disposed on and around the channel region, and a portion of the metal gate material is located between the two vertical field-effect transistors. An interlayer dielectric layer is located above the metal gate material and two resistive random access memory structures. Each resistive random access memory is adjacent to one side of the vertical field-effect transistor in the two vertical field-effect transistors, and this side is opposite to the portion of the metal gate material located between the two vertical field-effect transistors. Each resistive random access memory structure includes an oxide layer directly above the epitaxial region, a top electrode layer directly above the oxide layer, and a metal filler above the top electrode layer. The epitaxial region serves as the bottom electrode of the resistive random access memory structure. Description of the Drawings

[0007] The following detailed description will be best understood in conjunction with the accompanying drawings, which are given by way of example and are not intended to limit the present invention thereto, in the drawings:

[0008] Figure 1 is a cross-sectional view of a semiconductor device at an intermediate step during a method of manufacturing two vertical field-effect transistors according to an embodiment of the present invention.

[0009] Figure 2A cross-sectional view of a semiconductor device according to an embodiment of the present invention, showing a trench formed through a dielectric capping layer, a second spacer, a dummy gate, and a first spacer to expose a doped source.

[0010] Figure 3 A cross-sectional view of a semiconductor device according to an embodiment of the present invention, after growing an epitaxial layer from the doped source to form an epitaxial channel region in each trench.

[0011] Figure 4 A cross-sectional view of a semiconductor device according to an embodiment of the present invention, after removing the dielectric capping layer and forming an epitaxial region over the channel region.

[0012] Figure 5 A cross-sectional view of a semiconductor device according to an embodiment of the present invention, after removing a thin oxide layer and conformally depositing a gate dielectric material and a work function metal.

[0013] Figure 6 A cross-sectional view of a semiconductor device according to an embodiment of the present invention, after filling with a metal gate material and performing a planarization process.

[0014] Figure 7 A cross-sectional view of a semiconductor device according to an embodiment of the present invention, after partially recessing the metal gate material.

[0015] Figure 8 A cross-sectional view of a semiconductor device according to an embodiment of the present invention, after depositing an interlayer dielectric layer over the metal gate material and performing a planarization process.

[0016] Figure 9 A cross-sectional view of a semiconductor device according to an embodiment of the present invention, after forming a mask over the interlayer dielectric layer.

[0017] Figure 10 A cross-sectional view of a semiconductor device according to an embodiment of the present invention, showing after recessing a portion of the interlayer dielectric layer and the spacer.

[0018] Figure 11 A cross-sectional view of a semiconductor device according to an embodiment of the present invention after removing the mask.

[0019] Figure 12 A cross-sectional view of a semiconductor device according to an embodiment of the present invention after depositing an oxide layer.

[0020] Figure 13 A cross-sectional view of a semiconductor device according to an embodiment of the present invention after depositing an electrode.

[0021] Figure 14is a cross-sectional view of a semiconductor device after depositing a metal filler according to an embodiment of the present invention; and

[0022] Figure 15 is a cross-sectional view of a semiconductor device after forming a ReRAM contact according to an embodiment of the present invention.

[0023] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to depict specific parameters of the present invention. The drawings are intended to depict only typical embodiments of the present invention. In the drawings, like reference numerals denote like elements. Detailed Description

[0024] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be implemented in various forms. However, the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0025] For purposes of the following description, terms such as "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall refer to the disclosed structures and methods as oriented in the drawings. Terms such as "above", "overlying", "on top of", "on the top of", "located on" or "situated on top of" mean that a first element, such as a first structure, is present on a second element, such as a second structure, where an intermediate element, such as an interface structure, may be present between the first and second elements. The term "in direct contact" means that a first element (e.g., a first structure) and a second element (e.g., a second structure) are joined without any intermediate conductive, insulating, or semiconductor layer at the interface of the two elements.

[0026] It should be understood that although terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element discussed below may be referred to as a second element without departing from the scope of this concept.

[0027] To avoid obscuring the presentation of the embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be grouped together for presentation and for illustrative purposes and may not be described in detail in some instances. In other cases, some process steps or operations known in the art may not be described at all. It should be understood that the following description focuses more on the distinguishing features or elements of the various embodiments of the present invention.

[0028] A ReRAM structure typically includes a top electrode, a bottom electrode, and an oxide layer located between the two electrodes. In an oxide ReRAM, electroforming is required to form conductive filaments. This process relies on randomness, which hinders the control of the positions of the conductive filaments in the oxide ReRAM. This results in higher formation voltages as the ReRAM cells are scaled down and there is higher device variability.

[0029] In addition, due to the randomness of the electroforming process, the formed resistance states (i.e., the low resistance state (LRS) and the high resistance state (HRS)) show a wide distribution that narrows the memory window. Oxide ReRAM typically requires current-controlled field-effect transistors (FETs) to form a one-transistor one-resistor (1T1R) structure. This process is usually accompanied by a loss of device area.

[0030] Accordingly, embodiments of the present invention provide a method and related structure for fabricating a two-transistor two-resistor (2T2R) ReRAM structure, where two field-effect transistors share a metal gate. The proposed embodiments can reduce the randomness of electroforming of the conductive filaments, while making the device less susceptible to the variability of the ReRAM states, and improving the device scalability. Specifically, the proposed embodiments provide a vertically stacked 2T2R non-volatile memory cell for a field-programmable gate array (FPGA), where two oxide ReRAMs are co-integrated with two vertical field-effect transistors that share a metal gate using a portion of the top source / drain region of the VFETs as the bottom electrode of the ReRAM structure.

[0031] One way to form a two-transistor two-resistor ReRAM structure includes forming two VFET devices having a shared metal gate, each VFET device including a (faceted) epitaxial region having a protruding outer portion, forming a ReRAM stack directly above the epitaxial region of the VFET device, the ReRAM stack including an oxide layer above an electrode layer and a metal fill above the electrode layer, the oxide layer being in direct contact with the protruding outer portion of the (faceted) epitaxial region, and the protruding outer portion serving as the bottom electrode for each of the ReRAM elements. Embodiments that can form a two-transistor two-resistor ReRAM structure will be described in detail below with reference to the Figures 1-15 accompanying drawings.

[0032] Now referring to Figure 1 , a cross-sectional view of a semiconductor device 100 during an intermediate step in a method of fabricating a vertical field-effect transistor (VFET) according to an embodiment of the present invention is shown.

[0033] At this point in the manufacturing process, the semiconductor device 100 includes a dummy gate 120 and a dielectric capping layer 140 disposed on a semiconductor substrate 102 (hereinafter referred to as "substrate"). The substrate 102 includes, for example, a bulk semiconductor substrate. The substrate 102 includes one or more semiconductor materials. Non-limiting examples of suitable semiconductor materials for the substrate 102 may include silicon (Si), strained Si, silicon carbide (SiC), germanium (Ge), silicon-germanium (SiGe), silicon-germanium-carbon (SiGeC), Si alloys, Ge alloys, III-V materials (e.g., gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or aluminum arsenide (AlAs)), II-VI materials (e.g., cadmium selenide (CdSe), cadmium sulfide (CdS), cadmium telluride (CdTe), zinc oxide (ZnO), zinc selenide (ZnSe), zinc sulfide (ZnS), or zinc telluride (ZnTe)), or any combination thereof. In an embodiment, the substrate 102 may include germanium.

[0034] A doped source 108 is disposed on the substrate 102, above the counter-doped layer 104. The doped source 108 and the counter-doped layer 104 are formed on the substrate 102 by incorporating dopants into the substrate 102 or via epitaxial growth. According to an embodiment, the doped source 108 is heavily doped with a dopant, which may be a p-type dopant (e.g., boron or gallium) or an n-type dopant (e.g., phosphorus or arsenic). The counter-doped layer 104 includes a dopant different / opposite to the dopant in the doped source 108. For example, when the doped source 108 includes a p-type dopant, the counter-doped layer 104 includes an n-type dopant, and when the doped source 108 includes an n-type dopant, the counter-doped layer 104 includes a p-type dopant. The doped source 108 is heavily doped, with a dopant concentration varying between about 10 19 atoms / cm 3 to about 10 22 atoms / cm 3 The thickness of the counter-doped layer may vary in a range from about 5 nm to about 50 nm, or from about 10 nm to about 20 nm. The thickness of the doped source 108 may vary in the range of about 50 to about 250 nm, or about 100 to about 200 nm.

[0035] The dummy gate 120 is disposed between the first spacer 116 and the second spacer 118 and on the doped source 108. The first spacer 116 is deposited on the doped source 108, the dummy gate 120 is deposited on the first spacer 116, and the second spacer 118 is deposited on the dummy gate 120. The first spacer 116 and the second spacer 118 may include an insulating material, such as, for example, silicon dioxide, silicon nitride, SiOCN, or SiBCN. Other non-limiting examples of materials for the first spacer 116 and the second spacer 118 include dielectric oxides (e.g., silicon oxide), dielectric nitrides (e.g., silicon nitride), dielectric oxynitrides, or any combination thereof. The materials forming the first spacer 116 and the second spacer 118 are deposited by standard deposition processes, including, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD). The first spacer 116 and the second spacer 118 may each have a thickness varying between about 3 nm and about 15 nm or between about 5 nm and about 10 nm.

[0036] The dummy gate 120 includes a sacrificial gate material, such as amorphous silicon (aSi) or polysilicon. The sacrificial gate material may be deposited by a deposition process, including but not limited to PVD, CVD, plasma enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICP CVD), or any combination thereof. The sacrificial gate material forming the dummy gate 120 has a thickness varying between about 8 nm and about 100 nm, or between about 10 nm and about 30 nm.

[0037] The dielectric cap layer 140 is deposited on the second spacer 118 above the dummy gate 120. Non-limiting examples of materials for the dielectric cap layer 140 include silicon dioxide, tetraethyl orthosilicate (TEOS) oxide, high aspect ratio plasma (HARP) oxide, high temperature oxide (HTO), high density plasma (HDP) oxide, oxide formed by atomic layer deposition (ALD) process (e.g., silicon oxide), or any combination thereof. The dielectric cap layer 140 has a thickness in the range varying from about 30 nm to about 200 nm, or from about 50 nm to about 100 nm.

[0038] Now referring Figure 2 , a cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention is shown, which shows the formation of a trench 204 through the dielectric cap layer 140, the second spacer 118, and the dummy gate 120 to expose the first spacer 116.

[0039] The trench 204 extends from the top surface of the dielectric capping layer 140 to the top surface of the first spacer 116, thereby exposing the first spacer 116. The trench 204 is formed by performing an etching process that is selective to the material forming the first spacer 116 (which will not be substantially removed). The etching process can be, for example, reactive ion etching (RIE). As is known to those skilled in the art, multiple etching processes can be performed to form the trench 204. For example, a first etching process is performed to selectively remove a portion of the dielectric capping layer 140 relative to the material of the second spacer 118. Then, a second etching process is performed to selectively remove a portion of the second spacer 118 that is located below the portion of the trench 204 formed by the first etching process, with respect to the material of the dummy gate 120. Then, a third etching process is performed to selectively remove a portion of the dummy gate 120 that is located below the portion of the trench 204 formed by the second etching process, with respect to the material of the first spacer 116. As shown, the resulting trench 204 extends through the top surface of the dielectric capping layer 140 down to the top surface of the exposed portion of the first spacer 116. The width of the trench 204 can vary from about 3 nm to about 20 nm, or from about 5 nm to about 10 nm. The depth of the trench 204 can vary from about 50 nm to about 300 nm, or from about 100 nm to about 200 nm.

[0040] Continuing to refer Figure 2 , after forming the trench 204, the first spacer 116 can also be etched using a process that is selective to the material of the doping source 108 (which will not be substantially removed). The first spacer 116 can be etched by, for example, reactive ion etching. The exposed portion of the first spacer 116 is removed by the etching process to expose a portion of the underlying source contact layer (i.e., the doping source 108). This creates a self-aligned junction (not shown), since the source extension can grow epitaxially from the doping source 108 to the top surface of the first spacer 116, as will be described in detail below.

[0041] Then, an oxidation process can be performed on the semiconductor device 100 to oxidize the inner portion of the sidewalls of the dummy gate 120 and form a thin oxide layer 210. The oxidation can be performed by a plasma oxidation process or other oxidation processes for forming the thin oxide layer 210. In some embodiments, a portion of the first spacer 116 or the doping source 108 can also be oxidized. In such embodiments, any oxide formed in these regions is removed before performing the epitaxial growth described below in Figure 3 .

[0042] It should be noted that the above steps allow a significant reduction in the pitch between subsequently formed fins, which can be advantageous for scaling purposes. As is known to those skilled in the art, fins will subsequently be grown within each trench 204.

[0043] Referring now to Figure 3 , a cross-sectional view of a semiconductor device 100 is shown after growing an epitaxial layer from a doping source 108 to form an epitaxial channel region 302 (hereinafter referred to as "channel region") in each trench 204 ( Figure 2 ). As is known to those skilled in the art, the epitaxial growth of the channel region 302 includes epitaxial semiconductor material, and the epitaxial growth and / or deposition process is selective for formation on the semiconductor surface and does not deposit material on other surfaces, such as the thin oxide layer 210, the first spacer 116, or the second spacer 118. The epitaxial growth of the channel region 302 may extend over a dielectric capping layer 140 (not shown).

[0044] The channel region 302 can be grown using a suitable epitaxial growth process, including, for example, chemical vapor deposition (CVD) (liquid phase (LP) or reduced pressure chemical vapor deposition (RPCVD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), metalorganic chemical vapor deposition (MOCVD), or other suitable processes.

[0045] The source of the epitaxial channel material can be, for example, silicon, germanium, or a combination thereof. The gas sources for depositing the epitaxial semiconductor material may include a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source selected from silane, disilane, trisilane, tetrasilane, hexachloroethylsilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source selected from germane, digermane, halogenated germane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Combinations of these gas sources can be utilized to form an epitaxial silicon-germanium alloy layer. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used.

[0046] A planarization process is performed on the semiconductor device 100 to remove excess epitaxial growth (not shown) above the dielectric capping layer 140. The planarization process can be a chemical mechanical planarization (CMP) process. As is known to those skilled in the art, each channel region 302 constitutes the channel region of a subsequently formed vertical field effect transistor.

[0047] Subsequently, the channel region 302 can be partially recessed and filled with a dielectric material to form a dielectric cap 308. Specifically, the channel region 302 is partially recessed to a level that is still within the dielectric capping layer 140 and above the second spacer 116. The channel region 302 is recessed by using, for example, a reactive ion etching or wet etching process.

[0048] A groove (not shown) formed over the channel region 302 is filled with a dielectric material to form a dielectric cap 308 over the channel region 302. The dielectric material for forming the dielectric cap 308 can be a dielectric oxide (e.g., silicon oxide), a dielectric nitride (e.g., silicon nitride), a dielectric oxynitride, or any combination thereof. The dielectric material for forming the dielectric cap 308 is deposited by a standard deposition process, such as CVD or PVD. After deposition, the excess dielectric material is planarized, e.g., by CMP.

[0049] Now referring to Figure 4 , a cross-sectional view of a semiconductor device 100 is shown after removing the dielectric capping layer 140 and forming an epitaxial region 410 over the channel region 302 to form the source / drain regions of a first vertical field effect transistor (VFET1) and a second vertical field effect transistor (VFET2) in accordance with an embodiment of the present invention.

[0050] For VFET1 and VFET2, the epitaxial region 410 is disposed between the dielectric cap 308 and the channel region 302. As is known to those skilled in the art, a portion of the channel region 302 on the second spacer 118 may be recessed along the sidewalls before forming the epitaxial region 410. The epitaxial region 410 forms the source / drain regions of VFET1 and the source / drain regions of VFET2. The epitaxial growth of the epitaxial region 410 can be performed as described above in Figure 3 .

[0051] It should be noted that the diamond facet effect observed in the epitaxial region 410 is a result of different semiconductor growth along different crystal planes. The faceted epitaxial growth eventually slows down to a very low growth rate and "terminates" at the crystal plane group with the slowest growth rate (i.e., the <111> plane), and thus the resulting semiconductor structure has a surface oriented in such a crystal plane with the slowest semiconductor growth rate. As shown, the epitaxial region 410 includes two (opposite) triangular protruding regions or portions (bounded by the <111> plane), which horizontally extend beyond the channel regions 502 in each of VFET1 and VFET2. As will be described below, this geometry can enhance the hole / electron mobility towards the protruding or tip regions, which is advantageous for ReRAM performance. Various processing parameters, including growth temperature, growth pressure, flow rate of the processing gas, etc., can be easily adjusted to adjust the relative growth rates along different sets of crystal planes, thereby controlling the surface orientation of the resulting semiconductor structure.

[0052] Continuing to refer to Figure 4, spacers 420 are deposited on opposite sides of each epitaxial region 410 to protect the epitaxial region(s) 410 during subsequent process steps. The spacers 420 are also disposed on the sidewalls of the dielectric cap 308. The spacers 420 comprise an insulating material such as a dielectric oxide (e.g., silicon oxide), a dielectric nitride (e.g., silicon nitride), a dielectric oxynitride, or any combination thereof. The spacer 420 material is deposited by a standard deposition process such as CVD or PVD. The spacer material can be etched by a dry etching process (e.g., an RIE process) such that it covers the epitaxial region 410 and is removed from the surfaces of the dielectric cap 308 and the second spacer 118. The spacers 420 have a width that varies from about 5 nm to about 50 nm, or from about 15 nm to about 30 nm.

[0053] After forming the spacers 420, portions of the second spacer 118 and the dummy gate 120 are recessed to remove portions that horizontally extend beyond the spacers 420. An etching process that is selective to the first spacer 116 (substantially no removal) is performed. The etching process can be a dry etching process such as an RIE process.

[0054] The remaining portion of the dummy gate 120 can be removed by a wet etching process such as a process including hot ammonia.

[0055] Now referring Figure 5 , a cross-sectional view of a semiconductor device 100 is shown in accordance with an embodiment of the present invention after removing the thin oxide layer 210 and conformally depositing the gate dielectric material 504 and the work function metal 508. As is known to those skilled in the art, the gate dielectric material 504 and the work function metal 508 form part of a gate stack that replaces the dummy gate 120 in each of the VFET1 and VFET 2. The gate dielectric material 504 and the work function metal 508 are disposed on the remaining portion of the second spacer 118 below the first spacer 116, the channel region 302, and the epitaxial region 410.

[0056] (Multiple) gate dielectric materials 504 can be dielectric materials having a dielectric constant greater than 3.9, 7.0, or 10.0. Non-limiting examples of suitable materials for the gate dielectric material 504 include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials (having a dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, aluminum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. High-k materials can also include dopants such as lanthanum and aluminum. The gate dielectric material 504 can be formed by suitable deposition processes including, for example, CVD, PVD, PECVD, ALD, evaporation, chemical solution deposition, or other similar processes. The thickness of the gate dielectric material 504 can vary depending on the deposition process and the composition and amount of the high-k dielectric material used.

[0057] A work function metal 508 can be disposed on top of the gate dielectric material 504. The type of work function metal 508 depends on the type of transistor. Non-limiting examples of suitable work function metals 508 include p-type work function metal materials and n-type work function metal materials. P-type work function materials include components such as ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, or any combination thereof. N-type metal materials include compositions such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or any combination thereof. The work function metal 508 can be deposited by suitable deposition processes such as CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation, and sputtering.

[0058] Then, the gate dielectric material 504 and the work function metal 508 are recessed to remove portions that horizontally extend beyond the spacer 420, as shown. An etching process that is selective to the first spacer 116 (substantially not removed) is performed. For example, the etching process can be an anisotropic etching process.

[0059] Now refer to Figure 6, which shows a cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention after filling with a metal gate material 602 and performing a planarization process on the metal gate material 602. The metal gate material 602 is a conductive gate metal deposited on a gate dielectric material 504 and a work function metal 508 to form a gate stack for each of the VFET 1 and VFET 2. In this embodiment, the metal gate material 602 is deposited between the VFET 1 and VFET 2 such that a portion of the metal gate material 602 is shared by the two field effect transistors, which, as described above, helps to improve the device scalability.

[0060] Non-limiting examples of suitable conductive metals include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive metal forming the metal gate material 602 can be deposited by a suitable deposition process, such as CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation, and sputtering. A planarization process, such as CMP, is performed to polish the surface of the metal gate material 602.

[0061] Now refer to Figure 7 , which shows a cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention after partially recessing the metal gate material 602. The metal gate material 602 is partially recessed by an etching process, such as a reactive ion etching process.

[0062] Now refer to Figure 8 , which shows a cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention after depositing an interlayer dielectric (ILD) layer 804 on the metal gate material 602 and performing a planarization process. The ILD layer 804 can be formed of, for example, a low-k dielectric material (k < 4.0), including but not limited to silicon oxide, spin-on glass, flowable oxide, high density plasma oxide, borophosphosilicate glass (BPSG), or any combination thereof. The ILD layer 804 is deposited by a deposition process, including but not limited to CVD, PVD, PECVD, ALD, evaporation, chemical solution deposition, or similar processes.

[0063] Now refer to Figure 9, which shows a cross-sectional view of a semiconductor device 100 after forming a mask 920 according to an embodiment of the present invention. The mask 920 is deposited on the top surface of the semiconductor device 100. As shown, the mask 920 covers the area between the VFET 1 and VFET 2, including the central portion of the ILD layer 804 above the metal gate material 602. The mask 920 may also cover the outer regions of the first ILD layer 804. A portion of the spacer 420 of each vertical transistor and a portion of the first ILD layer 804 remain uncovered. The mask 920 can be made of a material resistant to the etching process, such that the portions of the semiconductor device 100 covered by the mask 920 can be protected. The mask 920 is deposited to protect the covered surface when the semiconductor device 100 is further processed to form Figure 14 the ReRAM structure shown.

[0064] Now referring to Figure 10 , which shows a cross-sectional view of the semiconductor device 100 after recessing portions of the ILD layer 804 and the spacer 420. The portions of the ILD layer 804 and the spacer 420 not covered by the mask 920 are recessed to create openings 1010 in the semiconductor device 100. As shown, the openings 1010 expose portions of the epitaxial regions 410 in each of the VFET 1 and VFET 2. The openings 1010 may also expose the sidewalls of the second spacer 118 and the dielectric caps 308 in each of the VFET 1 and VFET 2.

[0065] By performing an etching process that selectively etches (substantially without removing) the spacer 420 and the dielectric cap 308, the portions of the ILD layer 804 adjacent to the VFET 1 and VFET 2 not covered by the mask 920 can be removed. The etching process can be, for example, reactive ion etching. After recessing the first ILD layer 804, the portions of the spacer 420 not protected by the mask 920 (i.e., the regions of the spacer 420 on the opposite side of the shared portion of the metal gate material 602) can be removed from the VFET 1 and VFET 2, respectively, as shown. According to an embodiment, any suitable etching process can be used to remove the portions of the spacer 420 not covered by the mask 920. The openings 1010 can then be backfilled with other materials to integrate the ReRAM structure with each of the VFET 1 and VFET 2, as will be described in detail below.

[0066] After removing the exposed portions of the spacer 420, the mask 920 can be removed by performing any suitable etching technique known in the art, as Figure 11 shown.

[0067] Now referring to Figure 12, a cross-sectional view of a semiconductor device 100 after depositing an oxide layer 1220 according to an embodiment of the present invention is shown. The oxide layer 1220 is conformally deposited in an opening 1010 ( Figure 11 ) along the exposed sidewalls of the ILD layer 804 and the exposed surfaces of the epitaxial regions 410, the second spacers 118, and the dielectric caps 308 in each of the VFET 1 and VFET 2. The oxide layer 1220 can be conformally deposited using known deposition techniques, such as ALD. The oxide layer 1220 can be made of a metal oxide material or a high-k material. Non-limiting examples of suitable materials for the oxide layer 1220 can include titanium oxide, tantalum oxide, and hafnium oxide. The oxide layer 1220 serves as the dielectric layer of the ReRAM structure in Figure 15 , separating the epitaxial region 410 from the subsequently formed top electrode.

[0068] Now referring to Figure 13 , a cross-sectional view of a semiconductor device 100 after depositing an electrode layer 1310 according to an embodiment of the present invention is shown. The electrode layer 1310 can also be referred to as the top electrode of the ReRAM structure. The electrode layer 1310 is conformally deposited on top of the oxide layer 1220. The electrode layer 1310 can be deposited using known deposition techniques, such as ALD. The electrode layer 1310 can be made of materials such as titanium nitride and aluminum-doped titanium nitride. The electrode layer 1310 serves as the top electrode of the subsequently formed ReRAM structure, while the epitaxial region 410 has two functions. The epitaxial regions 410 in the VFET 1 and VFET 2 are the top source / drain regions of each VFET, and the doped sources 108 serve as the bottom source / drain of the VFET 1 and VFET 2, respectively. The epitaxial region 410 is also the bottom electrode in the ReRAM structure.

[0069] Now referring to Figure 14 , a cross-sectional view of a semiconductor device 100 after depositing a metal fill 1460 according to an embodiment of the present invention is shown. After the electrode layer 1310 is conformally deposited directly above the oxide layer 1220, the opening 1010 ( Figure 11 ) is filled with the metal fill 1460, and then the semiconductor device 100 undergoes a CMP process. The metal fill 1460 can be made of a suitable low-resistivity metal, such as tungsten or copper. The metal fill 1460 serves as an electrical conductor between the electrode layer 1310 and the contacts formed on the top surface of the metal fill 1460. The oxide layer 1220, the electrode layer 1310 above the oxide layer 1220, and the metal fill 1460 above the electrode layer 1310 form a ReRAM stack for two ReRAM structures ReRAM1 and ReRAM2 that are co-integrated with the VFET 1 and VFET 2, respectively.

[0070] Now referring toFigure 15 , which shows a cross-sectional view of a semiconductor device 100 after forming ReRAM contacts 1520 according to an embodiment of the present invention. It should be noted that although not depicted in the figure, source / drain contacts and gate contacts may also be formed in the semiconductor device 100. The processes for forming ReRAM, source / drain, and gate contacts are standard and well known in the art. The process generally includes forming trenches (not shown) to the target regions (i.e., metal fill 1460, doped source 108, and metal gate material 602) and filling the trenches with a conductive material or a combination of conductive materials.

[0071] The source / drain contacts (not shown) may extend through the first ILD layer 804 and the first spacer 116 to the doped source 108 and are formed within trenches (not shown). The conductive material filling the source / drain contacts includes conductive metals such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive material may be deposited by a suitable deposition process such as CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation, or sputtering. A planarization process, such as CMP, is performed to remove any conductive material from the surface of the ILD layer 804.

[0072] The gate contacts (not shown) extend from the surface of the ILD layer 804 through the metal gate material 602. The conductive material forming the gate contacts may be a conductive metal deposited by an appropriate deposition process such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof, and the deposition process is, for example, CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation, or sputtering. A planarization process, such as CMP, is performed to remove any conductive material from the surface of the ILD layer 804.

[0073] The ReRAM contacts 1520 may then be formed above and in direct contact with the metal fill 1460. The ReRAM contacts 1520 may be made of a conductive metal, including, for example, aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof.

[0074] Accordingly, embodiments of the present invention provide a semiconductor device and a method of manufacturing the same. The semiconductor device includes two ReRAM elements (ReRAM1 and ReRAM2), each vertically integrated on the outer top of a first VFET device (VFET1) and the outer top of a second VFET device (VFET2). The first and second VFET devices share a metal gate, which can significantly reduce (scale down) the pitch between the devices. In the proposed embodiments, each memory cell in the final semiconductor device includes two resistive memory elements and two selectors (2T2R), where oxide ReRAM is formed in the faceted epitaxial drain region to enhance the electric field at the tip of the (triangular) faceted epitaxial region, which also allows for a reduced device footprint. The bottom electrode of each resistive memory element (ReRAM1 and ReRAM2) is the triangular protrusion of the top source / drain region of each vertical field effect transistor. More specifically, the epitaxial region 410 includes the results of different growth of diamond-shaped facets along different crystal planes, which results in two opposite protrusion regions of the epitaxial region 410 being defined by the <111> plane. The proposed semiconductor device also includes a channel region made of single-crystal semiconductor material, which further enhances the device performance.

[0075] The description of the various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein were chosen to best explain the principles of the embodiments, the practical application, or the technical improvement over technologies found in the marketplace, or to enable other ordinary skilled artisans in the art to understand the embodiments disclosed herein.

[0076] In a preferred embodiment of the present invention, a method of forming a semiconductor device is provided, which includes: forming a doped source on a substrate; forming a dummy gate on the doped source, the dummy gate being disposed between a first spacer disposed on the doped source and a second spacer disposed on the dummy gate; forming two trenches in the dummy gate, the first spacer, and the second spacer, each trench exposing the doped source; epitaxially growing an epitaxial layer from the doped source in each trench to form two fins, each fin including a channel region extending from the doped source and passing through the dummy gate; recessing a top portion of the fin to form a dielectric cap; epitaxially growing an epitaxial region on a portion of the fin to form source / drain regions above the dummy gate and below the dielectric cap, the epitaxial region including two relatively triangular-shaped protruding regions horizontally extending beyond the fin; replacing the dummy gate with a gate stack including a metal gate material surrounding the channel region, wherein a portion of the gate stack is located between the two fins; etching the metal gate material to expose the epitaxial region; forming an interlayer dielectric layer separating the epitaxial region from the metal gate material; recessing the interlayer dielectric layer to form two openings, each opening exposing a portion of the epitaxial region opposite to the portion of the gate stack located between the two fins; and conformally depositing an oxide layer in each opening; and forming a top electrode layer directly above the oxide layer. The method preferably further includes: depositing a metal filler above the top electrode layer, wherein the oxide layer, the top electrode layer, and the metal filler include a resistive random access memory structure disposed on an exposed portion of the epitaxial region opposite to the portion of the gate stack located between the two fins. The exposed portion of the epitaxial region preferably serves as a bottom electrode of the resistive random access memory structure. The method preferably further includes: forming an anti-doped layer between the substrate and the doped source, wherein the doped source includes a first dopant, and the anti-doped layer includes a second dopant different from the first dopant. The method preferably further includes: forming a source / drain contact contacting the doped source. The method preferably further includes: forming a gate contact contacting the gate stack. The method preferably further includes: forming a resistive random access memory contact contacting a top portion of the metal filler.

Claims

1. A method of forming a semiconductor device, comprising: Forming two vertical field effect transistors on a substrate, each of the vertical field effect transistors including an epitaxial region located above a channel region and below a dielectric cap, the epitaxial region including two opposite protruding regions of a triangular shape that horizontally extend beyond the channel region; Depositing a metal gate material, the metal gate material being disposed on and around the channel region, wherein a portion of the metal gate material is located between the two vertical field effect transistors; Depositing an interlayer dielectric layer over the metal gate material; Recessing the interlayer dielectric layer to form two openings, each opening adjacent to a side of each vertical field effect transistor that is opposite to the portion of the metal gate material located between the two vertical field effect transistors, wherein each opening exposes a portion of the epitaxial region of each vertical field effect transistor; And Depositing a resistive random access memory stack in each of the two openings, the resistive random access memory stack including an oxide layer directly over the exposed portion of the epitaxial region, a top electrode layer directly over the oxide layer, and a metal fill located over the top electrode layer, wherein the exposed portion of the epitaxial region serves as a bottom electrode of the resistive random access memory stack.

2. The method according to claim 1, wherein forming the two vertical field effect transistors further comprises: Forming a doped source on the substrate; Forming the channel region extending from the doped source; Forming the dielectric cap over the channel region; And Forming the epitaxial region on a portion of the channel region.

3. The method according to claim 2, further comprising: Forming an anti-doped layer between the substrate and the doped source, wherein the doped source includes a first dopant and the anti-doped layer includes a second dopant different from the first dopant.

4. The method according to claim 1, further comprising: Etching the resistive random access memory stack to prepare for contact formation.

5. The method according to claim 4, further comprising: Forming resistive random access memory contacts that contact top portions of the metal fills in each of the two vertical field effect transistors.

6. The method according to claim 2, further comprising: Forming source / drain contacts that contact the doped source.

7. The method according to claim 1, further comprising: Forming gate contacts that contact the metal gate material.

8. A semiconductor device, comprising: Two vertical field effect transistors, each vertical field effect transistor including an epitaxial region located above a channel region and below a dielectric cap, the epitaxial region including two opposite protruding regions of a triangular shape that horizontally extend beyond the channel region; A metal gate material, which is disposed on and around the channel region, wherein a portion of the metal gate material is located between the two vertical field effect transistors; An interlayer dielectric layer over the metal gate material; And Two resistive random access memory structures, each resistive random access memory being adjacent to a side of the vertical field effect transistor of the two vertical field effect transistors opposite to a portion of the metal gate material located between the two vertical field effect transistors, wherein each resistive random access memory structure of the resistive random access memory structures includes an oxide layer directly above the epitaxial region, a top electrode layer directly above the oxide layer, and a metal filler above the top electrode layer, wherein the epitaxial region serves as the bottom electrode of the resistive random access memory structure.

9. The semiconductor device according to claim 8, wherein, The two vertical field effect transistors further include: A doped source on the substrate, the channel region extending from the doped source.

10. The semiconductor device according to claim 9, further comprising: An anti-doping layer between the substrate and the doped source, wherein the doped source includes a first dopant and the anti-doping layer includes a second dopant different from the first dopant.

11. The semiconductor device according to claim 10, further comprising: A source / drain contact contacting the doped source.

12. The semiconductor device according to claim 8, further comprising: A gate contact contacting the metal gate material.

13. The semiconductor device according to claim 8, further comprising: A resistive random access memory contact contacting a top portion of the metal filler in each vertical field effect transistor.

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