Low power wake-up mode detection for multiple data streams

Abstract

This application describes a technique for wake-up pattern-data stream correlation by a detector to provide a trigger condition for a microcontroller in a wake-up receiver (WuRX). For example, the detector (118) includes a packet layer (200) having a plurality of index registers (202) that are updated by samples of a data stream (208). A sample clock [204] is coupled to each of the plurality of index registers to independently activate each of the plurality of index registers. A shared comparator (212) then compares the updated plurality of index registers to a corresponding shift register (210) that is initialized with a rotating wake-up pattern bit (220). Based on a number of matches, the detector generates a trigger signal (228) that facilitates a change from a low-power mode of operation to a high-power mode of operation.

Description

Background Art

[0001] Radio Frequency Identification (RFID) uses radio waves to read and capture information stored on tags attached to objects. Tags can be read from several feet away and do not need to be within direct line of sight of a reader to be tracked.

[0002] RFID is used in many applications, such as identification in passive or wireless keyless entry systems. In such applications, the power or energy resources available for wireless keyless entry identification are limited. Therefore, it is common for RFID transponders to monitor received radio frequency signals and determine whether they contain a specific wake-up pattern. To this end, RFID transponders include a wake-up pattern mechanism that continuously monitors incoming signals from multiple sources. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The detailed description is described with reference to the accompanying drawings. In the drawings, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears. Like numerals are used throughout the drawings to represent like features and components.

[0004] Figure 1 is an example scenario implementing a device that transitions from a low power mode to a high power mode of operation based on detected data flow as described herein.

[0005] Figure 2 An example implementation of a detector performing correlation between wake-up pattern bits and multiple data streams as described herein is illustrated.

[0006] Figure 3 An example detector implementing multiple oversampling operations as described herein is illustrated.

[0007] Figure 4 An example detector that facilitates area optimization with multiple oversampling operations as described herein is illustrated.

[0008] Figure 5 is an example flow chart illustrating an example method for detecting a data flow that facilitates power conversion in a microcontroller as described herein. Summary of the Invention

[0009] This article describes a power and area optimization technique for performing wake-up mode-data flow correlation by a detector to provide a trigger condition for waking up a microcontroller in a receiver (WuRX). For example, the trigger condition generates a change from a low-power operating mode to a high-power operating mode in the microcontroller associated with the detector. DETAILED DESCRIPTION

[0010] In an embodiment, the detector includes a plurality of “N” data packet layers, where each data packet layer includes a plurality of “M” index registers (“M” and “N” are integers), where “M” is the number of wake-up pattern bits and “N” is the number of data streams (which is a product of the number of antennas multiplied by the number of demodulators from the transceiver). For example, 3 antennas * 12 demodulators. As further discussed below, “N” means the number of data layers. Each data packet layer is coupled to “M” comparators, where the “M” comparators can be shared by the plurality of “N” data packet layers.

[0011] To update the index registers, a clock gate on each index register is used to independently activate the index register to sample the data stream. The updated index register will be compared to the corresponding shift register by the corresponding comparator. Based on the matching results from the plurality of “M” comparators, a trigger condition can be generated.

[0012] Figure 1 is an example scenario 100 of implementing a device that transitions from a low power mode to a high power mode of operation based on a detected data stream as described herein. As shown, a vehicle 102 is associated with a vehicle base station 104 that includes a control unit 106, a low frequency (LF) transceiver unit 108, and an ultra-high frequency (UHF) receiver unit 110. A device (i.e., a wireless key device 112) includes an analog front end receiver 114, a microcontroller 116 with a detector 118, and a UHF transmitter 120. For example, the wireless key device 112 is a dedicated device for opening a vehicle door and / or starting an engine of the vehicle 102.

[0013] As an example, the control unit 106 is configured to control a keyless entry and engine ignition procedure of the vehicle 102 to which the vehicle base station 104 is attached. The control unit 106 can have different access rights to the entry and engine ignition. In this regard, different wake-up patterns as described herein can be used to correspond to different access conditions.

[0014] In an embodiment, the control unit 106 transmits a low-frequency (LF) interrogation signal. The LF interrogation signal comprises a data stream transmitted via the LF transceiver 108 to the wireless key device 112. In certain embodiments, the data stream is a word consisting of a bit pattern (e.g., 32 bits), where the bit pattern represents the number of index registers (designated "M"), as discussed further below. The analog front-end receiver 114 may include three antennas and 12 demodulators, which, as discussed further below, represent the number of data layers represented by "N." This means 1,152 (i.e., 32 bits * 3 antennas * 12 demodulators) toggle bits in the data layer. Due to oversampling, as discussed further below, the number of toggle bits is increased. For example, if the oversampling is 4 times, the number of toggle bits is 4,608 (4 times oversampling * 1,152 bits). The wireless key device 112, and in particular, the detector 118, receives the demodulated data stream via the analog front-end receiver 114. The detector 118 compares the received demodulated data stream to the wake-up mode bit and, based on the comparison, sends a trigger signal to the microcontroller 116. During this period, the wireless key device 112 receives the data stream of the LF interrogation signal in a first operating mode that uses a relatively minimal amount of power as described herein.

[0015] For example, the microcontroller 116 operates in a first operating mode and will remain in this mode until a trigger signal is received from the detector 118. In this example, the trigger signal is used to change the operating mode of the microcontroller from the first operating mode to a second operating mode, which includes a higher power consumption compared to the first operating mode.

[0016] In an embodiment, the detector 118 receives and processes the demodulated data stream by comparing the sampled data stream with a predefined wake-up mode bit. Based on the comparison, the detector 118 generates a trigger signal that is received by the microcontroller 116. The microcontroller 116 will then switch to the second operating mode.

[0017] In the second operating mode, the microcontroller 116 transmits control signals to the vehicle base station 104 via the UHF transmitter 120 (i.e., 315 MHz for North American vehicles and 433.92 MHz for European and Asian vehicles). For example, these control signals are received and used by the control unit 106 to perform actions on the vehicle 102, such as opening a vehicle door, starting the engine, etc.

[0018] The wireless key device 112 may be a dedicated wireless key configured for the vehicle 102, and in particular, the associated vehicle base station 104. In various operating scenarios, the wireless key device 112 receives multiple data streams, such as other LF interrogation signals from nearby vehicles, wireless fidelity (Wi-Fi) signals, other ambient noise, etc. In such cases, the wireless key device 112 (and in particular, the detector 118) demodulates the multiple data streams at low power and performs wake-up pattern and data stream correlation to determine a specific data stream that matches a pre-configured wake-up pattern bit associated with the vehicle base station 104.

[0019] In response to the received data stream matching the predefined wake-up pattern bits, the wireless key device 112 is triggered to operate in the second operating mode.

[0020] Figure 2 An example implementation of a detector 118 as described herein is illustrated that performs correlation between a wake-up pattern bit and a plurality of data streams. Figure 2 In the described operation, no oversampling occurs.

[0021] As shown, detector 118 includes multiple data packet layers 200A through 200N. Each of these "N" data packet layers 200 includes multiple index registers 202A through 202M, where "M" and "N" are integers. As discussed, "M" is the number of bits in the bit pattern of the data stream. For example, the bit pattern may be 32 bits, and "M" is 32. As discussed, "N" is the number of antennas multiplied by the number of demodulators at analog front-end receiver 114. "N" represents the number of data layers. There are "M*N" index registers 202A through 202M depicted, as well as "M*N" toggle bits. Therefore, if there are three antennas and 12 demodulators at analog front-end receiver 114, the value of "N" would be 36 (i.e., 3*12), and there would be 36 data layers. Therefore, there would be "M*N" toggle bits and index registers 202. In this example, 32*36 or 1152 toggle bits and index register 202 .

[0022] As depicted, for certain embodiments, sampling clock 204 is connected to each of the "M*N" index registers 202 using a separate clock input 206. Sampling clock 204 operates at a specific bit clock frequency and provides separate and continuous clock inputs 206 at the specific bit clock frequency. In other words, sampling clock 204 provides a clock input 206A to index register 202A, and then provides another clock input 206B to index register 202B, thereby continuously providing a clock input 206M to register 202M for each data layer 200 (i.e., 200A to 200N). Index register 202 receives data, with the register input of index register 202 connected to the data 208 of each data layer 200 (i.e., 200A to 200N).

[0023] Furthermore, detector 118 includes a plurality of wake-up pattern shift registers 210A through 210M. The number of wake-up pattern shift registers 210 is equal to the number of index registers 202 for packet layer 200. In other words, if there are "M" index registers 202 for packet layer 200, then there are also "M" wake-up pattern shift registers 210. The wake-up bit pattern length can vary to support specific data stream words. In other words, if the data stream word contains 16 bits instead of 32 bits, then the wake-up pattern supports 16 bits, and "M" will be 16.

[0024] Wake-up mode shift registers 210A through 210M are coupled to comparators 212A through 212M, respectively. The output of each comparator 212 is received by a multiplexer 214. In other words, multiplexer 214A receives output 216A, multiplexer 214B receives output 216B, and so on, multiplexer 214M receives output 216M. Multiplexers 214A through 214M receive corresponding outputs 216A through 216M from each of data layers 200A through 200N, multiplex outputs 216A through 216M, and provide corresponding outputs 218A, 218B, through 218M. Comparator 212 is used to compare the data stream bits of index register 202 with the wake-up mode bits 220A through 220M of shift register 210. Specifically, comparator 212 compares outputs 218A through 218M with bits 220A through 220M of shift register 210. Each of these "M" awake mode shift registers 210A through 210M is coupled to a bit clock 222 that provides a bit clock signal 224A through 224M, respectively.

[0025] The "M" wake-up pattern shift registers 210A to 210M are initialized to store rotated wake-up pattern bits 220A to 220M. After initialization, the wake-up pattern bits 220A to 220M rotate through the shift registers 210A to 210M for each bit clock 224A to 224M from the bit clock 222. The initial wake-up pattern bits 226 are provided as data 228 from a memory or storage device (not shown), which may be part of the detector 118 or external to the detector 118. The bit clock 222 may provide an enable bit signal 230. Multiplexers 232A to 232M support the rotation or initialization of the wake-up pattern bits 220A to 220M. Output signals 234A to 234M are provided to the inputs of the registers 210A to 210M, respectively.

[0026] The rotation or shifting of the wake-up pattern bits 220A through 220M is performed to support proper comparison of the bits in the data stream with the wake-up pattern. In other words, if the wake-up pattern bits 220A through 220M are not followed by the data stream bits, a proper comparison cannot be performed. The data stream 208 is continuously received according to each bit clock frequency determined by the sampling clock 204. As the data stream 208 is continuously received, the wake-up pattern bit pattern is rotated or shifted. For example, a first bit value is shifted to a second bit value, and the second bit value is shifted to a subsequent bit value, until the last bit value is shifted to the first bit value. In some embodiments, variable pattern lengths for the wake-up pattern are supported. In other words, wake-up patterns of different bit lengths can be supported.

[0027] For example, "M" wake-up pattern bits 220A to 220M are stored at "M" wake-up pattern shift registers 210A to 210M. In this example, the "M" wake-up pattern bits 220A to 220M are rotated after each bit clock signal 224A to 224M from the bit clock 222. This rotation updates the contents of each shift register 210A to 210M at the same frequency after each bit clock signal 224A to 224M. For the depicted operation, because the clock frequency phase shift of the sampling clock 204 and the bit clock 222 is the same for the operation, the contents of the "M*N" index registers 202 are also updated simultaneously.

[0028] Each of the M*N index registers 202 can be independently controlled or activated to sample the data stream 208 using the clock gate 206. The sampling of the data stream 208 by the M*N index registers 202 is synchronized with the bit clock from the bit clock 222. That is, as the M wake-up pattern bits 220A through 220M are rotated or shifted at the M wake-up pattern shift registers 210, the contents of the M*N index registers 202 are updated. In other words, since the data 208 is streamed at the same frequency as the bit clock 222, the comparison of the wake-up pattern bits 218 with the data stream bits of the data stream 208 is properly performed by ensuring that the corresponding wake-up pattern bits 220A through 220M are rotated or shifted. In an embodiment, the contents of the M*N index registers 202 are updated by the clock gate 206. In this regard, power savings may be achieved during data storage because not all of the “M*N” index registers 202 are switched during every bit clock on the bit clock 222 .

[0029] In one embodiment, "M" comparators 212 are configured to compare "M" wake-up pattern bits 220A through 220M with the corresponding contents of "M" index registers 202. After a complete cycle of the wake-up pattern rotation, the index registers 202 are updated one by one and a new cycle begins. Because the wake-up pattern comparison operation occurs at each bit clock 222, combinations of wake-up patterns are used for data correlation while the wake-up pattern rotates. Thus, the index registers are considered static, while the wake-up patterns are dynamic. For example, at bit clock 222, comparator 212A compares the value of shift register 210A with the value of index register 202A for packet layer 200A; comparator 212B compares the value of shift register 210B with the value of index register 202B for the same packet layer 200A; and so on. These comparisons performed on packet layer 200A are independent of the comparisons performed on each of the other packet layers 200B-200N. In other words, the "M" comparators 212 are placed "N" times to independently operate the "N" packet layers. For each packet layer, the "M" comparators 212 are placed "N" times and compared at the bit clock 222.

[0030] After the "M" comparators 212 perform the above comparisons, the detector 118 utilizes a trigger device 236 to determine the number of matches between the "M" rotating wake-up pattern bits and the sampled data stream 208 from the "M*N" index registers 202. In other words, a match is the number of bits in the sampled data stream 208 that match the wake-up pattern bits 220A through 220M. The comparators 212 performing the match output a "1" for a match or a "0" for a mismatch. The aggregate value of the comparators provides a "threshold" value to the trigger device 236. Based on the number of matches, the trigger device 236 sends a trigger signal 238 to the microprocessor 116. For example, as described herein, the trigger signal 238 facilitates a transition from a first, low-power operating mode to a second, high-power operating mode.

[0031] Figure 3 An example detector 118 is illustrated that implements a multiple oversampling operation as described herein. In particular, for example, the detector 118 depicted is implementing a double or two-time oversampling operation to illustrate the multiple oversampling operation. In other words, for two oversampling, there is a phase shift of 2π / 2 or π. In other embodiments, additional oversampling may be performed, such as four-time oversampling, where the phase shift is 2π / 4 or π / 2. For two oversampling, two sampling clocks are implemented that operate at different times or phases. In other words, for two or two oversampling, sampling is performed at one time or phase, and another sampling is performed at another time or phase (e.g., π for two oversampling and π / 2 for four oversampling). As will be discussed further, the number of correct matches of the received data stream bits to the wake-up pattern bits is compared.

[0032] Oversampling operations as described herein include a sampling clock frequency that is a multiple of the bit clock frequency (i.e., the frequency of bit clock 222). For example, in the depicted double oversampling (i.e., twice oversampling) operation, sampling clocks 204A and 204O (i.e., two sampling clocks) are used. That is, sampling clock 204A is used for data layer 200, and sampling clock 204O is used for data layer 304. Sampling clock 204A operates at a different frequency / phase than sampling clock 204O. In this simplified example, double oversampling is described, and two sampling clocks 204A and 204O are implemented. Thus, in a four-times oversampling implementation, four sampling clocks operating at different frequencies / phases are used. "0" indicates the number of oversamplings and is an integer.

[0033] In certain embodiments, an index register 302 is added to each of the packet layers 200A-200N. The index register 302 is used to initiate reception of the data stream bits 208 and is enabled by the sampling clock 204 (i.e., the receive enable signal 206). That is, index register 302A is added to packet layer 200A, index register 302B (not shown) is added to packet layer 200B, and so on, up to 302N (not shown) is added to packet layer 200N. Thus, for "N" packet layers 200, there are a total number of "(M+1)*N" index registers. Each of the index registers 302 is connected to the sampling clock 204A, and the "M" index registers 202 for each packet layer 200 are connected to the bit clock 222.

[0034] Figure 3 Further illustrated is another set of independent data packet layers 304A through 304N for double or double oversampling operation as described herein. Each of these "N" data packet layers 304 includes a plurality of index registers 306A-306M. Index registers 308A through 308N (not shown) are added to data packet layers 304A through 304N, respectively. That is, for a set of independent "N" data packet layers 304, there are "(M+1)*N" depicted index registers. Each of the index registers 308 is connected to the sampling clock 204O via a clock gate 310, while each of the plurality of index registers 306A-306M is connected to the bit clock 224 via a clock gate 310.

[0035] Index registers 302 and 308 are used in conjunction with sampling clock 204 for oversampling implementations. Index registers 202 and 306 operate in conjunction with bit clock 222. This is because a comparison is performed between wake-up pattern register 202 and index register 306 within a bit clock 222 cycle. Direct updates using sampling clock 204 would corrupt the comparison.

[0036] For oversampling, index registers 302 and 308 are implemented to receive data 208. In contrast, for no oversampling, data 208 can be received directly by index registers (e.g., index registers 202 and 306). In an embodiment, at the first sampling clock 204A, index register 302 samples data 208 and updates accordingly. Simultaneously, sampled data from register 302 is uploaded to index register 202, and sampled data from register 308 is uploaded to index register 306. This occurs "O*N" times per bit clock 222 at one of the "M" index registers, where "O" = 2.

[0037] As shown below Figure 4As further described in , for each data layer 200A to 200N, the output 312 of the index registers 202A to 202M (i.e., outputs 312A to 312M) is received at a corresponding multiplexer 214 (not shown) of the "M" structures. Figure 4 As further described in , for each data layer 304A to 304N, the outputs 314 of the index registers 306A to 306M (ie, outputs 314A to 314M) are received at corresponding multiplexers 214 (not shown) of the "M" structures.

[0038] After the contents of the shift register 210 and the index register 202 are compared by the comparators 212A-M, the trigger device 236 determines the number of matches and compares the number of matches to a first threshold.

[0039] At a sampling clock 2040 that is out of phase with the sampling clock 204A, the "N" index registers 308 sample data from the data stream 208 and are updated accordingly. As described above, the sampled data is updated at the second sampling clock 2040 and can be uploaded to the index register 306 at the bit clock 222.

[0040] After comparing the contents of shift register 210 and index register 306, trigger device 236 determines the number of matches and compares the number of matches to a first threshold. In an embodiment, a second threshold is used to generate a trigger signal when the second threshold exceeds a set number of times the first threshold is met.

[0041] After sampling clock 204O (not shown), a change in bit clock 222 will require the same operations described above. However, at this changed bit clock 222, the values ​​of index registers 302 and 308 will be carried over to the next sampling clocks 204A and 204O for the subsequent bit clock. In other words, the values ​​at index registers 302 and 308 are downsampled to the corresponding subsequent index registers 202 (i.e., 202A) and 306 (i.e., 306A). This is done to avoid corrupting the wake-up pattern comparison.

[0042] Figure 4 An example expansion of detector 118 is illustrated. Figure 4 A structure 400 is shown, which expands upon the above reference Figure 3 The structure described, Figure 3 Double oversampling or two-time oversampling is described. In other words, the structure 400 can be included as part of the detector 118. Specifically, the structures 400A to 400M ("M" total) support the first sampling, and the structures 400A0 to 400M0 ("M" total) support the second oversampling.

[0043] As mentioned above about Figure 3 As discussed, for each data layer 200A to 200N, the output 312 of the index register 202A to 202M (i.e., output 312A to 312M) is received at the corresponding multiplexer 214 of the corresponding structure 400A to 400M, and for each data layer 304A to 304N, the output 314 of the index register 306A to 306M (i.e., output 314A to 314M) is received at the corresponding multiplexer 214 of the corresponding structure 400A to 400M.

[0044] For each index register 202A to 202M of data layers 200A to 200N, the corresponding output 312A to 312M of index register 202 is received by a corresponding multiplexer 214A to 214M. For example, multiplexer 214A receives input 402A, which is the output of index register 202A of data layer 200A, input 402B, which is the output of index register 202A of data layer 200B, and so on, up to input 402N, which is the output of index register 202A of data layer 200N. For each index register 306A to 306M of data layers 304A to 304N, the corresponding output 314A to 314M of index register 306 is received by a corresponding multiplexer 214A0 to 214M0 (not shown). For example, multiplexer 214AO receives input 402AO which is the output of index register 306A of data layer 304A, input 402BO which is the output of index register 306A of data layer 304B, up to input 402NO which is the output of index register 202A of data layer 304N.

[0045] Detector 400 provides "M" comparisons of the index register with the wake-up pattern, where the components of the layer are placed "M" times each. In some embodiments, to optimize area, detector 400 is included in detector 118 described above. Otherwise, as described below, the comparator is not shared through the multiplexer and the comparator is implemented multiple times.

[0046] As discussed, “M” is also the number of bits in the wakeup pattern word. Figure 4 In the embodiment described in

[0015] , when comparing a data stream to a wake-up pattern, a comparison is performed where a first threshold is the number of matching bits (i.e., the number of bits in the received data stream that match the wake-up pattern word), and a second threshold is the number of sample comparisons that meet the criteria of the first threshold for some data layer. The first threshold can be used in both single-sample and oversampled embodiments, while the use of the second threshold is only for oversampled embodiments.

[0047] In some embodiments, "M" comparators are shared by the multiplexer 214. The multiplexer 214 performs comparisons with "N" stages at a MUX IDX (multiplexer index) 404 clock bit rate that is faster than the bit clock 222 because the comparators 212 perform comparisons with "N" stages (or higher) within a bit clock period of the bit clock 222. Therefore, "clock frequency MUX IDX / bit clock 222 frequency" is greater than 1.

[0048] Detector 400 performs functions similar to those of detector 118 described above; however, detector 400 may be implemented with a reduced number of components. Specifically, detector 400 utilizes at least "M" multiplexers 214, which may operate at up to "N" levels of oversampling, depending on the frequency at which multiplexer selector MUX IDX 404 is clocked. In other words, multiplexer 214 operates at "N" levels, once for each wake-up pattern comparison, and "M" times for each wake-up pattern cycle.

[0049] For example, in Figure 3 In double oversampling operation, each of the multiplexers 214 includes "N" inputs 402, where the 402 inputs are values ​​from index registers, in some embodiments, the values ​​of index registers 202A to 202M or 306A to 306M. For example, at the MUX IDX 404 clock, input 402A corresponds to the output of index register 202A for each of the "N" packet layers 200, input 402A corresponds to the output of index register 202B for each of the "N" packet layers 200, and so on. This operation is repeated at the MUX IDX 404 clock, for example, input 402A0 corresponds to index register 306A for each of the "N" packet layers 304, input 402B0 corresponds to index register 306B for each of the "N" packet layers 304, and so on. Thus, "M*O" multiplexers can be shared to operate Figure 3 As many as “N” levels of detectors 400 or detectors 118 may be used.

[0050] The outputs of multiplexers 214A and 214A0 select index data registers (i.e., registers 202A through 202M and registers 306A through 306M) to compare the index data registers with the wake-up mode bits of dynamic wake-up mode 220A, where multiplexer 214A selects between 202A of 200A through 202A of 200N, and 214A0 selects between 306A of 304A through 306A of 304N, a total of M times. Consequently, output multiplexer 214M correspondingly selects between index data registers 202M of 200A through 200N, and 214M0 selects between 306M of 304A through 306M of 304N, and index data register 306M is compared with the wake-up mode bits of dynamic wake-up mode 220M.

[0051] The output of comparator 406 (binary "1" or "0") controls the output of AND gate 408 (e.g., 408A) and AND gate 410 (e.g., 410A). The packet layer is independently placed "M" times to handle the correlation of a maximum number "M" of pattern bits, as "M" can be reduced (e.g., 12, 16, or 32 bits) and the relevant bits are masked. Masking occurs when the output of comparator 406 is zero or "0," resulting in AND gates 408 and 410 having a zero or "0" value.

[0052] In an embodiment, if the index M of the corresponding index register exceeds the maximum logical configuration wake-up mode register, the comparator 406 masks the association of the index registers 202 and 306 with the wake-up mode. For example, if the embodiment uses 32 bits as the wake-up mode, but can be configured as a 12-, 16-, or 24-bit wake-up mode, the rotation / shift feedback of the wake-up mode is applicable to different wake-up mode bit configurations.

[0053] Furthermore, in cases where the number of packet layers 200 and 304 is higher than the relationship between the switching multiplexers 214 and the sampling clock 206, the packet layers 200 and 304 can be distributed across a plurality of multiplexers to achieve area optimization. In this case, the level of area optimization is defined by the frequency of the multiplexers compared to the sampling clock 206.

[0054] Figure 5 An example flow chart 500 as described herein is shown, which illustrates an example method for detecting a data stream that promotes power conversion in a microcontroller. The order in which the method is described is not intended to be interpreted as limiting, and any number of method blocks described can be combined in any order to implement the method or alternative method. In addition, without departing from the spirit and scope of the subject matter described herein, individual blocks can be deleted from the method. In addition, the method can be implemented in any suitable hardware, software, firmware, or a combination thereof without departing from the scope of the present invention.

[0055] At block 502, sampling of the data stream is performed to update the state of the index register. For example, at sampling clock 206A, data stream 208 is sampled by temporary index register 302. In this example, index register 202 is updated by index register 302.

[0056] At block 504, a comparison of the index register with the shift register is performed. For example, the "M*O" comparator 212 compares the state of the shift register 210 with the corresponding index register 202 or 306 at the clock provided by MUX IDX 404, which needs to be faster than the bit clock 222.

[0057] In an embodiment, "M" comparators 212 are independently shared by data packet layers 200A to 200N and 304A to 304N. In this embodiment, at least "M*O" comparators 212 are used to service N data packet layers 200 and 304, which operate with the same clock (e.g., 32 kHz) that provides MUX IDX 404, which is faster than bit clock 222. MUX IDX 404 may be 32 kHz, where bit clock 222 is 2 kHz, meaning that MUX IDX 404 is 16 times faster than bit clock 222. MUX IDX 404 can operate between 16 data layers.

[0058] At block 506 , the number of matches is compared to a first threshold. For example, the number of matches from the outputs of the shared “M” comparators 212 is compared to the first threshold.

[0059] In response to the number of matches meeting the first threshold, then following the "yes" branch of block 506, at block 508, an adder for summing the number of times the first threshold is met may be used. Otherwise, following the "no" branch of block 506, at block 502, the data stream is sampled during the next bit clock cycle and the comparison is repeated.

[0060] At block 510, a comparison is performed between the number of times the first threshold is met and a second threshold. For example, the sum is compared to the second threshold. In response to the sum meeting the second threshold, following the "yes" branch of block 510, a trigger signal (e.g., trigger signal 238) is generated at block 512. Otherwise, following the "no" branch of block 510, the data stream is sampled again at block 502 during the next bit clock cycle.

[0061] At block 514 , a transition is performed from the first operating mode to the second operating mode. For example, when the adder satisfies the second threshold, then the microcontroller 116 is configured to change from the first operating mode to the second operating mode.

Claims

1. A device associated with communication, comprising: a plurality of packet layers, wherein the number of packet layers is an integer "N", wherein each packet layer comprises: a corresponding plurality of data index registers, wherein the number of data index registers is an integer "M", wherein each data index register is configured to be activated and updated by sampling the data stream; a sampling clock coupled to each of the plurality of data index registers, wherein the sampling clock is configured to independently activate each of the plurality of data index registers; a plurality of wake-up mode shift registers configured to store rotating "M" wake-up mode bits, wherein the number of the wake-up mode shift registers is "M", wherein the rotating of the "M" wake-up mode bits is synchronized with sampling on the data packet layer; a plurality of comparators, wherein the number of comparators is "M," wherein each comparator is coupled to and shared by each of the plurality of data packet layers, wherein each comparator is configured to compare a corresponding updated data index register with a wake-up mode bit from the wake-up mode shift register; a trigger device coupled to the plurality of comparators, wherein the trigger device is configured to generate a trigger signal based on a matching number of outputs from the plurality of comparators; and A microcontroller is coupled to the trigger device, the microcontroller being configured to transition to a high power mode in response to receiving the trigger signal. 2 . The apparatus of claim 1 , wherein the sampling clock further comprises a clock gate coupling each data index register to the sampling clock, wherein the clock gate facilitates independent activation of each data index register.

3. The apparatus of claim 1 , further comprising a bit clock coupled to the plurality of wake-up pattern shift registers, wherein the bit clock synchronizes the rotation of the “M” wake-up pattern bits with the number of samples on the data packet layer.

4. The apparatus of claim 3 , wherein the bit clock facilitates bit rotation of the rotating “M” wake-up pattern bits at each end of sampling on the packet layer. 5 . The apparatus of claim 1 , further comprising a multiplexer for selecting an updated data index register from each packet layer for transmission to the shared comparator. 6 . The apparatus of claim 5 , wherein the state of the updated data index register is received by the shared comparator and compared with a corresponding wake-up mode shift register. 7 . The device according to claim 1 , wherein the trigger device determines a matching number using a first threshold and a second threshold to output the trigger signal to the microcontroller.

8. The apparatus of claim 1, wherein the microcontroller transitions from a first low-power operating mode to a second operating mode that includes the high-power mode.

9. A detector comprising: a plurality of packet layers, wherein the number of packet layers is "N*O", wherein "N" is an integer and "O" is an integer indicating a number of oversampling operations, wherein each packet layer further comprises: a sample index register, which is activated and updated by sampling the data stream bits; a plurality of index registers, wherein the number of index registers is an integer "M", wherein each index register is activated and updated by sampling of the sampling index register; a bit clock coupled to each of the plurality of index registers, wherein the bit clock independently activates each of the plurality of index registers; a plurality of wake-up pattern shift registers initialized to store rotating "M" wake-up pattern bits, wherein the number of the wake-up pattern shift registers is "M", wherein the rotating of the "M" wake-up pattern bits is synchronized with a certain amount of oversampling on the data packet layer; a plurality of comparators, wherein the number of comparators is "M," wherein each comparator is coupled to and shared by each of the plurality of packet layers, wherein each comparator compares an updated index register with a wake-up mode bit from the wake-up mode shift register; a trigger device coupled to the plurality of comparators, wherein the trigger device generates a trigger signal based on a matching number of outputs from the plurality of comparators; and A microcontroller is coupled to the trigger device, wherein the microcontroller facilitates transitioning to the high power mode in response to receiving the trigger signal.

10. The detector of claim 9, wherein the bit clock further comprises a clock gate coupling each index register to the bit clock, wherein the clock gate facilitates independent activation of each of the plurality of index registers, and the amount of oversampling comprises sampling and holding different data streams by activated index registers of the plurality of index registers with different sampling clock signals.

11. The detector of claim 9, wherein the bit clock is coupled to the wake-up mode shift register to control the transmission of the wake-up mode bit to the corresponding comparator.

12. The detector of claim 9, further comprising a multiplexer for selecting an updated index register from each packet layer for transmission to the shared comparator.

13. The detector of claim 12, wherein the state of the updated index register is received by the shared comparator and compared with a corresponding shift register.

14. The detector of claim 9, wherein the trigger device generates the trigger signal using a first threshold and a second threshold.

15. The detector of claim 9 , further comprising a bit clock coupled to the plurality of wake-up pattern shift registers, wherein the bit clock synchronizes the rotation of the “M” wake-up pattern bits with the number of samples on the data packet layer.

16. The detector of claim 15, wherein the bit clock facilitates bit rotation of the rotating "M" wake-up pattern bits at each end of sampling on the data packet layer.

17. A detector comprising: A plurality of packet layers, wherein each packet layer further comprises: a plurality of index registers, wherein each index register is activated and updated by sampling the data stream; a sampling clock coupled to each of the plurality of index registers, wherein the sampling clock independently activates each of the plurality of index registers; Multiple independent and configurable wake-up modes; a plurality of wake-up mode shift registers for each wake-up mode, initialized to store alternating wake-up mode bits; a plurality of comparators, wherein each comparator is coupled to and shared by each of the plurality of packet layers, wherein each comparator compares an updated index register with a wake-up mode bit from the wake-up mode shift register of the independent and configurable wake-up mode; a trigger device coupled to the plurality of comparators, wherein the trigger device independently utilizes a first threshold and a second threshold for each independent and configurable wake-up mode to generate a trigger signal, wherein the first threshold is compared to a number of matches from outputs of the plurality of comparators, wherein in response to the number of matches meeting the first threshold, a counter is incremented, wherein the incremented counter is compared to the second threshold to generate the trigger signal; and A microcontroller is coupled to the trigger device, the microcontroller facilitating transitioning to the high power mode in response to receiving a trigger signal.

18. The detector of claim 17, wherein the sampling clock further comprises a clock gate coupling each index register to the sampling clock, wherein the clock gate facilitates independent activation of each register index register.

19. The detector of claim 17 , further comprising a bit clock coupled to the plurality of wake-up mode shift registers for each individual and configurable wake-up mode, wherein the bit clock synchronizes the rotation of the wake-up mode bits for each individual and configurable wake-up mode with the oversampling of the number of packet layers.

20. The detector of claim 17, further comprising a multiplexer utilized to select the updated index register from each packet layer for transmission to the shared comparator.

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