Chip Configuration Code Testing System and Method

Abstract

An embodiment of the present invention provides a chip configuration code testing system and method, belonging to the field of software testing. The testing system includes a development device, an intermediator, and an evaluation board. The evaluation board includes a testing module and an IP core regarding the high-speed serial interface of the designed chip. The development device includes multiple application program interfaces for configuration codes. The testing module is used to issue a test command. The intermediator is used to, in response to the test command, parse the target application program interface of the development device, retrieve the input parameters of the target configuration code, and access the IP core by using the input parameters. The IP core is used to, in response to the input parameters, execute the logic corresponding to the input parameters to obtain an execution result, so as to determine whether the target configuration code runs normally according to the execution result. Thus, the configuration code of the high-speed serial interface can be tested before the chip is taped out, thereby reducing the chip testing time and improving the chip testing efficiency.

Description

Technical Field

[0001] The present invention relates to the field of software testing, and more particularly, to a chip configuration code testing system and method. Background Art

[0002] A serializer / deserializer (SerDes) is an interface circuit in high-speed data communication. Through the pre-emphasis / equalization technology, the SerDes can achieve high-speed long-distance transmission. Therefore, in chip design, the high-speed serial interface provided by the SerDes is often used.

[0003] As an important module for transmitting signals at the physical layer of a switching chip, the high-speed serial interface plays a role in signal transmission in the switching chip. If the high-speed serial interface cannot operate or work properly, it will seriously hinder the debugging of other modules of the switching chip, resulting in the inability to advance the progress. Currently, it is difficult to build a simulation test environment through an FPGA. Usually, it is only after the chip is taped out that there is an environment for the high-speed serial interface to debug the relevant configuration code (SDK Code), resulting in a long chip testing time and low efficiency. Summary of the Invention

[0004] In view of this, an object of the present invention is to provide a chip configuration code testing system and method, which can improve the problem of long chip testing time and low efficiency caused by the fact that the relevant code of the high-speed serial interface of the chip can only be debugged after the chip is taped out.

[0005] To achieve the above object, the technical solutions adopted in the embodiments of the present invention are as follows.

[0006] In a first aspect, an embodiment of the present invention provides a chip configuration code testing system, adopting the following technical solutions.

[0007] A chip configuration code testing system includes a development device, an intermediator, and an evaluation board. The evaluation board includes a test module and an IP core for the high-speed serial interface of the designed chip;

[0008] The development device includes multiple application program interfaces for configuration codes, where each of the configuration codes implements a target configuration of the high-speed serial interface;

[0009] The test module is used to issue a test command, where the test command includes a target application program interface;

[0010] The intermediator is used to respond to the test command, parse the target application program interface of the development device, retrieve the input parameters of the target configuration code, and access the IP core using the input parameters;

[0011] The IP core is used to execute the logic corresponding to the input parameter in response to the input parameter, obtain an execution result, and determine whether the target configuration code is running normally according to the execution result.

[0012] Further, the evaluation board further includes a status register, and the system further includes a judge;

[0013] The IP core is used to write the execution result into the status register;

[0014] The judge is used to read the execution result from the status register and obtain the running result of the target configuration code according to the comparison result between the execution result and the target result of the target configuration code.

[0015] Further, the evaluation board further includes a display module;

[0016] The display module is used to receive and display the execution result output by the IP core, or read the execution result from the status register and display it.

[0017] Further, the intermediator is further used to convert the programming language of the target configuration code into the language environment of the IP core.

[0018] Further, the target configuration includes loopback interface configuration, equalization configuration, rate switching, and auto-negotiation configuration.

[0019] Further, the intermediator includes a plurality of decorator functions, and one application program interface corresponds to one decorator function;

[0020] The decorator function parses each application program interface of the development device, retrieves the input parameters of each configuration code, and accesses the IP core using the input parameters.

[0021] Further, the evaluation board further includes an IO interface;

[0022] The intermediator calls the IO interface with the input parameter as the input parameter to access the IP core.

[0023] In a second aspect, an embodiment of the present invention further provides a method for testing a chip configuration code, which adopts the following technical solutions.

[0024] A method for testing a chip configuration code, implemented based on the chip configuration code testing system as described in the first aspect, the method includes:

[0025] Sending a test command through a test module, where the test command includes a target application program interface;

[0026] The intermediator parses the target application programming interface of the development device in response to the test command, retrieves the input parameters of the target configuration code, and accesses the IP core using the input parameters;

[0027] The IP core executes the logic corresponding to the input parameters in response to the input parameters, obtains an execution result, and determines whether the target configuration code runs normally according to the execution result.

[0028] Further, the method further includes:

[0029] The IP core writes the execution result into a status register;

[0030] The judge reads the execution result from the status register and obtains the running result of the target configuration code according to the comparison result between the execution result and the target result of the target configuration code.

[0031] Further, the step of accessing the IP core using the input parameters includes:

[0032] The intermediator uses the input parameters as input parameters to call the IO interface of the evaluation board to access the IP core.

[0033] In a third aspect, an embodiment of the present invention provides a computer storage medium, adopting the following technical solution.

[0034] A computer storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the chip configuration code testing method as described in the second aspect.

[0035] In a fourth aspect, an embodiment of the present invention provides a processor, adopting the following technical solution.

[0036] A processor is used to run a computer program, and when the processor runs the computer program, it implements the chip configuration code testing method as described in the second aspect.

[0037] The chip configuration code testing system and method provided by the embodiments of the present invention use the IP core of the high-speed serial interface used when designing the chip, and combine the development device and the intermediator to build a testing system for the high-speed serial interface. The development device includes multiple configuration codes and application program interfaces that implement the target configuration of the serial interface. Thus, under the test command of the test module, the intermediator accesses the IP core on the evaluation board based on the input parameters of the configuration code obtained by parsing the target application program interface on the development device, so as to debug the target configuration code on the IP core. Therefore, before the chip is taped out, the various configuration codes of the high-speed serial interface of the chip can be tested, so that the testing time of the high-speed serial interface can be greatly reduced after the chip is taped out, thereby reducing the chip testing time and improving the efficiency.

[0038] To make the above objects, features and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0040] Figure 1 FIG. 1 shows one of the block diagrams of the chip configuration code testing system provided by the embodiments of the present invention.

[0041] Figure 2 FIG. 2 shows another block diagram of the chip configuration code testing system provided by the embodiments of the present invention.

[0042] Figure 3 FIG. 3 shows one of the flowcharts of the chip configuration code testing method provided by the embodiments of the present invention.

[0043] Figure 4 FIG. 4 shows another flowchart of the chip configuration code testing method provided by the embodiments of the present invention.

[0044] Reference numerals: 100 - chip configuration code testing system; 110 - development device; 120 - application program interface; 130 - intermediator; 140 - evaluation board; 150 - test module; 160 - IP core; 170 - status register; 180 - judge; 190 - display module. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Usually, the components of the embodiments of the present invention described and illustrated herein can be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0047] It should be noted that relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variation thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0048] A serializer / deserializer (SerDes) is an interface circuit in high-speed data communication. The SerDes can achieve high-speed long-distance transmission through pre-emphasis / equalization technology. Therefore, in chip design, the high-speed serial interface provided by the SerDes is often used.

[0049] As an important module for transmitting signals at the physical layer of a switching chip, the high-speed serial interface plays a role in signal transmission in the switching chip. If the high-speed serial interface cannot operate or work properly, it will seriously hinder the debugging of other modules of the switching chip, resulting in the inability to advance the progress.

[0050] Generally, the high-speed serial interface is configured through configuration codes to achieve various communication services. The configuration codes of the un-debugged high-speed serial interface have a large degree of uncertainty and there are relatively large potential risks. Therefore, before using the high-speed serial interface, it is necessary to debug the relevant configuration codes.

[0051] Currently, it is difficult to build a simulation test environment through an FPGA. Usually, it is not until the chip is taped out (chip taping out refers to chip production) that an environment with a high-speed serial interface is available to debug the relevant SDK Code, resulting in long chip testing time and low efficiency.

[0052] In view of the above considerations, an embodiment of the present invention provides a chip configuration code testing solution, which can debug / test the relevant configuration codes of the high-speed serial interface of the chip before the chip is taped out, thereby improving the chip testing efficiency and shortening the chip testing time. Hereinafter, this solution will be introduced from multiple embodiments.

[0053] In one embodiment, please refer to Figure 1 , a chip configuration code testing system 100 is provided, including a development device 110, an intermediator 130, and an evaluation board 140. The evaluation board 140 includes a test module 150 and an IP core 160 regarding the high-speed serial interface of the designed chip.

[0054] The development device 110 includes a plurality of application program interfaces 120 for configuration codes.

[0055] Among them, each configuration code implements a target configuration of the high-speed serial interface. The target configurations implemented by the configuration codes include but are not limited to: loopback interface configuration, equalization configuration, rate switching, and auto-negotiation configuration.

[0056] It should be understood that the target configuration includes all functional configurations of the high-speed serial interface. The above several target configurations are only partial examples among them, rather than the only limitation.

[0057] The test module 150 is used to issue test commands.

[0058] Among them, the test command includes the target application program interface 120.

[0059] The test module 150 includes a test interface, through which the test command is sent, and the configuration code to be debugged, that is, the target configuration code, is specified through the target application program interface 120 in the test command.

[0060] The intermediator 130 is used to parse the target application program interface 120 of the development device 110 in response to the test command, retrieve the input parameters of the target configuration code, and access the IP core 160 using the input parameters.

[0061] Considering the adaptability between the configuration code on the development device 110 side and the IP core 160, the intermediator 130 is used to parse the target application program interface 120 of the development device 110, retrieve the input parameters of the target configuration code, and access the IP core 160 using the input parameters to ensure that the IP core 160 can execute the logic of the target configuration code.

[0062] The IP core 160 is used to execute the logic corresponding to the input parameter in response to the input parameter, obtain an execution result, and determine whether the target configuration code is running properly according to the execution result.

[0063] Each configuration code has its corresponding expected result. If the execution result is the same as the expected result, it runs normally; if not, an execution exception occurs.

[0064] It should be understood that the logic corresponding to the input parameter refers to the logic of the target configuration code.

[0065] In this embodiment, the IP core 160 is a design of a logic block, a data block, or a circuit module of a high-speed serial interface provided by a high-speed serial interface manufacturer or developer, and has the logic function of a high-speed serial interface.

[0066] Compared with the traditional method that can only debug the relevant configuration code of the high-speed serial interface of the chip after the chip is taped out: the chip configuration code test system 100 provided by the present invention uses the IP core 160 of the high-speed serial interface used when designing the chip, and combines the development device 110 and the intermediator 130 to build a test system for the high-speed serial interface. The development device 110 includes a plurality of configuration codes and application program interfaces 120 that implement the target configuration of the serial interface. Thus, under the test command of the test module 150, the intermediator 130 accesses the IP core 160 on the evaluation board 140 based on the input parameters of the configuration code obtained by parsing the target application program interface 120 on the development device 110, so as to test the target configuration code on the IP core 160. Thus, before the chip is taped out, each configuration code of the high-speed serial interface of the chip can be tested, so that the test time of the high-speed serial interface can be greatly reduced after the chip is taped out, thereby reducing the chip test time and improving the efficiency.

[0067] Among them, the development device 110 includes, but is not limited to, terminal devices such as personal computers, laptop computers, and iPads, and a software development kit (SDK) is installed in the development device 110. The configuration code of the high-speed serial interface can be developed and written on the software development kit and stored in the development device 110.

[0068] The application program interface 120, that is, the API, mainly aims to provide the application program (software development kit) and developers with the ability to access a set of routines without having to access the source code or understand the details of the internal working mechanism.

[0069] Considering the situation that the language environment of the software development kit in the development device 110 (i.e., the language of the configuration code) may be different from that of the IP core 160, in one implementation, the intermediator 130 is further configured to convert the language of the target configuration code into the language environment of the IP core 160.

[0070] For example, if the language environment of the IP core 160 is a Python environment and the language environment of the software development kit is the C language, then the intermediate layer can convert the configuration code from the C language to the Python language, or convert the Python language to the C language. If the test command issued by the test module 150 is in the Python language, then the intermediator 130 converts the test command into the C language and then parses the target application programming interface 120. After the intermediator 130 converts the target configuration code into the Python language, it extracts the input parameters.

[0071] Further, please refer to Figure 2 , the intermediator 130 may include multiple decorator functions, and one application programming interface 120 of the development device 110 may correspond to one decorator function.

[0072] The decorator functions parse each application programming interface 120 of the development device 110, retrieve the input parameters of each configuration code, and access the IP core 160 using the input parameters.

[0073] The decorator function can add additional functions to other functions (configuration code) without making any code changes, that is, wrap other functions and change the behavior of the wrapped function (object, which is the configuration code in this embodiment).

[0074] Through the decorator function, an access function is added to the original configuration code, and at the same time, the intermediator 130 can also perform language conversion so that the IP core 160 can execute the logic of the target configuration code without obstacles according to the input parameters.

[0075] It should be understood that other functions can be added to the original configuration code through the decorator function, such as comparing execution results, or alarming when the running result is abnormal, etc., which are not specifically limited in this embodiment.

[0076] To introduce the process of accessing the IP core 160 in more detail, in one implementation, the evaluation board 140 further includes an IO interface, where the IO interface is the IO interface of the IP core 160. It should be understood that the IO interface includes a read IO and a write IO.

[0077] The intermediator 130 realizes accessing the IP core 160 using the input parameters in the following way: the intermediator 130 uses the input parameters as input parameters to call the IO interface to access the IP core 160.

[0078] More specifically, continue to follow Figure 2 The development device 110 further includes an IO interface. After the intermediator 130 receives the test command, through the IO interface of the development device 110, the decorator function corresponding to the target configuration code is used to perform language conversion and input parameter retrieval on the target configuration code from the target application interface 120, and the IO interface of the IP core 160 is retrieved through the IO decorator function corresponding to the IO interface of the development device 110, so as to access the IP core 160 using the input parameters.

[0079] In the above manner, accessing the IP core 160 using the input parameters of the target configuration code is achieved.

[0080] Furthermore, continue to refer to Figure 2 The chip configuration code test system 100 provided by the present invention further includes a judge 180, and the evaluation board 140 further includes a status register 170.

[0081] The IP core 160 is used to write the execution result into the status register 170.

[0082] The judge 180 is used to read the execution result from the status register 170, and obtain the running result of the target configuration code according to the comparison result between the execution result and the target result of the target configuration code.

[0083] By storing the execution result of the IP core 160 after executing the logic of each configuration code in the status register 170, the judge 180 can read the execution result from the status register 170 to judge the running result of the target configuration code.

[0084] Continue to refer to Figure 2 The evaluation board 140 of the chip configuration code test system 100 provided by the present invention may further include a display module 190.

[0085] The display module 190 is used to receive and display the execution result output by the IP core 160, or read the execution result from the status register 170 and display it.

[0086] In addition, the display module 190 is further used to obtain the running result of the target configuration code sent by the judge 180 and display the running result.

[0087] That is, the display module 190 displays the execution result and / or running result of the target configuration code, reminding the debugger of the result of the target configuration code and making it clear at a glance for the debugger.

[0088] In another embodiment, the chip configuration code testing system 100 may include a development device 110 and an evaluation board 140. The development device 110 includes multiple application program interfaces 120 for configuration codes and an intermediator 130. The evaluation board 140 includes a test module 150 and an IP core 160 for the high-speed serial interface of the designed chip.

[0089] The test module 150 is used to issue test commands.

[0090] Among them, the test command includes the target application program interface 120.

[0091] The intermediator 130 is used to, in response to the test command, parse the target application program interface 120 of the development device 110, retrieve the input parameters of the target configuration code, and access the IP core 160 using the input parameters.

[0092] The IP core 160 is used to, in response to the input parameters, execute the logic corresponding to the input parameters to obtain an execution result, and based on the execution result, determine whether the target configuration code is running properly.

[0093] That is, taking the intermediator 130 as a functional module of the development device 110, the chip configuration code testing system 100 is constructed to achieve the same functions as the chip configuration code testing system 100 in the first embodiment.

[0094] In yet another embodiment, the chip configuration code testing system 100 may include a development device 110 and an evaluation board 140. The development device 110 includes multiple application program interfaces 120 for configuration codes. The evaluation board 140 includes an intermediator 130, a test module 150, and an IP core 160 for the high-speed serial interface of the designed chip.

[0095] The test module 150 is used to issue test commands.

[0096] Among them, the test command includes the target application program interface 120.

[0097] The intermediator 130 is used to, in response to the test command, parse the target application program interface 120 of the development device 110, retrieve the input parameters of the target configuration code, and access the IP core 160 using the input parameters.

[0098] The IP core 160 is used to, in response to the input parameters, execute the logic corresponding to the input parameters to obtain an execution result, and based on the execution result, determine whether the target configuration code is running properly.

[0099] That is, taking the intermediator 130 as a functional module of the evaluation board 140, the chip configuration code testing system 100 is constructed to achieve the same functions as the chip configuration code testing system 100 in the first embodiment.

[0100] It should be understood that the above embodiments are only examples of several implementation manners of the chip configuration code test system 100 and are not the only limitations. In practical applications, the above development device 110, intermediator 130, and evaluation board 140 can be configured and combined differently to build different forms of the chip configuration code test system 100 to implement the above test functions.

[0101] In the chip configuration code test system 100 provided above, by introducing the intermediator 130 (including the decorator function), the configuration code (SDK code) of the high-speed serial interface is changed as little as possible to receive the parameters of the interfaces in different language environments, so as to implement the function of mixed call in different languages. Moreover, the intermediator 130 enables the logic of the configuration code to be executed in the inadaptable IP core 160 to improve the environmental adaptability of the chip configuration code test system 100.

[0102] It should be noted that the evaluation board 140 also includes the IP core 160 of the chip, and the development device 110 can also include the configuration code of the chip, so as to realize the chip function debugging before the chip is taped out.

[0103] In addition to using the evaluation board 140 of the high-speed serial interface for performance testing, the above test system can also be used to debug the configuration code before the chip is taped out, effectively reducing the uncertainty of the code during the Bring Up period after the chip is taped out and improving the risk controllability of the code.

[0104] Experimental results show that by adopting the above chip configuration code test system 100, during the chip BringUp stage, the debugging time of the chip high-speed serial interface is reduced from about 2 months to 1 month, greatly improving the chip verification efficiency.

[0105] Based on the same inventive concept as the above embodiments, in one embodiment, referring to Figure 3 , a chip configuration code test method is provided. This method is implemented based on the above chip configuration code test system 100 and may include the following steps.

[0106] S101, sending a test command through the test module.

[0107] Among them, the test command includes the target application program interface 120.

[0108] S102, in response to the test command through the intermediator, parsing the target application program interface of the development device, retrieving the input parameters of the target configuration code, and accessing the IP core using the input parameters.

[0109] S103. In response to the input parameter, execute the logic corresponding to the input parameter through the IP core to obtain an execution result, and based on the execution result, determine whether the target configuration code is running properly.

[0110] In the above chip configuration code testing method, under the test command of the test module 150, the intermediator 130 accesses the IP core 160 on the evaluation board 140 based on the input parameter of the configuration code obtained by parsing the target application programming interface 120 on the development device 110, so as to test the target configuration code on the IP core 160. Thus, before the chip is taped out, each configuration code of the high-speed serial interface of the chip can be tested, greatly reducing the test time of the high-speed serial interface after the chip is taped out, thereby reducing the chip test time and improving the efficiency.

[0111] Further, to facilitate knowing the execution result, referring to Figure 4 , the chip configuration code testing method provided by the present invention may further include the following steps.

[0112] S104. Write the execution result into the status register through the IP core.

[0113] S105. The judge reads the execution result from the status register and obtains the running result of the target configuration code according to the comparison result between the execution result and the target result of the target configuration code.

[0114] To further understand how the intermediator 130 accesses the IP core 160 using the input parameter, in one embodiment, for step S103, the IP core 160 can be accessed using the input parameter in the following manner: the intermediator 130 calls the IO interface of the evaluation board 140 with the input parameter as the input parameter to access the IP core 160.

[0115] For the specific limitations of the chip configuration code testing method, reference can be made to the limitations of the chip configuration code testing system 100 in the above text, which will not be elaborated here.

[0116] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step of the above chip configuration code testing method based on the chip configuration code testing system 100 is implemented.

[0117] In one embodiment, a processor is provided. The processor is used to run a computer program. When the processor runs the computer program, any step or any several steps of the above chip configuration code testing method based on the chip configuration code testing system 100 are implemented.

[0118] It should be understood that the processor can be the processors of the development device 110, the intermediator 130, and the evaluation board 140 in the above chip configuration code test system 100.

[0119] Each functional module (development device 110, intermediator 130, test module 150, and IP core 160) in the above chip configuration code test system 100 can be implemented in whole or in part by software, hardware, and their combination. Each of the above functional modules can be embedded in the processor of the computer device in hardware form or be independent of it, or can be stored in the memory of the computer device in software form so that the processor can call and execute the operations corresponding to each of the above modules.

[0120] In several embodiments provided by the present invention, it should be understood that the disclosed system and method can also be implemented in other ways. The system embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of the system, method, and computer program product according to multiple embodiments of the present invention. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks can occur in a different order from that marked in the accompanying drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0121] In addition, each functional module in each embodiment of the present invention can be integrated together to form an independent part, or each module can exist separately, or two or more modules can be integrated to form an independent part.

[0122] When the above-mentioned functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or a part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs.

[0123] The foregoing are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A chip configuration code testing system, characterized in that, it includes a development device, an intermediator and an evaluation board, and the evaluation board includes a test module and an IP core regarding the high-speed serial interface of the designed chip; the development device includes multiple application program interfaces for configuration codes, and each of the configuration codes implements a target configuration of the high-speed serial interface; the test module is used to issue a test command, and the test command includes a target application program interface; the intermediator is used to, in response to the test command, parse the target application program interface of the development device, retrieve the input parameters of the target configuration code, and access the IP core by using the input parameters; the IP core is used to, in response to the input parameters, execute the logic corresponding to the input parameters, obtain an execution result, and determine whether the target configuration code runs normally according to the execution result; the intermediator includes multiple decorator functions, and one application program interface corresponds to one decorator function; the decorator function parses each application program interface of the development device, retrieves the input parameters of each configuration code, and accesses the IP core by using the input parameters.

2. The chip configuration code testing system according to claim 1, characterized in that, the evaluation board further includes a status register, and the system further includes a judge; the IP core is used to write the execution result into the status register; the judge is used to read the execution result from the status register and obtain the running result of the target configuration code according to the comparison result between the execution result and the target result of the target configuration code.

3. The chip configuration code testing system according to claim 2, characterized in that, the evaluation board further includes a display module; the display module is used to receive and display the execution result output by the IP core, or read the execution result from the status register and display it.

4. The chip configuration code testing system according to claim 1, characterized in that, the intermediator is further used to convert the programming language of the target configuration code into the language environment of the IP core.

5. The chip configuration code testing system according to claim 1, characterized in that, the target configuration includes loopback interface configuration, equalization configuration, rate switching and auto-negotiation configuration.

6. The chip configuration code testing system according to any one of claims 1 to 5, characterized in that, the evaluation board further includes an IO interface; the intermediator calls the IO interface with the input parameters as input parameters to access the IP core.

7. A chip configuration code testing method, characterized in that, it is implemented based on the chip configuration code testing system according to any one of claims 1 to 6, and the method includes: issuing a test command through the test module, and the test command includes a target application program interface; responding to the test command through the intermediator, parsing the target application program interface of the development device, retrieving the input parameters of the target configuration code, and accessing the IP core by using the input parameters; Execute the logic corresponding to the input parameter through the IP core in response to the input parameter to obtain an execution result, and determine whether the target configuration code runs normally according to the execution result.

8. The method for testing a chip configuration code according to claim 7, wherein, the method further includes: writing the execution result into a status register through the IP core; reading the execution result from the status register through a judge, and obtaining the running result of the target configuration code according to the comparison result between the execution result and the target result of the target configuration code.

9. The method for testing a chip configuration code according to claim 7 or 8, wherein, the step of accessing the IP core by using the input parameter includes: a middleman uses the input parameter as an input parameter to call the IO interface of an evaluation board to access the IP core.

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