Method and system for establishing equivalent model of parasitic parameters of large analog circuits

Abstract

The present invention provides a method and system for establishing a parasitic parameter equivalent model of a large-scale analog circuit, including obtaining the capacitance parasitic parameters corresponding to the interconnection lines between the front-stage circuit module and the rear-stage circuit module in the large-scale analog circuit, determining the sum of the capacitance parasitic parameters, and dividing the sum of the capacitance into N equal parts; obtaining the equivalent resistance parameters corresponding to the interconnection lines between the front-stage circuit module and the rear-stage circuit module in the large-scale analog circuit, determining the sum of the resistance values ​​of the equivalent resistance parameters, and dividing the sum of the resistance values ​​into N equal parts; establishing a distributed N-order equivalent RC model, and the distributed N-order equivalent RC model is used to replace the interconnection lines between the front-stage circuit module and the rear-stage circuit module for simulation. The present invention replaces the parasitic parameters caused by long-distance routing in the layout with a concise and accurate RC network, which can be used to evaluate the influence of the parasitic parameters of the long routing between the two-stage circuit on the front-stage circuit, and can also optimize the post-simulation speed, which is suitable for post-simulation verification of large-scale analog circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of analog circuit design, and in particular to a method and system for establishing a parasitic parameter equivalent model of a large analog circuit. Background Art

[0002] As the process of integrated circuits enters the deep submicron era, the secondary effect and short channel effect of MOS tubes have an increasingly greater impact on analog circuit design, and post-simulation verification of analog circuits has become a crucial step. Therefore, accurate and effective post-simulation methods and scientific and standardized post-simulation processes have become issues that analog circuit design engineers have always paid attention to.

[0003] Figure 1 The figure shows a traditional design simulation process applicable to common analog circuit modules. The analog circuit engineer completes the circuit design and pre-simulation work, and then hands it over to the layout personnel to complete the layout work and the corresponding DRC+LVS verification. After the layout personnel complete the layout-related rule verification, they extract the file with parasitic parameters. The circuit engineer performs a series of post-simulation verifications based on the parasitic parameter files provided by the layout to evaluate the circuit performance.

[0004] In large analog circuits, there are multiple modules that communicate with each other. The output of the previous circuit serves as the input of the next circuit. The two are far apart in the layout. The output of the previous circuit needs to be routed over a long distance to reach the next circuit. At this time, the parasitics caused by the long distance routing cannot be ignored.

[0005] Figure 1 The analog circuit design and simulation process shown is suitable for basic analog IP. If a large analog circuit is considered, the process needs to be further improved. This is because when the circuit is large in scale, the parasitic file extracted from the front-stage circuit plus the interactive signals between the front-stage and back-stage circuits is too large, which will seriously slow down the subsequent simulation speed. Summary of the invention

[0006] The present invention provides a method and system for establishing a parasitic parameter equivalent model of a large analog circuit, so as to solve the defect in the prior art that when the circuit scale is large, the parasitic file extracted by the front-stage circuit plus the interactive signal between the front-stage circuit and the front-stage circuit is too large, which will seriously slow down the subsequent simulation speed.

[0007] The present invention provides a method for establishing a parasitic parameter equivalent model of a large analog circuit, comprising:

[0008] Obtaining capacitance parasitic parameters corresponding to interconnection lines between a front-stage circuit module and a rear-stage circuit module in a large analog circuit, determining a sum of the capacitance parasitic parameters, and dividing the sum into N equal parts, where N is a positive integer;

[0009] Obtaining equivalent resistance parameters corresponding to interconnections between a front-stage circuit module and a rear-stage circuit module in a large analog circuit, determining a total resistance value of the equivalent resistance parameters, and dividing the total resistance value into N equal parts;

[0010] A distributed N-order equivalent RC model is established, and the distributed N-order equivalent RC model is used to replace the interconnection lines between the front-stage circuit module and the back-stage circuit module for simulation.

[0011] Furthermore, the obtaining of the capacitance parasitic parameters corresponding to the interconnection lines between the front-stage circuit module and the back-stage circuit module in the large analog circuit includes:

[0012] A layout parasitic parameter netlist corresponding to interconnection lines between a front-stage circuit module and a back-stage circuit module in a large-scale analog circuit is obtained, and capacitor parasitic parameters are extracted from the layout parasitic parameter netlist.

[0013] Furthermore, the value range of N is 5-10.

[0014] Furthermore, the obtaining of equivalent resistance parameters corresponding to interconnections between a front-stage circuit module and a rear-stage circuit module in a large analog circuit includes:

[0015] According to the routing length, width and metal layer used of the interconnection lines between the front-stage circuit module and the back-stage circuit module in the large-scale analog circuit, the corresponding equivalent resistance parameters are obtained.

[0016] Furthermore, the establishment of a distributed N-order equivalent RC model includes:

[0017] A distributed N-order equivalent RC model is established in the order of resistance first and capacitance later. The resistance value of the equivalent RC model is the value of the total resistance value divided into N equal parts, and the capacitance value is the value of the total capacitance divided into N equal parts.

[0018] The present invention also provides a system for establishing a parasitic parameter equivalent model of a large analog circuit, comprising:

[0019] A first parameter acquisition unit is used to acquire capacitance parasitic parameters corresponding to interconnections between a front-stage circuit module and a rear-stage circuit module in a large analog circuit, determine a sum of the capacitance parasitic parameters, and divide the sum into N equal parts, where N is a positive integer;

[0020] A second parameter acquisition unit is used to acquire equivalent resistance parameters corresponding to interconnections between a front-stage circuit module and a rear-stage circuit module in a large analog circuit, determine a total resistance value of the equivalent resistance parameters, and divide the total resistance value into N equal parts;

[0021] The model building unit is used to build a distributed N-order equivalent RC model, and the distributed N-order equivalent RC model is used to replace the interconnection lines between the front-stage circuit module and the back-stage circuit module for simulation.

[0022] The present invention also provides a simulation method for a large-scale analog circuit, which obtains a parasitic parameter file of a front-stage circuit module in the large-scale analog circuit and a distributed N-order equivalent RC model for post-simulation.

[0023] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the method for establishing the parasitic parameter equivalent model of the large analog circuit is implemented.

[0024] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the method for establishing the parasitic parameter equivalent model of the large analog circuit is implemented.

[0025] The method and system for establishing a parasitic parameter equivalent model of a large analog circuit provided by the present invention replace the parasitic parameters caused by long-distance routing at a long distance in the layout with a simple and accurate RC network, which not only accurately evaluates the influence of the parasitic parameters of the long routing between two-stage circuits on the previous-stage circuit, but also optimizes the post-simulation speed, and is suitable for post-simulation verification of large analog circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 It is a design simulation flow chart applicable to common analog circuit modules in the prior art;

[0028] Figure 2 It is a flow chart of a method for establishing a parasitic parameter equivalent model of a large analog circuit provided by the present invention;

[0029] Figure 3 It is a simulation example schematic diagram of a large analog circuit in a TDDI product;

[0030] Figure 4 It is a schematic diagram of the parasitic parameter equivalent model of the gray-scale voltage signal;

[0031] Figure 5 It is a schematic diagram of the fifth-order distributed RC equivalent model;

[0032] Figure 6It is a principle block diagram of the method for establishing a parasitic parameter equivalent model of a large analog circuit provided by the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] like Figure 2 As shown, the present invention provides a method for establishing a parasitic parameter equivalent model of a large analog circuit, comprising:

[0035] S1, obtaining capacitance parasitic parameters corresponding to interconnection lines between a front-stage circuit module and a back-stage circuit module in a large analog circuit, determining a sum of the capacitance parasitic parameters, and dividing the sum into N equal parts, where N is a positive integer;

[0036] The layout parameter extraction tool Calibre can be used to extract the C+CC type parasitic parameter netlist. In the netlist, the names of the interconnection lines between the previous and next stage circuits are searched to obtain the total capacitance of C+CC of each interconnection line, and the total capacitance is divided into N equal parts.

[0037] S2, obtaining equivalent resistance parameters corresponding to interconnections between a front-stage circuit module and a rear-stage circuit module in a large analog circuit, determining a total resistance value of the equivalent resistance parameters, and dividing the total resistance value into N equal parts;

[0038] S3, establishing a distributed N-order equivalent RC model, wherein the distributed N-order equivalent RC model is used to replace the interconnection lines between the front-stage circuit module and the back-stage circuit module for simulation.

[0039] As an optional embodiment, the obtaining of capacitance parasitic parameters corresponding to interconnections between a front-stage circuit module and a rear-stage circuit module in a large analog circuit includes:

[0040] A layout parasitic parameter netlist corresponding to interconnection lines between a front-stage circuit module and a back-stage circuit module in a large-scale analog circuit is obtained, and capacitor parasitic parameters are extracted from the layout parasitic parameter netlist.

[0041] Specifically, the C+CC netlist can be extracted through layout, and the C+CC parasitic parameters of the interactive signals between the previous and next stage circuits can be found from the C+CC netlist. C is the parasitic capacitance, and CC is the coupling capacitance.

[0042] As an optional embodiment, the value range of N is 5-10. The value of N has a certain range requirement. If the value of N is too small, it cannot be close to the actual situation, and if the value of N is too large, the RC model will become complicated. Generally, the value of N is between 5-10.

[0043] As an optional embodiment, the obtaining of equivalent resistance parameters corresponding to interconnections between a front-stage circuit module and a rear-stage circuit module in a large analog circuit includes:

[0044] The corresponding equivalent resistance parameters are obtained based on the routing length, width and metal layer used for the interconnection lines between the front-stage circuit modules and the back-stage circuit modules in the large analog circuit. When calculating the corresponding resistance, special attention should be paid to the series-parallel relationship of the calculated equivalent resistance. The corresponding resistance Rt is calculated based on the square resistance Rs of the metal layer used for the routing, the routing width W and the length L: Rt = Rs*(L / W).

[0045] Furthermore, the establishment of a distributed N-order equivalent RC model includes:

[0046] A distributed N-order equivalent RC model is established in the order of resistance first and capacitance later. The resistance value of the equivalent RC model is the value of the total resistance value divided into N equal parts, and the capacitance value is the value of the total capacitance divided into N equal parts.

[0047] Figure 3 This is a simulation example of a large analog circuit in a TDDI product. The pixel data is grayscale corrected by GAMMA, and the output 65-bit grayscale voltage signal GVP<64:0> needs to be spread throughout the chip to connect to the source driver circuit. After the data passes through the source, the pixel circuit is driven to complete the light emission. GAMMA is located in the center of the chip, and the source driver circuit is arranged from left to right in the chip. Therefore, in order to accurately evaluate the stability and transient response performance of the GAMMA module, the influence of the long routing parasitic parameters of the 65-bit grayscale voltage signal GVP<64:0> must be considered.

[0048] Figure 4 is the grayscale voltage signal GVP <0> Parasitic parameter equivalent model, GVP <0> After the GAMMA output, pull the entire chip left and right, and calculate the corresponding resistance R0, R1, and R2 based on the square resistance of the metal layer used for the routing, the routing width, and the length. Find GVP in the parasitic parameter file based on the GAMMA extracted from the layout plus all sources plus GVP<64:0> <0> The total capacitance of C+CC is C total , that is, C1, C2, C1=C2=C totalR1 and C1 are the equivalent resistance parameters and capacitance parasitic parameters corresponding to the interconnection lines between the front-stage circuit module and the back-stage circuit module in the large analog circuit, and R2 and C2 are the equivalent resistance parameters and capacitance parasitic parameters corresponding to the interconnection lines between the front-stage circuit module and the back-stage circuit module in the large analog circuit.

[0049] Figure 5 It is GVP <0> The fifth-order distributed RC equivalent model is divided into N equal parts, where N = 5, and GVP is established. <0> The fifth-order RC distributed equivalent model, R 10 =R 11 =R 12 =R 13 =R 14 =R1 / 5, R 20 =R 21 =R 22 =R 23 =R 24 =R2 / 5, C 10 =C 11 =C 12 =C 13 =C 14 =C1 / 5, C 20 =C 21 =C 22 =C 23 =C 24 = C2 / 5. According to this method, the fifth-order RC distributed equivalent model of GVP<64:0> can be established respectively, and then the equivalent model can be used to replace the long-distance grayscale signal lines between GAMMA and all sources for simulation.

[0050] like Figure 6 As shown, the present invention also provides a system for establishing a parasitic parameter equivalent model of a large analog circuit, comprising:

[0051] A first parameter acquisition unit is used to acquire capacitance parasitic parameters corresponding to interconnections between a front-stage circuit module and a rear-stage circuit module in a large analog circuit, determine a sum of the capacitance parasitic parameters, and divide the sum into N equal parts, where N is a positive integer;

[0052] A second parameter acquisition unit is used to acquire equivalent resistance parameters corresponding to interconnections between a front-stage circuit module and a rear-stage circuit module in a large analog circuit, determine a total resistance value of the equivalent resistance parameters, and divide the total resistance value into N equal parts;

[0053] The model building unit is used to build a distributed N-order equivalent RC model, and the distributed N-order equivalent RC model is used to replace the interconnection lines between the front-stage circuit module and the back-stage circuit module for simulation.

[0054] The present invention also provides a simulation method for a large analog circuit, which obtains the parasitic parameter file of the front-stage circuit module in the large analog circuit and the distributed N-order equivalent RC model for post-simulation. By using the N-order RC distributed equivalent model to replace the long-distance routing between two analog modules, not only can the influence of the parasitic parameters of the long-distance routing between the layout modules on the front-stage module be evaluated concisely and accurately, but also the post-simulation speed is greatly improved.

[0055] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the method for establishing the parasitic parameter equivalent model of the large analog circuit is implemented.

[0056] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the method for establishing the parasitic parameter equivalent model of the large analog circuit is implemented.

[0057] The method and system for establishing a parasitic parameter equivalent model of a large analog circuit provided by the present invention replace the parasitic parameters caused by long-distance routing at a long distance in the layout with a simple and accurate RC network, which not only accurately evaluates the influence of the parasitic parameters of the long routing between two-stage circuits on the previous-stage circuit, but also optimizes the post-simulation speed, and is suitable for post-simulation verification of large analog circuits.

[0058] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for establishing a parasitic parameter equivalent model of a large analog circuit, characterized in that: include: Obtaining capacitance parasitic parameters corresponding to interconnection lines between a front-stage circuit module and a rear-stage circuit module in a large analog circuit, determining a sum of the capacitance parasitic parameters, and dividing the sum into N equal parts, where N is a positive integer; Obtaining equivalent resistance parameters corresponding to interconnections between a front-stage circuit module and a rear-stage circuit module in a large analog circuit, determining a total resistance value of the equivalent resistance parameters, and dividing the total resistance value into N equal parts; Establishing a distributed N-order equivalent RC model, wherein the distributed N-order equivalent RC model is used to replace the interconnection line between the front-stage circuit module and the back-stage circuit module for simulation; In TDDI products, pixel data is grayscale corrected by GAMMA, and the output 65-bit grayscale voltage signal GVP<64:0> needs to be spread throughout the chip to connect to the source driver circuit. After the data passes through the source, the pixel circuit is driven to emit light. GAMMA is located in the center of the chip, and the source driver circuit is arranged from left to right in the chip. GVP <0> After the GAMMA output, pull the entire chip left and right, and calculate the corresponding resistances R0, R1, and R2 based on the square resistance of the metal layer used for the routing, the routing width, and the length; find GVP in the parasitic parameter file based on the GAMMA extracted from the layout plus all sources plus GVP<64:0> <0> The total capacitance of C+CC is C total , that is, C1, C2, C1=C2=C total ; R1 and C1 are the equivalent resistance parameters and capacitance parasitic parameters corresponding to the interconnection lines between the front-stage circuit module and the back-stage circuit module in the large analog circuit, and R2 and C2 are the equivalent resistance parameters and capacitance parasitic parameters corresponding to the interconnection lines between the front-stage circuit module and the back-stage circuit module in the large analog circuit; N-order RC distributed equivalent models of GVP<64:0> are established respectively, and the equivalent models are used to replace the long-distance grayscale signal lines between GAMMA and all sources for simulation.

2. The method for establishing a parasitic parameter equivalent model of a large analog circuit according to claim 1, characterized in that: The method of obtaining the capacitance parasitic parameters corresponding to the interconnection lines between the front-stage circuit module and the back-stage circuit module in the large analog circuit includes: A layout parasitic parameter netlist corresponding to interconnection lines between a front-stage circuit module and a back-stage circuit module in a large-scale analog circuit is obtained, and capacitor parasitic parameters are extracted from the layout parasitic parameter netlist.

3. The method for establishing a large-scale analog circuit parasitic parameter equivalent model according to claim 1, characterized in that: The value range of N is 5-10.

4. The method for establishing a parasitic parameter equivalent model of a large analog circuit according to claim 1, characterized in that: The method of obtaining the equivalent resistance parameters corresponding to the interconnection lines between the front-stage circuit module and the back-stage circuit module in the large analog circuit includes: According to the routing length, width and metal layer used of the interconnection lines between the front-stage circuit module and the back-stage circuit module in the large-scale analog circuit, the corresponding equivalent resistance parameters are obtained.

5. The method for establishing a parasitic parameter equivalent model of a large analog circuit according to claim 1, characterized in that: The establishing of the distributed N-order equivalent RC model comprises: A distributed N-order equivalent RC model is established in the order of resistance first and capacitance later. The resistance value of the equivalent RC model is the value of the total resistance value divided into N equal parts, and the capacitance value is the value of the total capacitance divided into N equal parts.

6. A system for establishing a parasitic parameter equivalent model of a large analog circuit, used to implement the method for establishing a parasitic parameter equivalent model of a large analog circuit as described in any one of claims 1 to 5, characterized in that: include: A first parameter acquisition unit is used to acquire capacitance parasitic parameters corresponding to interconnections between a front-stage circuit module and a rear-stage circuit module in a large analog circuit, determine a sum of the capacitance parasitic parameters, and divide the sum into N equal parts, where N is a positive integer; A second parameter acquisition unit is used to acquire equivalent resistance parameters corresponding to interconnections between a front-stage circuit module and a rear-stage circuit module in a large analog circuit, determine a total resistance value of the equivalent resistance parameters, and divide the total resistance value into N equal parts; The model building unit is used to build a distributed N-order equivalent RC model, and the distributed N-order equivalent RC model is used to replace the interconnection lines between the front-stage circuit module and the back-stage circuit module for simulation.

7. A method for simulating a large analog circuit, implemented based on the method for establishing a parasitic parameter equivalent model of a large analog circuit according to any one of claims 1 to 5, characterized in that: Obtain the parasitic parameter files and distributed N-order equivalent RC models of the previous stage circuit modules in large analog circuits for post-simulation.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for establishing a parasitic parameter equivalent model of a large analog circuit as claimed in any one of claims 1 to 5 is implemented.

9. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method for establishing a parasitic parameter equivalent model of a large analog circuit as claimed in any one of claims 1 to 5 is implemented.

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