Voltage Output Control Method and Its System, Display Control System, and Display Device

Abstract

The present disclosure provides a voltage output control method for controlling a power supply module to supply a required operating voltage to a display panel. The process of the display panel displaying a frame of a picture includes a plurality of row driving cycles performed in sequence. The row driving cycle includes: a charging period and a non-charging period; during the charging period, a data line is conducted with sub-pixels of a corresponding row to write a data voltage into the corresponding sub-pixels; during the non-charging period, the data line is open-circuited with the sub-pixels; the voltage output control method includes: controlling the power supply module to output at a preset first operating frequency during the process of displaying a picture to be displayed, and the time when the power supply module outputs the operating voltage to the display panel does not overlap with the charging period.

Description

Technical Field

[0001] The present invention relates to the field of displays, and particularly to a voltage output control method, a voltage output control system, a display control system, a display device, an electronic device, and a computer-readable medium. Background Art

[0002] A display device generally includes a display control system and a display panel (including a source driver circuit and a gate driver circuit). The display control system includes a power supply module, and its core component is a charge pump (also known as a boost circuit). The power supply module is used to provide the required operating voltage for the display panel, and the operating voltage includes but is not limited to a high-level operating voltage VGH, a low-level operating voltage VGL, a reference voltage Vref, an initialization voltage Vinit, a common voltage Vcom, etc.

[0003] The power supply module provides the operating voltage to the display panel according to a preset operating frequency (also known as the output frequency of the power supply module). The current operating frequency of the power supply module is set based on the consideration of the power consumption of the power supply module. In actual applications, it is found that the current power supply module will have a certain impact on the display screen during the process of outputting the operating voltage to the display panel, resulting in obvious mura in the display screen. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art, and provides a voltage output control method, a voltage output control system, a display control system, a display device, an electronic device, and a computer-readable medium.

[0005] In a first aspect, an embodiment of the present disclosure provides a voltage output control method for controlling a power supply module to provide the required operating voltage for a display panel. The process of the display panel displaying a frame of a picture includes a plurality of row driving cycles performed in sequence. The row driving cycle includes: a charging period and a non-charging period; during the charging period, a data line is conducted with a sub-pixel corresponding to a row to write a data voltage into the corresponding sub-pixel; during the non-charging period, the data line is disconnected from the sub-pixel;

[0006] The voltage output control method includes:

[0007] Controlling the power supply module to output at a preset first operating frequency during the process of displaying a picture to be displayed, and the time when the power supply module outputs the operating voltage to the display panel does not overlap with the charging period.

[0008] In some embodiments, it further includes: detecting whether the picture to be displayed is a first picture;

[0009] Wherein, when it is detected that the to-be-displayed screen is the first screen, the step of controlling the power supply module to output at a preset first operating frequency during the display of the to-be-displayed screen is executed.

[0010] In some embodiments, the first screen is a heavy-load screen.

[0011] In some embodiments, it further includes:

[0012] When it is detected that the to-be-displayed screen is not the first screen, control the power supply module to output at a preset second operating frequency during the display of the to-be-displayed screen;

[0013] The second operating frequency is less than the first operating frequency.

[0014] In some embodiments, the step of controlling the power supply module to output at a preset first operating frequency during the display of the to-be-displayed screen includes:

[0015] During the display of the to-be-displayed screen, send a first clock signal with a first clock frequency to the power supply module, so that the power supply module outputs at the first operating frequency;

[0016] The step of controlling the power supply module to output at a preset second operating frequency during the display of the to-be-displayed screen includes:

[0017] During the display of the to-be-displayed screen, send a second clock signal with a second clock frequency to the power supply module, so that the power supply module outputs at the second operating frequency;

[0018] The second clock frequency is less than the first clock frequency.

[0019] In some embodiments, the display panel includes: multiple columns of sub-pixels, each column of sub-pixels is configured with a corresponding data line, and the sub-pixels located in the same column are all connected to the corresponding data line;

[0020] The step of detecting whether the to-be-displayed screen is the first screen includes:

[0021] According to the change of the data voltages of different sub-pixels in each column of sub-pixels in the to-be-displayed screen, determine the heavy-load degree of the to-be-displayed screen;

[0022] According to the heavy-load degree and a preset degree threshold, judge whether the to-be-displayed screen is the first screen;

[0023] Wherein, if the heavy-load degree is greater than the preset degree threshold, it is judged that the to-be-displayed screen is the first screen;

[0024] If the overload degree is less than or equal to the preset degree threshold, it is determined that the to-be-displayed picture is not the first picture.

[0025] In some embodiments, the display panel includes M*N sub-pixels arranged in an array of N rows and M columns;

[0026] The step of determining the overload degree of the to-be-displayed picture according to the change of the data voltages of different sub-pixels in each column of sub-pixels in the to-be-displayed picture includes:

[0027] Calculate the degree of change of the data voltage between any two adjacent sub-pixels in the row direction in the same column, and compare them with the preset change degree threshold respectively, and count the frequency of the degree of change of the data voltage greater than the preset change degree threshold;

[0028]

[0029] S (n_m,n+1_m) represents the degree of change of the data voltage between the sub-pixel located in the nth row and the mth column and the sub-pixel located in the (n + 1)th row and the mth column, V n_m represents the data voltage of the sub-pixel located in the nth row and the mth column, V n+1_m represents the data voltage of the sub-pixel located in the (n + 1)th row and the mth column, n is an integer and 1 ≤ n ≤ N - 1, m is an integer and 1 ≤ m ≤ M;

[0030] Determine the overload degree of the to-be-displayed picture according to the frequency of the degree of change of the data voltage greater than the preset change degree threshold;

[0031]

[0032] P represents the overload degree of the to-be-displayed picture, and K represents the frequency of the degree of change of the data voltage greater than the preset change degree threshold.

[0033] In some embodiments, the first operating frequency f1 satisfies:

[0034]

[0035] Q is an integer and 1 ≤ N ≤ 5, and t0 is the duration corresponding to 1 row driving period.

[0036] In a second aspect, embodiments of the present disclosure further provide a voltage output control system for controlling a power supply module to supply a required operating voltage to a display panel. The process of the display panel displaying a frame of a picture includes a plurality of row driving cycles performed in sequence. The row driving cycle includes: a charging period and a non-charging period; during the charging period, a data line is conducted with sub-pixels of a corresponding row to write a data voltage into the corresponding sub-pixels; during the non-charging period, the data line is open-circuited from the sub-pixels.

[0037] The voltage output control system includes:

[0038] A first control module that controls the power supply module to output at a preset first operating frequency during the process of displaying the picture to be displayed, and the time when the power supply module outputs the operating voltage to the display panel does not overlap with the charging period.

[0039] In some embodiments, it further includes:

[0040] A detection module for detecting whether the picture to be displayed is a first picture;

[0041] The first control module is specifically configured to, when the detection module detects that the picture to be displayed is a first picture, control the power supply module to output at a preset first operating frequency during the process of displaying the picture to be displayed, and the time when the power supply module outputs the operating voltage to the display panel does not overlap with the charging period.

[0042] In some embodiments, the first picture is a heavy load picture.

[0043] In some embodiments, it further includes:

[0044] A second control module for controlling the power supply module to output at a preset second operating frequency during the process of displaying the picture to be displayed when the detection module detects that the picture to be displayed is not a first picture; the second operating frequency is less than the first operating frequency.

[0045] In some embodiments, the first control module specifically includes:

[0046] A first clock output unit for sending a first clock signal with a first clock frequency to the power supply module during the process of displaying the picture to be displayed, so that the power supply module outputs at the first operating frequency;

[0047] The second control module specifically includes:

[0048] A second clock output unit, configured to send a second clock signal with a second clock frequency to the power supply module during the process of displaying the to-be-displayed picture, so that the power supply module outputs at the second operating frequency; the second clock frequency is less than the first clock frequency.

[0049] In some embodiments, the display panel includes: multiple columns of sub-pixels, each column of sub-pixels is configured with a corresponding data line, and the sub-pixels located in the same column are all connected to the corresponding data line;

[0050] The detection module includes:

[0051] A determination unit, configured to determine the overload degree of the to-be-displayed picture according to the change of the data voltages of different sub-pixels in each column of sub-pixels in the to-be-displayed picture;

[0052] A judgment unit, configured to judge whether the to-be-displayed picture is a first picture according to the overload degree and a preset degree threshold;

[0053] If the overload degree is greater than the preset degree threshold, it is judged that the to-be-displayed picture is a first picture;

[0054] If the overload degree is less than or equal to the preset degree threshold, it is judged that the to-be-displayed picture is not a first picture.

[0055] In some embodiments, the display panel includes M*N sub-pixels arranged in an array of N rows and M columns;

[0056] The determination unit includes:

[0057] A first arithmetic unit, configured to calculate the degree of change of the data voltage between any two adjacent sub-pixels in the row direction and located in the same column, compare them with a preset change degree threshold respectively, and count the frequency of the degree of change of the data voltage greater than the preset change degree threshold;

[0058]

[0059] S (n_m,n+1_m) represents the degree of change of the data voltage between the sub-pixel located in the nth row and the mth column and the sub-pixel located in the (n + 1)th row and the mth column, V n_m represents the data voltage of the sub-pixel located in the nth row and the mth column, V n+1_m represents the data voltage of the sub-pixel located in the (n + 1)th row and the mth column, n is an integer and 1 ≤ n ≤ N - 1, m is an integer and 1 ≤ m ≤ M;

[0060] A second operator unit, configured to determine the overload degree of the to-be-displayed picture according to the frequency of the data voltage change degree greater than the preset change degree threshold;

[0061]

[0062] Let P represent the overload degree of the to-be-displayed picture, and K represent the frequency of the data voltage change degree greater than the preset change degree threshold.

[0063] In some embodiments, the first operating frequency f1 satisfies:

[0064]

[0065] Q is an integer and 1 ≤ N ≤ 5, and t0 is the duration corresponding to one line driving period.

[0066] In a third aspect, an embodiment of the present disclosure further provides a display control system, including: a power supply module and the voltage output control system provided in the second aspect above.

[0067] In a fourth aspect, an embodiment of the present disclosure further provides a display device, including: a display panel and the display control system adopted in the third aspect above.

[0068] In a fifth aspect, an embodiment of the present disclosure further provides an electronic device, including:

[0069] One or more processors;

[0070] A memory, configured to store one or more programs;

[0071] When the one or more programs are executed by the one or more processors, the one or more processors implement the voltage output control method provided in the first aspect.

[0072] In some embodiments, the processor includes a field programmable gate array.

[0073] In a sixth aspect, an embodiment of the present disclosure further provides a computer-readable medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps in the voltage output control method provided in the first aspect. Description of the Drawings

[0074] Figure 1 It is a systematic block diagram of a display device related to the technical solution of the present disclosure;

[0075] Figure 2 It is a circuit structure schematic diagram of a sub-pixel in an embodiment of the present disclosure;

[0076] Figure 3 Another circuit structure diagram of a sub-pixel in an embodiment of the present disclosure;

[0077] Figure 4 A circuit structure diagram of a power supply module in an embodiment of the present disclosure;

[0078] Figure 5 A timing diagram of the voltage Vpph to be output inside the power supply module;

[0079] Figure 6 A timing distribution diagram of displaying a frame of a picture in an embodiment of the present disclosure;

[0080] Figure 7 A timing diagram of the voltage Vpph to be output inside the power supply module and displaying a frame of a picture in the related art;

[0081] Figure 8 A flowchart of a voltage output control method provided in an embodiment of the present disclosure;

[0082] Figure 9a A flowchart of another voltage output control method provided in an embodiment of the present disclosure;

[0083] Figure 9b A flowchart of yet another voltage output control method provided in an embodiment of the present disclosure;

[0084] Figure 10 A timing diagram of the voltage Vpph to be output inside the power supply module and displaying a frame of a picture in the present disclosure;

[0085] Figure 11 A flowchart of an alternative implementation method of step S1 in an embodiment of the present disclosure;

[0086] Figure 12 A structural block diagram of a voltage output control system provided in an embodiment of the present disclosure;

[0087] Figure 13 A structural diagram of an electronic device in an embodiment of the present disclosure. Detailed implementation manners

[0088] To enable those skilled in the art to better understand the technical solutions of the present invention, a voltage output control method, a voltage output control system, a display control system, a display device, an electronic device, and a computer-readable medium provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0089] Figure 1 A systematic structural block diagram of a display device related to the technical solution of the present disclosure, as Figure 1 shown, a display panel 1 and a display control system 2.

[0090] Among them, when divided according to the display dimension, the display panel 1 can be a 2D display panel or a 3D display panel; when divided according to the light-emitting type, the display panel 1 can be a liquid crystal display panel (LCD), a light-emitting diode (LED) display panel, an organic light-emitting diode (OLED) display panel, or a quantum dot light-emitting diode (QLED) display panel. The technical solution of the present disclosure does not limit the type and structure of the display panel. In the embodiments of the present disclosure, the display panel includes a plurality of sub-pixels arranged in an array along the row direction and the column direction, and each sub-pixel is connected to a corresponding row gate line and a corresponding column data line; among them, the sub-pixels located in the same row are connected to the same gate line, and the sub-pixels located in the same column are connected to the same data line.

[0091] The display panel 1 is configured with a gate driving circuit (not shown) and a source driving circuit (not shown); the gate driving circuit is used to provide a gate driving signal to the gate line to perform a scanning drive on the gate line; the source driving circuit is used to provide a data voltage to the data line to write the data voltage into the corresponding sub-pixel through the data line to control the sub-pixel to display a gray scale.

[0092] Figure 2 It is a schematic circuit diagram of a sub-pixel in an embodiment of the present disclosure, as Figure 2 shown, the sub-pixel is a sub-pixel in the liquid crystal display panel 1, including a switching transistor T0 and a pixel electrode. The control electrode of the switching transistor T0 is connected to the corresponding row gate line GATE, the first electrode of the switching transistor T0 is connected to the data line DATA, and the second electrode of the switching transistor T0 is connected to the pixel electrode. When the driving signal provided by the gate line GATE is in an effective level state, the switching transistor T0 is turned on, and the data voltage in the data line DATA is written into the pixel electrode.

[0093] Figure 3 It is another schematic circuit diagram of a sub-pixel in an embodiment of the present disclosure, as Figure 3As shown, the sub-pixel is a sub-pixel in the LED / OLED / QLED display panel 1, including: a data writing transistor T1, a driving transistor DTFT, and a light-emitting element EL (specifically, it can be an LED, an OLED, or a QLED); the control electrode of the data writing transistor T1 is connected to the corresponding row gate line GATE, the first electrode of the data writing transistor T1 is connected to the data line DATA, the second electrode of the data writing transistor T1 is connected to the control electrode of the driving transistor DTFT, the first electrode of the driving transistor DTFT is connected to the power supply terminal VDD, and the second electrode of the driving transistor DTFT is connected to the light-emitting element EL. When the driving signal provided by the gate line GATE is in the effective level state, the data writing transistor T1 is turned on, and the data voltage in the data line DATA is written to the control of the driving transistor DTFT, and the driving transistor DTFT outputs a corresponding driving circuit.

[0094] It should be noted that the circuit structure of the sub-pixel in the embodiments of the present disclosure is not limited to Figure 2 and Figure 3 shown in, and other circuit structures can also be adopted, and no further examples will be given here.

[0095] In the embodiments of the present disclosure, the specific form of the gate driving circuit can be a chip with a gate driving function (generally referred to as a Gate IC), or a circuit structure directly formed in the peripheral area of the display panel based on the array substrate process (Gate on Array, abbreviated as GOA). The specific form of the source driving circuit can be a chip with a source driving function (generally referred to as a Source IC), and the source driving chip can be bonded to the connection pads on the display panel through a flexible circuit board (Flexible Printed Circuit, abbreviated as FPC). The technical solution of the present disclosure does not limit the specific structures of the gate driving circuit and the source driving circuit.

[0096] The display control system includes a voltage output control system and a power supply module. The voltage output control system can be used to receive the display data of the picture to be displayed (including the data voltage of each sub-pixel) and control the power supply module to work.

[0097] Figure 4 This is a schematic diagram of a circuit structure of the power supply module in the embodiments of the present disclosure. Figure 5 This is a timing diagram of the voltage Vpph to be output inside the power supply module. As Figure 4 and Figure 5As shown, the core component of the power supply module 4 is a charge pump, which includes a boost circuit 401 and a voltage clamp circuit 402. The boost circuit 401 performs a boost operation in response to the control of the clock signal CLK, and gradually raises the output voltage Vpph. When the output voltage Vpph reaches the clamping high voltage of the voltage clamp circuit 402, that is, when the charge pump is started, the enable signal pump_en of the boost circuit 401 changes from a high level to a low level, thereby turning off the boost circuit 401, and the charge pump outputs the output voltage Vpph as a working voltage (the output duration is relatively short), that is, the power supply module 4 supplies power to the display panel; subsequently, when the output voltage Vpph drops below the clamping low voltage of the voltage clamp circuit 402 due to discharge or other reasons, the enable signal pump_en of the boost circuit 401 changes from a low level to a high level, and the boost circuit 401 starts again; in this way, the working voltage actually output by the charge pump can be maintained at a relatively stable high voltage.

[0098] In practical applications, in order to enable the power supply module 4 to provide different operating voltages (for example, a high-level operating voltage VGH, a low-level operating voltage VGL, a reference voltage Vref, an initialization voltage Vinit, and a common voltage Vcom), a plurality of boost circuits 401 and corresponding plurality of voltage clamp circuits 402 (i.e., a plurality of charge pumps) may be provided inside the power supply module 4, and each boost circuit 401 and corresponding voltage clamp circuit 402 are used to output a type of operating voltage. The present disclosure does not limit the specific circuit structure of the power supply module 4.

[0099] Figure 6 Schematic diagram of a time distribution of displaying a frame of picture in the embodiment of the present disclosure, such as Figure 6 As shown, the process of displaying a frame of picture on the display panel includes: a pixel driving stage; in some embodiments, after the pixel driving stage, a stable display stage (not shown in the figure) is also included. The pixel driving stage includes: a plurality of row driving cycles p0 ( Figure 6 Only nine row driving periods p0 are exemplarily shown in the figure, and a plurality of row driving periods p0 are performed sequentially, and each row driving period p0 includes: a charging period s2 and a non-charging period s1.

[0100] The start and end of each row drive cycle is controlled by the horizontal synchronization signal HSYNC. Figure 6 As shown, when the horizontal synchronization signal HSYNC switches from a low level to a high level, it indicates the end of the previous row driving period p0 and the beginning of the current row driving period p0.

[0101] Taking the driving of a certain row of sub-pixels as an example. During the charging period s2 corresponding to the sub-pixels of this row, the gate driving circuit provides an effective level signal so that the transistors (for example, Figure 2 the switching transistor T0 in Figure 3 and the data writing transistor T1 in

[0102] In some embodiments, referring to Figure 6 as shown, within a row driving cycle p0, a non-charging period s1 (generally also referred to as a charging preparation period) is set between the start time of the row driving cycle p0 and the start time of the charging period s2; the charging preparation period within the current row driving cycle serves as the line buffer between the charging period s2 within the current row driving cycle and the charging period s2 within the previous row driving cycle.

[0103] In other embodiments, not only is a non-charging period s1 set between the start time of the row driving cycle p0 and the start time of the charging period, but also a non-charging period (generally also referred to as a charging end stabilization period) is set between the end time of the charging period and the end time of the row driving cycle. The charging preparation period within the current row driving cycle p0 and the charging end stabilization period within the previous row driving cycle together serve as the line buffer between the charging period s2 within the current row driving cycle and the charging period s2 within the previous row driving cycle. No corresponding drawings are given for this situation here.

[0104] It should be noted that Figure 6 Gn+1 to Gn+9 in Figure 6 respectively represent the (n + 1)-th to (n + 9)-th gate lines, that is, Figure 6 in

[0105] Figure 7 shows the timing diagram of the voltage Vpph to be output inside the power supply module in the related art and a frame of display. As Figure 7 shown, in the related art, the design of the working frequency of the power supply module only considers the power consumption factor. Generally, under the condition of meeting the requirements of resistance-capacitance delay and power supply demand, the working frequency is set as small as possible to achieve the purpose of reducing power consumption.

[0106] See Figure 7 As shown, the time when the power supply module in the related art outputs the working voltage will be located in the charging period within some line driving cycles, and the corresponding positions in different charging periods are different. For example, Figure 7 in [reference] the time t1 when the power supply module outputs the working voltage is located at a position relatively late in the charging period of the (n + 4)-th line driving cycle, and the time t2 when the power supply module outputs the working voltage is located at a position relatively in the middle of the charging period of the (n + 8)-th line driving cycle.

[0107] In addition, for different frame images, the line driving cycles in which the power supply module outputs the working voltage are also different; for example, in the process of displaying the current frame image, the time when the power supply module outputs the working voltage is as Figure 7 in [reference] located in the (n + 4)-th line driving cycle and the (n + 8)-th line driving cycle; however, in the process of displaying the next frame image, the time when the power supply module outputs the working voltage may be located in the (n + 3)-th line driving cycle and the (n + 7)-th line driving cycle (the corresponding drawings are not given).

[0108] When the power supply module outputs the working voltage to the display panel, it will cause certain interference to the process of writing the data voltage to the sub-pixels by the data line. Especially when the voltage on the data line needs to change greatly (that is, there is a large difference in the data voltages loaded by two pixel units located in the same column and adjacent rows, and at this time the data line is in a heavy load state), the interference of the working voltage output by the display panel to the charging of the sub-pixels will be amplified, resulting in the data voltage not being accurately written to the sub-pixels, and then resulting in abnormal display of the sub-pixels, and finally resulting in mura in the display panel.

[0109] To effectively solve the above technical problems, the present disclosure provides corresponding solutions. The following will be described in detail with specific embodiments.

[0110] Figure 8 The flowchart of a voltage output control method provided by an embodiment of the present disclosure is as Figure 8 shown. This voltage output control method is applied to a voltage output control system. This voltage output control method is used to control the power supply module to provide the required working voltage to the display panel. The process of the display panel displaying a frame image includes a plurality of line driving cycles performed in sequence. The line driving cycle includes: a charging period and a non-charging period; during the charging period, the data line is conducted with the sub-pixels corresponding to the row to write the data voltage to the corresponding sub-pixels; during the non-charging period, the data line is open-circuited with the sub-pixels. This voltage output control method includes:

[0111] Step S2, control the power supply module to output at a preset first working frequency during the process of displaying the to-be-displayed image, and the time when the power supply module outputs the working voltage to the display panel does not overlap with the charging period.

[0112] In the embodiments of the present disclosure, the operating frequency of the power supply module is controlled, and the time when the power supply module outputs the operating voltage to the display panel is not within the charging period; that is to say, the time when the power supply module outputs the operating voltage (which is a very short period of time) is staggered from the sub-pixel charging period. Therefore, the process of the power supply module outputting the operating voltage will not interfere with the charging process of any row of sub-pixels, and the occurrence of mura can be effectively avoided.

[0113] Figure 9a The flowchart of another voltage output control method provided by the embodiments of the present disclosure is as Figure 9a shown, and the voltage output control method includes:

[0114] Step S1, detecting whether the to-be-displayed screen is a first screen.

[0115] Wherein, when it is detected in step S1 that the to-be-displayed screen is a first screen, the following step S2 is executed.

[0116] Step S2, controlling the power supply module to output at a preset first operating frequency during the process of displaying the to-be-displayed screen, and the time when the power supply module outputs the operating voltage to the display panel does not overlap with the charging period.

[0117] In the embodiments of the present disclosure, the "first screen" is a screen that meets certain preset conditions as required. That is to say, in the embodiments of the present disclosure, for the screen that meets the preset conditions, the power supply method in step S2 can be adopted.

[0118] In some embodiments, the first screen may be a heavy-load screen; wherein, the heavy-load screen refers to a screen in which the frequency and / or amplitude of the change of the data voltage of different sub-pixels within each column of sub-pixels are relatively large; it reflects that the frequency and amplitude of the change of the data voltage output by the same signal channel on the source driver chip during the display process are relatively large, which will make the output of the source driver chip more difficult and the source driver chip is in a high-load state.

[0119] In the embodiments of the present disclosure, before displaying the to-be-detected display screen, it can be first detected whether the to-be-displayed screen is a heavy-load screen, and when it is detected that the to-be-displayed screen is a heavy-load screen, the operating frequency of the power supply module can be controlled, and the time when the power supply module outputs the operating voltage to the display panel is not within the charging period. That is to say, during the process of displaying the heavy-load screen, the time when the power supply module outputs the operating voltage (which is a very short period of time) is staggered from the sub-pixel charging period. Therefore, the process of the power supply module outputting the operating voltage will not interfere with the charging process of any row of sub-pixels, and the occurrence of mura can be effectively avoided, thereby ensuring the normal display of the heavy-load screen.

[0120] Figure 9b A flowchart of another voltage output control method provided by an embodiment of the present disclosure is as follows. As Figure 9b shown, different from the previous embodiments, in the Figure 9a embodiment shown, it not only includes step S1 and step S2, but also includes step S3. Optionally, the first screen in step S1 is an overload screen. When it is determined in step S1 that the screen to be displayed is an overload screen, step S2 is executed; when it is determined in step S1 that the screen to be displayed is not an overload screen, step S3 is executed. Only step S3 will be described in detail below.

[0121] Step S3: Control the power supply module to output at a preset second operating frequency when displaying the screen to be displayed.

[0122] Wherein, the second operating frequency is less than the first operating frequency.

[0123] As a specific implementation manner, the first operating frequency is 72KHZ, and the second operating frequency is 33kHZ. The specific values of the first operating frequency and the second operating frequency can be set according to actual needs.

[0124] In the embodiment of the present disclosure, when it is detected in step S1 that the screen to be displayed is an overload screen, control the power supply module to output at a preset first operating frequency during the process of displaying the screen to be displayed, and the time when the power supply module outputs the working voltage to the display panel does not overlap with the charging period, so as to avoid the interference of the process of the power supply module outputting the working voltage on the charging process of the sub-pixels and ensure the normal display of the overload screen. When it is detected in step S1 that the screen to be displayed is not an overload screen (that is, the screen to be displayed is a light load screen), control the power supply module to output at a second operating frequency lower than the first operating frequency when displaying the screen to be displayed. Since the operating frequency of the power supply module is reduced, the power consumption of the power supply module is correspondingly reduced.

[0125] Wherein, the second operating frequency can be the operating frequency adopted when the operating frequency is set as small as possible while meeting the requirements of RC delay and power supply demand in the prior art.

[0126] In step S3, although there will be a situation where the time when the power supply module outputs the working voltage overlaps with the charging period (the process of the power supply module outputting the working voltage interferes with the charging process of the sub-pixels), but since the screen to be displayed is a light load screen, the interference of the process of the power supply module outputting the working voltage on the charging process of the sub-pixels is relatively small, and the risk of mura in the display screen is small and obvious mura will not occur.

[0127] It can be seen that the technical solution of the present disclosure can effectively avoid mura when displaying an overload screen and reduce power consumption when displaying a light load screen.

[0128] It should be noted that when it is detected that the to-be-displayed screen is not a reloaded screen, the situation of using step S3 to control the power supply module to output at a preset second working frequency when displaying the to-be-displayed screen is only a preferred implementation in the embodiments of the present disclosure, which can effectively reduce power consumption. Those skilled in the art should know that in the embodiments of the present disclosure, it is also possible to use, when it is detected that the to-be-displayed screen is not a reloaded screen, the method of controlling the power supply module to output at a preset first working frequency during the process of displaying the to-be-displayed screen as in step S2, and the time when the power supply module outputs the working voltage does not overlap with the charging period for output (to avoid interference of the process of the power supply module outputting the working voltage on the charging process of the sub-pixels); or, controlling the power supply module to output at a third working frequency higher than the first working frequency (to improve the output capacity of the power supply module). These situations should also fall within the protection scope of the present disclosure.

[0129] In some embodiments, step S2 specifically includes: step S201.

[0130] Step S201: During the process of displaying the to-be-displayed screen, send a first clock signal with a first clock frequency to the power supply module, so that the power supply module outputs at the first working frequency.

[0131] Step S3 specifically includes: step S301.

[0132] Step S301: During the process of displaying the to-be-displayed screen, send a second clock signal with a second clock frequency to the power supply module, so that the power supply module outputs at the second working frequency; the second clock frequency is less than the first clock frequency.

[0133] Based on the foregoing content, it can be seen that the working frequency (output frequency) of the power supply module is positively correlated with the clock frequency of the clock signal received by the internal boost voltage thereof. That is, the higher the clock frequency of the clock signal received by the power supply module, the higher the output frequency of the power supply module (the specific mapping relationship between the clock frequency and the output frequency of the power supply module is determined by the internal structure of the power supply module). By controlling the frequency of the clock signal output to the power supply module, the working frequency of the power supply module can be controlled.

[0134] In some embodiments, the first working frequency f1 satisfies: Q is an integer and 1 ≤ N ≤ 5, and t0 is the duration corresponding to one line driving period.

[0135] Figure 10 This is a timing schematic diagram of the to-be-output voltage Vpph inside the power supply module in the present disclosure for displaying one frame of a screen, as Figure 10As shown, when displaying the overload screen, the period for the power supply module to output the working voltage is Q*t0, which is an integer multiple of one line driving period. That is to say, it is only necessary that the time when the power supply module first outputs the working voltage during the display of the overload screen is located in the non-charging period within a certain line driving period, so as to ensure that the time when the power supply module outputs the working voltage subsequently is also definitely located in the non-charging period within the line driving period.

[0136] As an example, Q is taken as 2. In Figure 10 when displaying the overload screen, the time t1 for the power supply module to output the working voltage is located in the non-charging period within the (n + 3)-th line driving period, the time t2 for the power supply module to output the working voltage is located in the non-charging period within the (n + 5)-th line driving period, the time t3 for the power supply module to output the working voltage is located in the non-charging period within the (n + 7)-th line driving period, and the time t4 for the power supply module to output the working voltage is located in the non-charging period within the (n + 9)-th line driving period.

[0137] When displaying the non-overload screen, the power supply module operates at the second working frequency. For specific content, reference can be made to the previous description of Figure 7 and details will not be elaborated here.

[0138] Figure 11 This is a flowchart of an optional implementation method for step S1 in the embodiments of the present disclosure. As shown in Figure 9a 、 Figure 9b and Figure 11 in some embodiments, step S1 includes:

[0139] Step S101: Determine the overload degree of the to-be-displayed screen according to the changes in the data voltages of different sub-pixels within each column of sub-pixels in the to-be-displayed screen.

[0140] In some embodiments, the display panel includes M*N sub-pixels arranged in an array of N rows and M columns; step S101 includes:

[0141] Step S1011: Calculate the degree of change in the data voltage between any two adjacent sub-pixels in the row direction within the same column, compare them with the preset change degree threshold respectively, and count the frequency of the degree of change in the data voltage greater than the preset change degree threshold.

[0142]

[0143] S (n_m,n+1_m) represents the degree of change in the data voltage between the sub-pixel located in the n-th row and the m-th column and the sub-pixel located in the (n + 1)-th row and the m-th column, V n_m represents the data voltage of the sub-pixel located in the n-th row and the m-th column, V n+1_mThe data voltage of the sub-pixel located in the (n + 1)-th row and the m-th column, where n is an integer and 1 ≤ n ≤ N - 1, and m is an integer and 1 ≤ m ≤ M.

[0144] As an example, the value of the preset change degree threshold is generally greater than or equal to 50%, such as 55%, 60%, 65%, 70%, 80%, 85%, 90%, 95%, etc., and can be pre-designed and adjusted according to actual needs.

[0145] Step S1012: Determine the overload degree of the to-be-displayed screen according to the frequency of the data voltage change degree greater than the preset change degree threshold.

[0146]

[0147] P represents the overload degree of the to-be-displayed screen, and K represents the frequency of the data voltage change degree greater than the preset change degree threshold.

[0148] Step S102: Judge whether the to-be-displayed screen is an overloaded screen according to the overload degree and the preset degree threshold.

[0149] If the overload degree is greater than the preset degree threshold, it is judged that the to-be-displayed screen is an overloaded screen; if the overload degree is less than or equal to the preset degree threshold, it is judged that the to-be-displayed screen is not an overloaded screen (i.e., a lightly loaded screen).

[0150] As an example, the value of the preset degree threshold is generally greater than or equal to 50%, such as 55%, 60%, 65%, 70%, 80%, 85%, 90%, 95%, etc., and can be pre-designed and adjusted according to actual needs.

[0151] It should be noted that the above situation of judging whether the display screen is an overloaded screen based on Step S101 and Step S102 is only an optional implementation manner in the embodiments of the present disclosure, and it will not limit the technical solution of the present disclosure. In the art, "overloaded screen" is a well-known term in the art, and in the present disclosure, other algorithms in related technologies can also be used to judge whether a certain screen is an overloaded screen, which will not be elaborated here.

[0152] Based on the same inventive concept, the embodiments of the present disclosure further provide a voltage output control system, which is used to control the power supply module to provide the required working voltage for the display panel. The process of the display panel displaying a frame of the screen includes a plurality of row driving cycles performed in sequence. The row driving cycle includes: a charging period and a non-charging period; during the charging period, the data line is conducted with the sub-pixels of the corresponding row to write the data voltage into the corresponding sub-pixels; during the non-charging period, the data line is disconnected from the sub-pixels.

[0153] Figure 12The block diagram of a voltage output control system provided by an embodiment of the present disclosure is as follows Figure 12 As shown, the voltage output control system includes: a first control module 32.

[0154] The first control module 32 is configured to control the power supply module to output at a preset first operating frequency during the display of the to-be-displayed screen, and the time when the power supply module outputs the operating voltage to the display panel does not overlap with the charging period.

[0155] In some embodiments, the voltage output control system further includes: a detection module 31; the detection module 31 is configured to detect whether the to-be-displayed screen is a first screen.

[0156] At this time, the first control module 32 is specifically configured to, when the detection module detects that the to-be-displayed screen is the first screen, control the power supply module to output at a preset first operating frequency during the display of the to-be-displayed screen, and the time when the power supply module outputs the operating voltage to the display panel does not overlap with the charging period.

[0157] In some embodiments, the first screen is a heavy load screen.

[0158] Further, in some embodiments, the voltage output control system further includes: a second control module 33. Wherein, the second control module 33 is configured to, when the detection module 31 detects that the to-be-displayed screen is not the first screen, control the power supply module to output at a preset second operating frequency during the display of the to-be-displayed screen; the second operating frequency is less than the first operating frequency.

[0159] In some embodiments, the first control module 32 specifically includes: a first clock output unit. Wherein, the first clock output unit is configured to send a first clock signal with a first clock frequency to the power supply module during the display of the to-be-displayed screen, so that the power supply module outputs at the first operating frequency.

[0160] The second control module 33 specifically includes: a second clock output unit. Wherein, the second clock output unit is configured to send a second clock signal with a second clock frequency to the power supply module during the display of the to-be-displayed screen, so that the power supply module outputs at the second operating frequency; the second clock frequency is less than the first clock frequency.

[0161] In some embodiments, the first operating frequency f1 satisfies:

[0162]

[0163] Q is an integer and 1 ≤ N ≤ 5, and t0 is the duration corresponding to one line driving cycle. In some embodiments, Q takes a value of 2.

[0164] In some embodiments, the display panel includes: multiple columns of sub-pixels, each column of sub-pixels is configured with a corresponding data line, and the sub-pixels located in the same column are all connected to the corresponding data line;

[0165] The detection module 31 includes: a determination unit 311 and a judgment unit 312. Among them, the determination unit 311 is used to determine the overload degree of the to-be-displayed picture according to the change of the data voltage of different sub-pixels in each column of sub-pixels in the to-be-displayed picture; the judgment unit 312 is used to judge whether the to-be-displayed picture is the first picture according to the overload degree and a preset degree threshold; if the overload degree is greater than the preset degree threshold, it is judged that the to-be-displayed picture is the first picture; if the overload degree is less than or equal to the preset degree threshold, it is judged that the to-be-displayed picture is not the first picture.

[0166] In some embodiments, the display panel includes M*N sub-pixels arranged in an array of N rows and M columns;

[0167] The determination unit 311 includes: a first operator unit and a second operator unit.

[0168] Among them, the first operator unit is used to calculate the degree of change of the data voltage between any two adjacent sub-pixels in the row direction and located in the same column, compare them with the preset change degree threshold respectively, and count the frequency of the degree of change of the data voltage greater than the preset change degree threshold;

[0169]

[0170] S (n_m,n+1_m) represents the degree of change of the data voltage between the sub-pixel located in the nth row and the mth column and the sub-pixel located in the (n + 1)th row and the mth column, V n_m represents the data voltage of the sub-pixel located in the nth row and the mth column, V n+1_m represents the data voltage of the sub-pixel located in the (n + 1)th row and the mth column, n is an integer and 1 ≤ n ≤ N - 1, m is an integer and 1 ≤ m ≤ M;

[0171] The second operator unit is used to determine the overload degree of the to-be-displayed picture according to the frequency of the degree of change of the data voltage greater than the preset change degree threshold;

[0172]

[0173] P represents the overload degree of the to-be-displayed picture, and K represents the frequency of the degree of change of the data voltage greater than the preset change degree threshold.

[0174] For the specific descriptions of the above modules, units, and sub-units, reference can be made to the relevant content described in the foregoing method embodiments, and details are not repeated here.

[0175] Based on the same inventive concept, embodiments of the present disclosure further provide a display control system. Refer to Figure 1 As shown, the display control system includes: a power supply module and a voltage output control system. Among them, the voltage output control system adopts the voltage output control system provided in the previous embodiment, and the specific content can be referred to the content in the previous embodiment, which will not be elaborated here.

[0176] Based on the same inventive concept, embodiments of the present disclosure further provide a display device. Refer to Figure 1 As shown, the display device includes: a display panel and a display control system. Among them, the display control system adopts the display control system provided in the previous embodiment, and the specific content can be referred to the content in the previous embodiment, which will not be elaborated here.

[0177] Based on the same inventive concept, embodiments of the present disclosure further provide an electronic device. Figure 13 It is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure. As Figure 13 shown, an electronic device provided by an embodiment of the present disclosure includes: one or more processors 101, a memory 102, and one or more I / O interfaces 103. One or more programs are stored on the memory 102. When the one or more programs are executed by the one or more processors, the one or more processors implement the voltage output control method as described in any of the above embodiments; one or more I / O interfaces 103 are connected between the processor and the memory and are configured to implement information interaction between the processor and the memory.

[0178] Among them, the processor 101 is a device with data processing capabilities, including but not limited to a central processing unit (CPU), etc.; the memory 102 is a device with data storage capabilities, including but not limited to a random access memory (RAM, more specifically such as SDRAM, DDR, etc.), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory (FLASH); the I / O interface (read / write interface) 103 is connected between the processor 101 and the memory 102 and can implement information interaction between the processor 101 and the memory 102, including but not limited to a data bus (Bus), etc.

[0179] In some embodiments, the processor 101, the memory 102, and the I / O interface 103 are interconnected through a bus 104 and are further connected to other components of the computing device.

[0180] In some embodiments, the one or more processors 101 include a field programmable gate array.

[0181] According to an embodiment of the present disclosure, there is also provided a computer-readable medium. A computer program is stored on the computer-readable medium, wherein when the program is executed by a processor, the steps in the voltage output control method according to any one of the above embodiments are implemented.

[0182] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, including a computer program carried on a machine-readable medium, the computer program including program code for performing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), the above functions defined in the system of the present disclosure are executed.

[0183] It should be noted that the computer-readable medium shown in the present disclosure can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program, and the program can be used by or combined with an instruction execution system, apparatus, or device. And in the present disclosure, the computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, wherein the computer-readable program code is carried. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium can also be any computer-readable medium other than the computer-readable storage medium, and the computer-readable medium can send, propagate, or transmit a program for use by or combined with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted by any suitable medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0184] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a portion of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that, in some alternative implementations, the functions noted in the blocks may occur in a different order than that noted in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system that performs the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0185] The circuits or sub-circuits described in the embodiments of the present disclosure can be implemented in software or in hardware. The described circuits or sub-circuits can also be provided in a processor. For example, it can be described as a processor including a receiving circuit and a processing circuit, and the processing module includes a writing sub-circuit and a reading sub-circuit. Among them, the names of these circuits or sub-circuits do not, in some cases, constitute a limitation on the circuits or sub-circuits themselves. For example, the receiving circuit can also be described as "receiving a video signal".

[0186] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present disclosure, and the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.

Claims

1. A voltage output control method, characterized in that, It is used to control the power supply module to provide the required working voltage for the display panel. The process of the display panel displaying a frame of picture includes multiple row driving cycles performed in sequence. Each row driving cycle includes a charging period and a non-charging period. During the charging period, the data line is conducted with the sub-pixels of the corresponding row to write the data voltage into the corresponding sub-pixels. During the non-charging period, the data line is disconnected from the sub-pixels. The voltage output control method includes: Detecting whether the picture to be displayed is a heavy-load picture; When it is detected that the picture to be displayed is a heavy-load picture, controlling the power supply module to output at a preset first working frequency during the process of displaying the picture to be displayed, and the time when the power supply module outputs the working voltage to the display panel does not overlap with the charging period; When it is detected that the picture to be displayed is not a heavy-load picture, controlling the power supply module to output at a preset second working frequency during the process of displaying the picture to be displayed; the second working frequency is less than or equal to the first working frequency.

2. The voltage output control method according to claim 1, wherein The step of controlling the power supply module to output at a preset first working frequency during the process of displaying the picture to be displayed includes: During the process of displaying the picture to be displayed, sending a first clock signal with a first clock frequency to the power supply module, so that the power supply module outputs at the first working frequency; The step of controlling the power supply module to output at a preset second working frequency during the process of displaying the picture to be displayed includes: During the process of displaying the picture to be displayed, sending a second clock signal with a second clock frequency to the power supply module, so that the power supply module outputs at the second working frequency; The second clock frequency is less than the first clock frequency.

3. The voltage output control method according to claim 1, wherein The display panel includes: multiple columns of sub-pixels, each column of sub-pixels is configured with a corresponding data line, and the sub-pixels located in the same column are all connected to the corresponding data line; The step of detecting whether the picture to be displayed is a first picture includes: Determining the heavy-load degree of the picture to be displayed according to the changes of the data voltages of different sub-pixels in each column of sub-pixels in the picture to be displayed; Judging whether the picture to be displayed is a first picture according to the heavy-load degree and a preset degree threshold; Wherein, if the heavy-load degree is greater than the preset degree threshold, it is judged that the picture to be displayed is a first picture; If the heavy-load degree is less than or equal to the preset degree threshold, it is judged that the picture to be displayed is not a first picture.

4. The voltage output control method according to claim 3, wherein The display panel includes M*N sub-pixels arranged in an array of N rows and M columns; The step of determining the heavy-load degree of the picture to be displayed according to the changes of the data voltages of different sub-pixels in each column of sub-pixels in the picture to be displayed includes: Calculating the degree of change of the data voltage between any two sub-pixels that are adjacent in the row direction and located in the same column, and respectively comparing it with a preset change degree threshold, and counting the frequency of the degree of change of the data voltage that is greater than the preset change degree threshold; S (n_m,n+1_m) represents the degree of data voltage change between the sub-pixel located in the n-th row and m-th column and the sub-pixel located in the (n + 1)-th row and m-th column, V n_m represents the data voltage of the sub-pixel located in the n-th row and m-th column, V n+1_m represents the data voltage of the sub-pixel located in the (n + 1)-th row and m-th column, where n is an integer and 1 ≤ n ≤ N - 1, and m is an integer and 1 ≤ m ≤ M; Determining the heavy-load degree of the picture to be displayed according to the frequency of the degree of change of the data voltage that is greater than the preset change degree threshold; P represents the overload degree of the to-be-displayed screen, and K represents the frequency of the data voltage change degree greater than the preset change degree threshold.

5. The voltage output control method according to any one of claims 1 to 4, characterized in that, The first operating frequency f1 satisfies: Q is an integer and 1 ≤ N ≤ 5, and t0 is the duration corresponding to one row driving period.

6. A voltage output control system, characterized in that, It is used to control the power supply module to provide the required operating voltage to the display panel. The process of the display panel displaying a frame of picture includes multiple row driving periods in sequence. The row driving period includes: a charging period and a non-charging period; during the charging period, the data line is conducted with the sub-pixels of the corresponding row to write the data voltage into the corresponding sub-pixels; during the non-charging period, the data line is disconnected from the sub-pixels. The voltage output control system includes: A detection module for detecting whether the to-be-displayed screen is an overloaded screen. A first control module for controlling the power supply module to output at a preset first operating frequency during the process of displaying the to-be-displayed screen when the detection module detects that the to-be-displayed screen is an overloaded screen, and the time when the power supply module outputs the operating voltage to the display panel does not overlap with the charging period. A second control module for controlling the power supply module to output at a preset second operating frequency during the process of displaying the to-be-displayed screen when the detection module detects that the to-be-displayed screen is not an overloaded screen; the second operating frequency is less than or equal to the first operating frequency.

7. The voltage output control system according to claim 6, wherein The first control module specifically includes: A first clock output unit for sending a first clock signal with a first clock frequency to the power supply module during the process of displaying the to-be-displayed screen, so that the power supply module outputs at the first operating frequency. The second control module specifically includes: A second clock output unit for sending a second clock signal with a second clock frequency to the power supply module during the process of displaying the to-be-displayed screen, so that the power supply module outputs at the second operating frequency; the second clock frequency is less than the first clock frequency.

8. The voltage output control system according to claim 6, characterized in that, The display panel includes: multiple columns of sub-pixels, each column of sub-pixels is configured with a corresponding data line, and the sub-pixels in the same column are all connected to the corresponding data line. The detection module includes: A determination unit for determining the overload degree of the to-be-displayed screen according to the change of the data voltage of different sub-pixels in each column of sub-pixels in the to-be-displayed screen. A judgment unit for judging whether the to-be-displayed screen is a first screen according to the overload degree and the preset degree threshold. If the overload degree is greater than the preset degree threshold, it is judged that the to-be-displayed screen is a first screen. If the overload degree is less than or equal to the preset degree threshold, it is judged that the to-be-displayed screen is not a first screen.

9. The voltage output control system according to claim 8, characterized in that The display panel includes M*N sub-pixels arranged in an array of N rows and M columns. The determination unit includes: The first operator unit is configured to calculate the degree of change in data voltage between any two sub-pixels located in the same column and adjacent in the row direction, compare them with a preset change degree threshold respectively, and count the frequency of the degree of change in data voltage greater than the preset change degree threshold; S (n_m,n+1_m) represents the degree of data voltage change between the sub-pixel located in the n-th row and the m-th column and the sub-pixel located in the (n + 1)-th row and the m-th column, V n_m represents the data voltage of the sub-pixel located in the n-th row and the m-th column, V n+1_m represents the data voltage of the sub-pixel located in the (n + 1)-th row and the m-th column, where n is an integer and 1 ≤ n ≤ N - 1, and m is an integer and 1 ≤ m ≤ M; The second operator unit is configured to determine the overload degree of the to-be-displayed picture according to the frequency of the degree of change in data voltage greater than the preset change degree threshold; P represents the overload degree of the to-be-displayed picture, and K represents the frequency of the degree of change in data voltage greater than the preset change degree threshold.

10. The voltage output control system according to any one of claims 6 to 9, characterized in that, The first working frequency f1 satisfies: Q is an integer and 1 ≤ N ≤ 5, and t0 is the duration corresponding to 1 row driving period.

11. A display control system, characterized in that, Comprising: A power supply module and the voltage output control system according to any one of claims 6 to 10 above.

12. A display device, characterized in that, Comprising: A display panel and the display control system according to claim 11 above.

13. An electronic device, characterized in that, Comprising: One or more processors; A memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the voltage output control method according to any one of claims 1 to 5.

14. The electronic device according to claim 13, characterized in that, The processor includes a field programmable gate array.

15. A computer-readable medium having a computer program stored thereon, characterized in that, The computer program implements the steps in the voltage output control method according to any one of claims 1 to 5 when executed by a processor.

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