A reactive atmosphere annealing method for eliminating surface damage layers of compound semiconductor crystals

Abstract

This invention provides a reactive atmosphere annealing method for eliminating surface damage layers in compound semiconductor crystals, solving the problem of introducing new surface damage during existing wafer surface treatment processes, leading to wafer quality deterioration and affecting subsequent device fabrication. This method involves introducing a reactive atmosphere at high temperature after the ingot is cut and polished to react with defects and stress layers on the wafer surface, generating inert substances or volatile gases. During high-temperature annealing, the products are converted into gaseous substances and discharged with the protective atmosphere, resulting in an ideal crystal surface. In addition to controlling internal defects generated during crystal growth, the reactive atmosphere also reacts to remove the surface processing layer.

Description

Technical Field

[0001] This invention belongs to the field of compound semiconductor crystal processing technology, specifically relating to a reactive atmosphere annealing method for eliminating the surface damage layer of a compound semiconductor crystal, which uses a reactive atmosphere to anneal the compound semiconductor crystal while eliminating the surface damage layer. Background Technology

[0002] Since the 1920s, artificial crystal growth technology has advanced rapidly, enabling compound semiconductor crystal materials, such as III-V and II-VI compounds, oxide semiconductors, and metal halide compounds, to be widely used in defense industries, daily life, high technology, and basic scientific research. Applications in high-precision fields have also placed higher demands on crystal quality.

[0003] In the actual growth process of compound semiconductor crystals, due to limitations in growth technology and issues such as thermal stress release and melt mass transfer during growth, a large number of structural defects exist in the crystal, which seriously affect the crystal's performance. Therefore, in order to meet the requirements for fabricating high-performance devices, an annealing method is often used, in which the crystal deviates from the equilibrium state is heated to a high temperature and held for a certain time, and then cooled at a certain cooling rate to obtain an annealing method that is close to the equilibrium state. This method further controls the defect state inside the crystal to improve or homogenize the various properties of the crystal.

[0004] Besides visible defects such as scratches, spots, and oxidation marks, crystal surfaces can also contain surface damage zones, even on bright, scratch-free wafer surfaces visible under a microscope. During crystal processing, process parameters such as the feed rate during dicing and the abrasive grain size and intensity during polishing all affect the thickness of the surface damage layer during ingot dicing. During mechanical polishing of wafers, a damage layer exists near the surface, consisting of stress concentrations, electrically active defects, impurities, and micro-scratches and micro-undulations invisible to the naked eye. These surface damage layers introduced during processing significantly impact subsequent crystal applications such as device fabrication, substrate growth, and performance testing.

[0005] An ideal surface is defined as the outermost layer without any adsorbents and arranged in the same lattice as the bulk crystal, the only difference being an abrupt interruption in the direction perpendicular to the surface. Ideal surfaces do not exist in reality. Actual surfaces are categorized by their cleanliness level into uncleaned surfaces, clean surfaces, and vacuum-cleaned surfaces. Uncleaned surfaces contain a considerable amount of contaminants and adsorbents. Clean surfaces, despite undergoing special cleaning, still contain various adsorbents and oxides in the natural environment. Vacuum-cleaned surfaces are those that, after thorough cleaning, undergo ion bombardment to remove the adsorbent layer under a certain vacuum, followed by annealing, and are then preserved under high or ultra-high vacuum conditions.

[0006] The patent "Jie Wanqi, Hou Wenxin, Wang Tao, Zha Gangqiang, Xu Lingyan. Surface Treatment Method for CdZnTe Planar Detector [P]. Shaanxi: CN107123698A, 2017-09-01" points out that after mechanical polishing, a damaged layer exists near the surface of the CdZnTe crystal. Etching the crystal with a certain proportion of Br-MeOH for several minutes yields a bright surface. However, the etched CdZnTe surface is rich in Te and highly reactive, which can cause a large leakage current after applying a high bias voltage to the deposition electrode, leading to increased background noise and decreased energy resolution. Furthermore, the highly reactive Te-rich layer is easily oxidized in air and adsorbs various impurities, which can adversely affect the detector performance.

[0007] The literature “Stach S, Lu T, Dallaev R, et al. Evaluation of the Topographical Surface Changes of Silicon Wafers after Annealing and Plasma Cleaning[J].Silicon,2020,12(11):2563-2570” describes the treatment of Si crystal surfaces using different combinations of annealing times and plasma cleaning methods. The surface morphology under different treatment conditions was observed using AFM (atomic force microscopy). The Si surface is sensitive to plasma cleaning time; increasing the annealing and cleaning time increases the surface roughness of Si, which is detrimental to obtaining a smooth and flat surface.

[0008] It is evident that existing wafer processing methods introduce new surface damage, leading to wafer quality deterioration and affecting subsequent device fabrication. Therefore, it is necessary to propose a new wafer processing method. Summary of the Invention

[0009] This invention addresses the problem of introducing new surface damage in existing wafer surface treatment processes (such as mechanical cutting and polishing), which leads to wafer quality deterioration and affects subsequent device fabrication. It combines annealing with surface damage layer treatment to provide a reactive atmosphere annealing method for eliminating surface damage layers in compound semiconductor crystals. This two-step reactive atmosphere annealing process eliminates the processing damage layer on the wafer surface and improves wafer quality.

[0010] To achieve the above objectives, the technical solution provided by this invention is:

[0011] A reactive atmosphere annealing method for eliminating damage layers on the surface of compound semiconductor crystals, characterized by comprising the following steps:

[0012] 1) Ingot cutting:

[0013] The ingot is fixed to the sample stage using paraffin wax or hot melt adhesive, and then cut on a diamond wire cutter to obtain a wafer of the target size. The size is adjusted according to the requirements, and the diamond wire cutter is set with the appropriate parameters according to the requirements during cutting. Among these, using hot melt adhesive to fix the wafer may make it difficult to remove or cause damage to the wafer during removal. Therefore, fixing with paraffin wax is preferred as it is more reliable.

[0014] 2) Wafer grinding and polishing:

[0015] Use sandpaper to polish the wafer obtained in step 1) until there are no visible scratches on the surface, and then polish the wafer.

[0016] 3) Annealing in a low-temperature reaction atmosphere:

[0017] 3.1) Place the polished wafer from step 2) on an annealing rack of appropriate size, place it in a vacuum atmosphere tube furnace, and purge it with a protective atmosphere.

[0018] 3.2) Close the tail valve of the vacuum atmosphere tubular furnace and evacuate to 10Pa - 1.0 × 10⁻¹⁰ Pa. -3 Pa, a reaction atmosphere is introduced; the reaction atmosphere is an atmosphere that can react with the wafer and the reaction products can be removed at high temperature;

[0019] 3.3) Raise the temperature of the vacuum atmosphere tube furnace to the low-temperature annealing point and carry out the heat preservation reaction;

[0020] 4) High-temperature annealing:

[0021] After the reaction is complete, the reaction atmosphere is removed, a protective atmosphere is introduced for purging, and the temperature is raised to above the boiling point of the reaction products and below the melting point of the wafer crystal. The temperature is maintained, and the reaction products are removed while the normal annealing is performed. The reaction products refer to the products generated after the reaction atmosphere and the wafer react, and their boiling points are obtained from research.

[0022] 5) After annealing, the exhaust gas is extracted and treated to obtain a compound semiconductor crystal with the surface damage layer eliminated.

[0023] Furthermore, step 2) specifically involves:

[0024] The wafer obtained in step 1) is polished sequentially using 500 grit, 1000 grit, 2000 grit, 3000 grit, and 5000 grit sandpaper. Gold velvet cloth and corresponding polishing media are used for polishing. Different polishing media are selected for different wafers.

[0025] Furthermore, in step 3.2), the reaction atmosphere is a silane atmosphere or a halogen atmosphere, such as SiCl4, CCl4, SiBr4, Br2, Cl2, etc.; specifically, the material properties of the wafer are consulted to select a suitable reactive atmosphere for the reaction to achieve the purpose.

[0026] The reaction atmosphere flow rate is 1-10 mL / min to ensure a more uniform reaction atmosphere in the chamber.

[0027] Further, in step 3.3), the low-temperature annealing heating rate is 5-10℃ / min; the low-temperature annealing temperature is 450℃-580℃; and the annealing time is 20min-60min.

[0028] Further, in step 4), the heating rate of the high-temperature annealing is 1-5℃ / min; the temperature of the high-temperature annealing is 700℃-1100℃ (the specific temperature is higher than the boiling point of the reaction product and lower than the melting point of the wafer), and the annealing time is 40min-240min.

[0029] Further, in step 4), the protective atmosphere during the annealing process is at least one of Ar and N2, and the protective atmosphere used in step 3.1) can be the same; the flow rate of the protective atmosphere during the annealing process is 0.1-0.5 L / min.

[0030] Furthermore, after the low-temperature annealing process is completed, the gas circuit valve is closed, the reaction atmosphere in the furnace is extracted using a vacuum pump, and the exhaust gas is treated by connecting a processing device.

[0031] Furthermore, after the high-temperature annealing process is completed, the gas circuit valve is closed, and the reaction product gas in the furnace is extracted using a vacuum pump and connected to a treatment device for exhaust gas treatment.

[0032] The aforementioned treatment device can be an existing exhaust gas treatment device.

[0033] Furthermore, in step (1), the annealing frame is a quartz crystal frame adapted to the wafer size;

[0034] The sample stage is made of graphite blocks and can be reused.

[0035] Meanwhile, the present invention also provides a compound semiconductor crystal, which is special in that the surface damage layer is eliminated by the above method.

[0036] The principle of this invention:

[0037] This method involves cutting and polishing the crystal ingot, then introducing a reactive atmosphere at high temperature to react with defects and stress layers on the wafer surface, generating inert substances or volatile gases. During high-temperature annealing, the products are converted into gaseous substances and discharged with the protective atmosphere, resulting in an ideal crystal surface. Introducing a reactive atmosphere not only controls internal defects generated during crystal growth but also removes the surface processing layer.

[0038] The advantages of this invention are:

[0039] 1. This invention, based on the surface state and composition of compound semiconductor surfaces after mechanical polishing, selects a reactive atmosphere for annealing. A corrosive atmosphere is chosen to react with the active surface of the mechanically processed wafer under annealing conditions. This effectively eliminates surface polishing damage while removing internal structural defects during annealing, thus facilitating subsequent processing steps (such as epitaxial growth, device fabrication, and performance characterization). Compared to traditional processes, this two-step reactive atmosphere annealing method not only reduces internal stress and defects generated during crystal growth but also removes surface defects (such as surface processing layers introduced during initial mechanical processing) through the reactive atmosphere, resulting in a clean surface and wafers with high surface and internal crystal quality, laying a solid foundation for subsequent wafer processing. Simultaneously, it simplifies operation, reduces defects introduced during processing, and saves time and costs. Furthermore, this method can be applied to most wafers that react with halogen atmospheres, is easy to operate, requires simple equipment, and has high feasibility and practicality.

[0040] 2. This invention combines the annealing process with the method of removing the surface adsorption layer and damage layer. During low-temperature annealing, the reaction atmosphere reacts with the crystal surface, and the products are removed at high temperature. This not only improves the surface condition of the wafer, but also regulates and homogenizes a large number of structural defects in the crystal to obtain a wafer in an ideal state.

[0041] 3. In this invention, after ingot cutting and mechanical polishing, the wafers are placed on a wafer annealing rack. A protective atmosphere is introduced for purging, followed by the introduction of halogen or silane compound gases to heat the furnace to a low-temperature annealing point for complete reaction. Then, a protective atmosphere is introduced again to raise the temperature to a high-temperature annealing temperature. After sufficient holding at this temperature, the reaction products are discharged with the protective atmosphere for exhaust gas treatment. This invention can simultaneously remove structural defects, surface and subsurface damage layers introduced by mechanical polishing of the wafer surface during a two-step annealing process, improving crystal quality and thus obtaining high-quality wafers. It also simplifies the operation and saves time and costs. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the device of the present invention;

[0043] Figure 2 This is a schematic flowchart of the method of the present invention;

[0044] Figure 3 This is a diagram showing the bicrystalline rocking curves of the wafer before and after annealing in Example 1;

[0045] Figure 4 The images show infrared transmission patterns of the wafer before and after annealing in Example 1, with (a) showing the wafer before annealing and (b) showing the wafer after annealing.

[0046] Figure 5 The images show the surface topography and AFM pattern of the annealed wafer in Example 1, with (a) being the surface topography and (b) being the AFM pattern.

[0047] Figure 6 This is a diagram showing the bicrystalline rocking curves of the wafer before and after annealing in Example 2;

[0048] Figure 7 The images show the surface topography and AFM pattern of the annealed wafer in Example 2. (a) is the surface topography image; (b) is the AFM pattern.

[0049] Figure 8 The images are AFM images of the wafer before and after annealing in Example 3; (a) before annealing, (b) after annealing;

[0050] Figure 9 The images show the infrared transmission of the wafer before and after annealing. (a) is before annealing, and (b) is after annealing.

[0051] Figure 10 The images show the surface topography and AFM image of the wafer after sanding. (a) is the surface topography image; (b) is the AFM image. Detailed Implementation

[0052] The following examples further illustrate specific implementations of the present invention, but the implementation and protection of the present invention are not limited thereto. It should be noted that any processes not specifically described below are those that can be implemented or understood by those skilled in the art by referring to existing technology. Reagents or instruments whose manufacturers are not specified are considered to be conventional products that can be purchased commercially.

[0053] See Figure 1 This is a general-purpose device for removing surface processing layers by reactive atmosphere annealing. After the wafer is polished, the wafer is placed on an annealing rack (used to hold the wafer) that is adapted to the wafer size and placed in a vacuum atmosphere tube furnace for annealing.

[0054] The invention will be further illustrated below with specific examples.

[0055] Example 1:

[0056] The first step is to fix the CdZnTe crystal ingot onto a graphite block with paraffin wax, and then cut the ingot on a diamond wire cutter to obtain the desired wafer.

[0057] The second step involves sequentially polishing the wafer surface with 500-grit, 1000-grit, 2000-grit, 3000-grit, and 5000-grit metallographic sandpaper. Then, coarse polishing is performed on a polishing cloth using 40mm-diameter magnesium oxide powder. Finally, the polishing medium is changed to a mixture of silica sol and hydrogen peroxide for fine polishing until the wafer surface is smooth and scratches are removed.

[0058] The third step involves placing the wafer on an annealing rack and then placing it in a vacuum tube furnace, where a vacuum of 1.0 × 10⁻⁶ is created. -1 Ar gas is introduced at a preferred flow rate of 0.3 L / min for 30 min for washing.

[0059] Step 4: Introduce Cl2 gas at a flow rate of 6 mL / min, heat to 550℃ at a heating rate of 10℃ / min, and hold for 60 min.

[0060] Step 5: Evacuate to 1.0×10 -1 Pa, close the tail valve, introduce Ar gas at a flow rate of 0.3 L / min, and heat to 970℃ at a heating rate of 5℃ / min, and hold for 60 min.

[0061] Step 6: Evacuate the furnace for 20 minutes to remove the exhaust gas. Close the furnace and remove the wafers.

[0062] In this embodiment, an annealed CdZnTe wafer is obtained. The reactant gas Cl2 reacts with the surface, and the resulting material is discharged with the exhaust gas at high temperature. Figure 3 The rocking curves of the twin crystals show good symmetry in the diffraction curves. The diffraction peak position increases from 38.16° to 38.23°, which is closer to the theoretical diffraction angle of the (111) crystal plane. The full width at half maximum (FWHM) decreases from 182" before annealing to 53" after annealing, and the peak intensity increases from 6230. -1 Rising to 6630 -1 This indicates that the crystal quality is significantly improved after annealing. Figure 4 Mid-infrared transmission imaging shows that the inclusion phases were almost completely eliminated after annealing. Figure 5 The AFM image shows that the crystal surface is smooth after reaction annealing, and an ideal crystal surface is obtained.

[0063] Example 2:

[0064] The first step is to fix the CdMnTe crystal ingot onto a graphite block with paraffin wax, and then cut the ingot on a diamond wire cutter at a cutting rate of 0.2 mm / min to obtain the desired wafer.

[0065] The second step is to polish the wafer surface with 1500-grit metallographic sandpaper, then use W10 and W5 diamond polishing paste on the polishing cloth for rough polishing, and then replace the polishing medium with a suspension of 0.05μm magnesium oxide powder and deionized water for fine polishing until the wafer surface is smooth and scratches are removed.

[0066] The third step is to place the wafer on an annealing rack and put it in a vacuum atmosphere tube furnace. The furnace is evacuated to 10 Pa and N2 gas is introduced at a flow rate of 0.3 L / min for 30 min for gas washing.

[0067] Step 4: Introduce Br2 gas at a flow rate of 5 mL / min, heat to 530℃ at a heating rate of 10℃ / min, and hold for 30 min.

[0068] Step 5: Evacuate to 10 Pa, close the tail valve, introduce N2 gas at a flow rate of 0.3 L / min, and heat to 1080℃ at a heating rate of 5℃ / min, and hold for 90 min.

[0069] Step 6: Evacuate the furnace for 20 minutes to remove the exhaust gas. Close the furnace and remove the wafers.

[0070] In this embodiment, an annealed CdMnTe wafer is obtained. The reactant gas Br2 reacts with the wafer surface, and the resulting material is discharged with the exhaust gas at high temperature. Figure 6 The rocking curves of the medium-sized twin crystals show good symmetry in the diffraction pattern. The full width at half maximum (FWHM) decreased from 69.1" before annealing to 53.2", and the peak intensity increased from 13223. -1 Rising to 15630 -1 The peak position increased from 38.27° before annealing to 38.34°, indicating a significant improvement in crystal quality. Figure 7 The AFM image shows that the crystal surface is smooth after reaction annealing, achieving an ideal surface treatment effect.

[0071] Example 3:

[0072] The first step is to fix the ZnTe ingot onto a graphite block with paraffin wax, and then cut the ingot on a diamond wire cutter at a cutting rate of 0.2 mm / min to obtain the desired wafer.

[0073] The second step involves using 500-grit, 1000-grit, 2000-grit, and 3000-grit metallographic sandpaper to polish the wafer surface in sequence. Then, a suspension of magnesium oxide powder and deionized water is used on a polishing cloth for coarse polishing, followed by fine polishing with silica sol until the wafer surface is smooth and mirror-like.

[0074] The third step involves placing the wafer on an annealing rack and then placing it in a vacuum tube furnace, where a vacuum of 1.0 × 10⁻⁶ is created. -2Pa, N2 gas is introduced at a preferred flow rate of 0.3 L / min for 30 min for gas washing.

[0075] Step 4: Introduce SiCl4 gas at a flow rate of 8 mL / min, heat to 540℃ at a heating rate of 10℃ / min, and hold for 40 min.

[0076] Step 5: Evacuate to 1.0×10 -1 Pa, close the tail valve, introduce N2 gas at a flow rate of 0.3 L / min, and heat to 760℃ at a heating rate of 3℃ / min, and hold for 120 min.

[0077] Step 6: Evacuate the furnace for 20 minutes to remove the exhaust gas. Close the furnace and remove the wafers.

[0078] This embodiment obtains a ZnTe wafer annealed in a reactive atmosphere. The reactive atmosphere SiCl4 reacts with the wafer surface, and the resulting product is discharged at high temperature with the protective atmosphere. Figure 8 The AFM plots show that the surface is smoother and less rough after reactive annealing compared to after grinding and polishing. Figure 9 The infrared transmission image shows that the size and number of inclusions inside the wafer are significantly reduced after annealing.

[0079] Comparative Example 1:

[0080] This comparative example relates to Example 1, but the CdZnTe wafer was not subjected to reactive atmosphere annealing. Instead, it was cut and sequentially polished at 500, 1000, 2000, 3000, and 5000 mesh. An AFM test was performed on the crystal surface, and the results are as follows: Figure 10 The results showed that after polishing with 5000-grit sandpaper, the chip surface was visibly shiny, but AFM observation revealed that many tiny scratches remained, which would affect the chip's future use.

[0081] In summary, this invention provides a universal annealing and surface damage layer removal method, which solves the problems of new surface defects and damage layers appearing in current wafer machining processes, as well as structural defects generated during crystal growth.

[0082] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the scope of the technology disclosed in the present invention, and such modifications or substitutions should all be covered within the scope of protection of the present invention.

Claims

1. A reactive atmosphere annealing method for eliminating the damage layer on the surface of a compound semiconductor crystal, characterized in that, Includes the following steps: 1) Ingot cutting: The ingot is fixed on the sample stage using paraffin wax or hot melt adhesive, and then cut on a diamond wire cutter as required to obtain a wafer of the target size. 2) Wafer grinding and polishing: Use sandpaper to polish the wafer obtained in step 1) until there are no visible scratches on the surface, and then polish the wafer. 3) Annealing in a low-temperature reaction atmosphere: 3.1) Place the polished wafer from step 2) on an annealing rack of appropriate size, place it in a vacuum atmosphere tube furnace, and purge it with a protective atmosphere. 3.2) Close the tail valve of the vacuum atmosphere tubular furnace and evacuate to 10Pa - 1.0 × 10⁻¹⁰. -3 Pa, a reaction atmosphere is introduced; the reaction atmosphere is an atmosphere that can react with the wafer and the reaction products can be removed at high temperature, specifically a silane atmosphere and a halogen atmosphere; 3.3) The temperature of the vacuum atmosphere tube furnace is raised to the low-temperature annealing point to carry out the reaction; the low-temperature annealing point is the temperature at which the reaction atmosphere reacts with the wafer, specifically 450℃-580℃; 4) High-temperature annealing: After the reaction is complete, the reaction atmosphere is removed, a protective atmosphere is introduced, and the temperature is raised to above the boiling point of the reaction products, specifically 700℃-1100℃, and then maintained at that temperature. 5) After annealing, the exhaust gas is extracted and treated to obtain a compound semiconductor crystal with the surface damage layer eliminated.

2. The reactive atmosphere annealing method for eliminating the surface damage layer of a compound semiconductor crystal according to claim 1, characterized in that, Step 2) specifically involves: The wafer obtained in step 1) was polished sequentially using 500 grit, 1000 grit, 2000 grit, 3000 grit, and 5000 grit sandpaper, and polished using velvet cloth and the corresponding polishing media.

3. The reactive atmosphere annealing method for eliminating the surface damage layer of a compound semiconductor crystal according to claim 1 or 2, characterized in that: In step 3.2), the flow rate of the reaction atmosphere is 1-10 mL / min.

4. The reactive atmosphere annealing method for eliminating the surface damage layer of a compound semiconductor crystal according to claim 3, characterized in that: In step 3.3), the heating rate of the low-temperature annealing is 5-10℃ / min; the reaction time is 20min-60min.

5. The reactive atmosphere annealing method for eliminating the surface damage layer of a compound semiconductor crystal according to claim 4, characterized in that: In step 4), the heating rate of the high-temperature annealing is 1-5℃ / min; the annealing time is 40min-240min.

6. The reactive atmosphere annealing method for eliminating the surface damage layer of a compound semiconductor crystal according to claim 5, characterized in that: In step 4), the protective atmosphere during the annealing process is Ar or N2; the flow rate of the protective atmosphere during the annealing process is 0.1-0.5 L / min.

7. The reactive atmosphere annealing method for eliminating the surface damage layer of a compound semiconductor crystal according to claim 6, characterized in that: After the low-temperature annealing process is completed, the gas circuit valve is closed, the reaction atmosphere in the furnace is extracted using a vacuum pump, and the exhaust gas is treated by connecting a processing device.

8. The reactive atmosphere annealing method for eliminating the surface damage layer of a compound semiconductor crystal according to claim 7, characterized in that: After the high-temperature annealing process is completed, the gas circuit valve is closed, and the reaction product gas in the furnace is extracted using a vacuum pump and connected to a treatment device for tail gas treatment.

9. The reactive atmosphere annealing method for eliminating the surface damage layer of a compound semiconductor crystal according to claim 8, characterized in that: The annealing frame is a quartz crystal frame adapted to the size of the wafer; The sample stage is made of graphite blocks.

10. A compound semiconductor crystal, characterized in that: The surface damage layer is eliminated by any of the methods described in claims 1-9.

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