Method for preparing semiconductor structure

Abstract

The present disclosure relates to a method for preparing a semiconductor structure. The method comprises: providing a substrate, wherein an interlayer dielectric layer is formed on the surface of the substrate; etching the interlayer dielectric layer to form an initial interconnection hole in the interlayer dielectric layer, and a portion of the interlayer dielectric layer is left at the bottom of the initial interconnection hole; performing thermal oxidation treatment on the structure obtained above, so that the portion of the interlayer dielectric layer at the bottom of the initial interconnection hole forms a thermal oxidation layer; performing ion implantation into the substrate through the thermal oxidation layer to form a damaged layer on the surface of the substrate; etching the thermal oxidation layer to expose the damaged layer on the surface of the substrate; forming a metal layer and a metal compound layer on the damaged layer on the surface of the substrate, wherein the metal compound layer is located on the surface of the substrate, and the metal layer is located on the surface of the metal compound layer away from the substrate. The use of this method can improve the macroscopic and microscopic morphologies of the metal layer in the obtained semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] With the development of semiconductor technology, a semiconductor structure has emerged. The semiconductor structure includes a dielectric material forming interconnection holes on a semiconductor material substrate, and a metal material is filled in the interconnection holes.

[0003] In conventional technology, the material to be etched (including a semiconductor material base layer and a dielectric layer covering the base layer) is first wet-etched to form interconnect holes, exposing the base layer covered by the dielectric layer in the interconnect holes, and then metal sputtering is performed.

[0004] However, due to the low stability of the wet etching process and large fluctuations in the etching rate, the microstructure formed after metal sputtering is inconsistent, and macroscopic anomalies such as color difference will appear on the metal surface. Summary of the invention

[0005] Based on this, it is necessary to provide a method for preparing a semiconductor structure that can eliminate metal color difference in interconnect holes in order to solve the above technical problems.

[0006] In a first aspect, the present disclosure provides a method for preparing a semiconductor structure. The method comprises:

[0007] Providing a substrate, wherein an interlayer dielectric layer is formed on a surface of the substrate;

[0008] Etching the interlayer dielectric layer to form an initial interconnection hole in the interlayer dielectric layer, with a portion of the interlayer dielectric layer remaining at the bottom of the initial interconnection hole;

[0009] Performing thermal oxidation treatment on the structure obtained above, so that the portion of the interlayer dielectric layer at the bottom of the initial interconnection hole forms a thermal oxidation layer;

[0010] Performing ion implantation into the substrate through the thermal oxidation layer to form a damaged layer on the surface of the substrate;

[0011] Etching the thermal oxide layer to expose the damaged layer on the surface of the substrate;

[0012] A metal layer and a metal compound layer are formed on the damaged layer on the surface of the substrate, wherein the metal compound layer is located on the surface of the substrate, and the metal layer is located on the surface of the metal compound layer away from the substrate.

[0013] In one embodiment, the substrate comprises a silicon substrate, and the metal compound comprises a metal silicide.

[0014] In one embodiment, the step of forming the interlayer dielectric layer on the surface of the substrate comprises:

[0015] forming an oxide layer on the surface of the substrate, wherein an opening exposing the substrate is formed in the oxide layer;

[0016] forming a first dielectric layer in the opening and on a surface of the oxide layer away from the substrate;

[0017] A second dielectric layer is formed on a surface of the first dielectric layer away from the substrate.

[0018] In one embodiment, the step of performing thermal oxidation treatment on the structure obtained above so as to form a thermal oxidation layer on the portion of the interlayer dielectric layer at the bottom of the initial interconnection hole comprises:

[0019] The obtained structure is subjected to rapid thermal oxidation treatment or low temperature thermal treatment, so that the portion of the interlayer dielectric layer at the bottom of the initial interconnection hole forms a thermal oxidation layer.

[0020] In one embodiment, the interlayer dielectric layer includes low-pressure tetraethyl orthosilicate and borophosphosilicate glass.

[0021] In one embodiment, the depth of the initial interconnect hole is less than the thickness of the interlayer dielectric layer; after the thermal oxide layer is formed, the total thickness of the thermal oxide layer and the interlayer dielectric layer retained at the bottom of the initial interconnect hole is

[0022] In one embodiment, forming a metal layer and a metal compound layer on the damaged layer on the surface of the substrate comprises:

[0023] forming a metal material layer on the damaged layer on the surface of the substrate;

[0024] removing the metal material layer located in the interlayer dielectric layer away from the surface of the substrate;

[0025] The obtained structure is alloyed to form the metal layer and the metal compound layer.

[0026] In one embodiment, the substrate includes a device region and an annular region located outside the device region, and interconnected holes are formed in the device region and the annular region; after forming the metal layer and the metal compound layer on the damaged layer on the surface of the substrate, the method further includes:

[0027] A protection layer is formed on a surface of the interlayer dielectric layer away from the substrate, the protection layer covers the annular region, an opening is formed in the protection layer, and the opening exposes the metal layer in the interconnection hole in the device region.

[0028] In one embodiment, forming a protective layer on a surface of the interlayer dielectric layer away from the substrate comprises:

[0029] forming a protective material layer on a surface of the interlayer dielectric layer away from the substrate;

[0030] The protective material layer is patterned to obtain the protective layer having the opening.

[0031] In one embodiment, forming a protective layer on a surface of the interlayer dielectric layer away from the substrate comprises:

[0032] forming a polyimide layer on a surface of the interlayer dielectric layer away from the substrate;

[0033] Patterning the polyimide layer to form the opening in the polyimide layer;

[0034] The patterned polyimide layer is cured to obtain the protective layer.

[0035] In one embodiment, the ions used in the ion implantation are argon ions, the energy range of the argon ions is 20 KeV to 50 KeV, and the implantation dose range of the argon ions is 1×10 12 ion / cm 3 ~1×10 13 ion / cm 3 .

[0036] The above-mentioned method for preparing a semiconductor structure first retains an interlayer dielectric layer on the substrate surface of the interconnection hole (during ion implantation, the interlayer dielectric layer is equivalent to a substrate protective layer), then adds a thermal oxidation process to turn the interlayer dielectric layer into a thermal oxidation layer, and then adds an ion implantation process to form a damaged layer on the substrate surface. The damaged layer lays the foundation for the nucleation of the metal layer and the formation of a new metal lattice without macroscopic color difference, ultimately achieving the beneficial effect of improving the macroscopic and microscopic morphology of the metal layer in the resulting semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description are used to explain the principles of the present disclosure, and do not constitute improper limitations on the present disclosure.

[0038] Figure 1 is a schematic flow chart of a method for preparing a semiconductor structure in one embodiment;

[0039] Figure 2 A schematic diagram of a cross-sectional structure of a semiconductor structure obtained in step S10 in one embodiment;

[0040] Figure 3 A schematic diagram of a cross-sectional structure of a semiconductor structure obtained in step S20 in one embodiment;

[0041] Figure 4 A schematic diagram of a cross-sectional structure of a semiconductor structure obtained in step S30 in one embodiment;

[0042] Figure 5 is a schematic diagram of a cross-sectional structure of a semiconductor structure obtained in step S50 in one embodiment;

[0043] Figure 6 is a schematic diagram of a cross-sectional structure of a semiconductor structure obtained in step S60 in one embodiment;

[0044] Figure 7 is a schematic cross-sectional structural diagram of a semiconductor structure obtained after forming a second dielectric layer in another embodiment;

[0045] Figure 8 is a schematic diagram of a cross-sectional structure of a semiconductor structure obtained after forming a protective layer in another embodiment;

[0046] Fig. 9 A morphology comparison diagram of two semiconductor structures in one embodiment;

[0047] Fig.10 is an X-ray diffraction pattern of a semiconductor structure in one embodiment;

[0048] Fig.11 is an X-ray diffraction pattern of another semiconductor structure in one embodiment;

[0049] Fig.12 This is a graph showing the on-state voltage drop test results of two semiconductor structures at 100uA in one embodiment;

[0050] Fig.13 A graph showing the on-state voltage drop test results of two semiconductor structures at 15A in one embodiment;

[0051] Fig.14 A diagram showing breakdown voltage test results of two semiconductor structures in one embodiment;

[0052] Fig.15 Graph showing leakage current test results of two semiconductor structures in one embodiment.

[0053] Description of reference numerals:

[0054] 110 - interlayer dielectric layer, 120 - substrate, 130 - part of the interlayer dielectric layer in the initial interconnection hole, 140 - implanted ions, 150 - thermal oxide layer, 160 - metal layer, 170 - protective layer, 111 - first material layer, 112 - second material layer, 113 - third material layer. DETAILED DESCRIPTION

[0055] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0057] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0058] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0059] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0060] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0061] See also Figure 1 The present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0062] S10, providing a substrate, wherein an interlayer dielectric layer is formed on a surface of the substrate;

[0063] S20, etching the interlayer dielectric layer to form an initial interconnection hole in the interlayer dielectric layer, with a portion of the interlayer dielectric layer remaining at the bottom of the initial interconnection hole;

[0064] S30, performing thermal oxidation treatment on the obtained structure, so that the portion of the interlayer dielectric layer at the bottom of the initial interconnection hole forms a thermal oxidation layer;

[0065] S40, performing ion implantation into the substrate through the thermal oxidation layer to form a damaged layer on the surface of the substrate;

[0066] S50, etching the thermal oxide layer to expose the damaged layer on the surface of the substrate;

[0067] S60, forming a metal layer and a metal compound layer on the damaged layer on the surface of the substrate, wherein the metal compound layer is located on the surface of the substrate, and the metal layer is located on the surface of the metal compound layer away from the substrate.

[0068] In step S10, for example Figure 2 As shown, the substrate 120 generally refers to a substrate composed of a semiconductor material. In special cases, it can also be a non-semiconductor material according to actual use requirements. The material constituting the substrate includes but is not limited to silicon material. The interlayer dielectric layer 110 is generally composed of a non-conductive oxide material. In special cases, it can also be other materials that meet the use requirements. The specific composition of the substrate and the interlayer dielectric layer is not limited here. A substrate 120 is provided, and an interlayer dielectric layer 110 is formed on the surface of the substrate 120, that is, the interlayer dielectric layer 110 covers the surface of the substrate 120.

[0069] In step S20, for example Figure 3 As shown in the figure, the interlayer dielectric layer 120 is etched to produce an initial interconnection hole, and an interlayer dielectric layer 130 remains at the bottom of the initial interconnection hole, that is, the partial interlayer dielectric layer. The means used to etch the interlayer dielectric layer may be wet etching, dry etching or other etching means that meet the actual use requirements, or a combination of multiple etching means may be used, such as first using dry etching to a certain depth, and then using wet etching. The position and shape of the initial interconnection hole are adjusted according to actual needs. A preset thickness requirement may be established for the interlayer dielectric layer 130. The preset thickness requirement may refer to a pre-set thickness requirement, which may include making the thickness meet a certain thickness range, or making the thickness greater than or less than a certain threshold. The specific thickness requirement is set according to actual needs. For example, according to production needs, the preset thickness requirement may be set to a thickness of approximately The error tolerance range can also be set. For example, the preset thickness requirement can be set to a thickness that satisfies The preset thickness requirement is generally set in consideration of the requirements of the subsequent ion implantation process. The interlayer dielectric layer is etched to form an initial interconnection hole in the interlayer dielectric layer, and an interlayer dielectric layer 130 is left at the bottom of the initial interconnection hole. The interlayer dielectric layer 130 meets the preset thickness requirement.

[0070] In step S30, for example Figure 4 As shown, the obtained structure is subjected to thermal oxidation treatment, so that all or part of the interlayer dielectric layer 130 at the bottom of the initial interconnection hole is converted into a thermal oxide layer 150. The figure shows the situation when the remaining interlayer dielectric layer 130 at the bottom of the initial interconnection hole is completely converted into a thermal oxide layer 150. Thus, a thermal oxide layer is formed at the bottom of the initial interconnection hole.

[0071] In step S40, for example Figure 4 As shown, ions 140 are injected into the resulting structure at a certain angle, and the ions 140 will pass through the thermal oxide layer 150 to reach the surface of the substrate 120, and then form a damaged layer on the surface of the substrate 120. The ions 140 used for ion injection can be inert gas ions, for example, one or more of helium ions, neon ions, argon ions, krypton ions, and radon ions. Parameters such as the type, energy, injection rate, and injection time of the ions 140 are set according to actual use needs. Ions are injected into the substrate through the thermal oxide layer to form a damaged layer on the surface of the substrate. The injected ions 140 can pass through the thermal oxide layer to reach the substrate and form a damaged layer on the surface of the substrate.

[0072] In step S50, for example Figure 5 As shown, the thermal oxide layer in the initial interconnect hole is etched to expose the damaged layer on the surface of the substrate. The initial interconnect hole that exposes the surface of the substrate can be called an interconnect hole. The means used to etch the initial interconnect hole is not limited, for example, it can be wet etching, which is based on the actual use needs. During the etching process, damage to the substrate should generally be avoided, and the thermal oxide layer 150 and the interlayer dielectric layer that may not be converted into a thermal oxide layer are removed at the same time.

[0073] In step S60, a metal layer and a metal compound layer are formed on the damaged layer on the surface of the substrate. The metal contained in the metal layer and the metal compound layer are generally the same metal. A sputtering process can be used to form a metal layer on the damaged layer on the surface of the substrate. After reaction, the part of the metal layer in contact with the substrate 120 can become a metal compound layer. The metal compound layer is located on the surface of the substrate 120, and the metal layer is located on the surface of the metal compound layer away from the substrate 120. The metal compound can be a metal compound formed by the metal and the substrate. For example Figure 6 As shown, a metal layer 160 is formed in the interconnection hole. Since the metal layer and the metal compound layer generally have no obvious boundary, only the metal layer 160 is drawn in the figure. The metal in the metal layer 160 includes metal aluminum.

[0074] In this embodiment, compared with the prior art, an interlayer dielectric layer is first retained on the substrate surface of the interconnection hole (during ion implantation, the interlayer dielectric layer is equivalent to a substrate protective layer), and then a thermal oxidation process is added to convert the interlayer dielectric layer into a thermal oxidation layer. Then, an ion implantation process is added to form a damaged layer on the substrate surface. The damaged layer lays a foundation for the nucleation of the metal layer and the formation of a new metal lattice without macroscopic color difference, thereby ultimately improving the macroscopic and microscopic morphologies of the metal layer in the resulting semiconductor structure.

[0075] In one embodiment, forming a metal layer and a metal compound layer on the damaged layer on the surface of the substrate comprises:

[0076] forming a metal material layer on the damaged layer on the surface of the substrate;

[0077] removing the metal material layer located in the interlayer dielectric layer away from the surface of the substrate;

[0078] The obtained structure is alloyed to form the metal layer 160 and the metal compound layer.

[0079] Specifically, it is necessary to form a metal material layer on the damaged layer on the surface of the substrate. However, due to the limitation of the preparation process, a metal material layer may also be formed on the surface of the interlayer dielectric layer away from the substrate during this process. Therefore, it is necessary to remove the metal material layer located on the surface of the interlayer dielectric layer away from the substrate. The metal material layer is located on the surface of the substrate 120 and in the holes in the interlayer dielectric layer 110. The resulting structure is then alloyed, during which part of the metal material layer undergoes an alloying reaction and is transformed into a metal compound layer. The metal material layer that has not been transformed into a metal compound layer can be referred to as a metal layer. The alloying treatment has a certain repair effect on the damaged layer caused by ion implantation.

[0080] In this embodiment, by adding processing to the metal material layer of the interlayer dielectric layer away from the substrate surface, it is closer to the preparation process of the semiconductor structure, which is conducive to preparing the semiconductor structure that meets actual use requirements.

[0081] In one embodiment, Figure 7 As shown, the step of forming the interlayer dielectric layer on the surface of the substrate in step S10 includes:

[0082] An oxide layer 111 is formed on the surface of the substrate 120, and an opening is formed in the oxide layer 111 to expose the substrate;

[0083] forming a first dielectric layer 112 in the opening and on a surface of the oxide layer away from the substrate;

[0084] A second dielectric layer 113 is formed on a surface of the first dielectric layer away from the substrate.

[0085] In this example, by making the interlayer dielectric layer include an oxide layer, a first dielectric layer, and a second dielectric layer, it is beneficial to better protect the substrate during the etching process and to adapt to the actual semiconductor device manufacturing process.

[0086] In one embodiment, the step S30 of performing thermal oxidation treatment on the obtained structure so as to form a thermal oxidation layer on the portion of the interlayer dielectric layer at the bottom of the initial interconnection hole comprises:

[0087] The obtained structure is subjected to rapid thermal oxidation treatment or low temperature thermal treatment, so that the portion of the interlayer dielectric layer at the bottom of the initial interconnection hole forms a thermal oxidation layer 150 .

[0088] Specifically, the obtained structure is subjected to rapid thermal oxidation treatment to rapidly thermally oxidize the part of the interlayer dielectric layer 130 to form a thermal oxide layer 150. During the rapid thermal oxidation treatment, the conditions should be controlled to avoid oxidation of the substrate 120 as much as possible. Alternatively, the obtained structure is subjected to low-temperature heat treatment to convert the part of the interlayer dielectric layer 130 into the thermal oxide layer 150. It should be noted that the above-mentioned processing of the remaining interlayer dielectric layer 130 into the thermal oxide layer 150 includes: processing part or all of the remaining interlayer dielectric layer 130 into the thermal oxide layer 150.

[0089] In this embodiment, by using rapid thermal oxidation treatment or low-temperature thermal oxidation treatment in the thermal oxidation treatment, the beneficial effect of facilitating the formation of a thermal oxidation layer at the bottom of the initial interconnection hole can be achieved.

[0090] In one embodiment, the interlayer dielectric layer 110 in step S10 includes low-pressure tetraethyl orthosilicate and borophosphosilicate glass.

[0091] Specifically, the English name of low-pressure tetraethyl orthosilicate is tetra-ethyl-orthosilicate, and its English abbreviation is LPTEOS. The full English name of borophospho-silicate glass is boro-phospho-silicate glass, and its English abbreviation is BPSG. The interlayer dielectric layer 110 may include a low-pressure tetraethyl orthosilicate layer and a borophospho-silicate glass layer. The low-pressure tetraethyl orthosilicate layer may be located on the surface of the substrate 120, and the borophospho-silicate glass layer may be located on the surface of the low-pressure tetraethyl orthosilicate layer away from the substrate 120. The partial interlayer dielectric layer 130 may only include a low-pressure tetraethyl orthosilicate layer.

[0092] In this embodiment, by making the material constituting the interlayer dielectric layer include low-pressure tetraethyl orthosilicate and borophosphosilicate glass, it is beneficial to achieve the beneficial effects of effectively protecting the substrate and facilitating etching.

[0093] In one embodiment, the depth of the initial interconnect hole in step S20 is less than the thickness of the interlayer dielectric layer; in step S30, after the thermal oxide layer 150 is formed, the total thickness of the thermal oxide layer 150 and the interlayer dielectric layer retained at the bottom of the initial interconnect hole is Specifically, the total thickness of the thermal oxidation layer 150 and the interlayer dielectric layer retained at the bottom of the initial interconnection hole can be or etc.

[0094] Specifically, the thermal oxidation layer 150 originates from the part of the interlayer dielectric layer 130. When the part of the interlayer dielectric layer 130 is not completely transformed into the thermal oxidation layer 150, a layer of interlayer dielectric layer will be retained at the bottom of the initial interconnection hole. The thermal oxidation layer 150 and the retained interlayer dielectric layer together constitute a protective layer of the bottom substrate of the initial interconnection hole. Through etching and thermal oxidation treatment, the total thickness of the thermal oxidation layer 150 and the interlayer dielectric layer retained at the bottom of the initial interconnection hole is It is beneficial to protect the substrate and ensure the effect of ion implantation.

[0095] In this embodiment, by clarifying the thickness of the substrate protection layer composed of the thermal oxidation layer 150 and the retained interlayer dielectric layer, it is beneficial to protect the substrate while ensuring the effect of ion implantation.

[0096] In one embodiment, the substrate 120 in step S10 includes a silicon substrate, and the metal compound in step S60 includes metal silicide.

[0097] Specifically, the substrate 120 may be a silicon substrate or other substrates that can be used to prepare semiconductors. During the formation of the metal compound, the metal material layer will undergo an alloying reaction with the silicon substrate to generate metal silicide.

[0098] In this embodiment, by specifying that the substrate includes a silicon substrate and the metal compound includes a metal silicide, it is helpful to prepare a semiconductor structure that meets actual use requirements.

[0099] In one embodiment, for example Figure 7 As shown, the semiconductor structure includes a device region 102, a device region 106, and an annular region 104 located outside the device region, and the device region 102, the device region 106, and the annular region 104 are all formed with the interconnection holes; after the metal layer 160 and the metal compound layer are formed on the damaged layer on the surface of the substrate, as shown in Figure 7 As shown, it also includes:

[0100] Step S70 , forming a protective layer 170 on a surface of the interlayer dielectric layer away from the substrate 120 , wherein the protective layer 170 covers the annular region and has an opening formed therein, wherein the opening exposes the metal layer 160 in the interconnection hole in the device region.

[0101] The interconnection hole may refer to a hole obtained by removing the thermal oxidation layer and the interlayer dielectric layer at the bottom of the initial interconnection hole.

[0102] Specifically, according to the actual device preparation needs, the semiconductor structure may include a device area and an annular area located outside the device area. It should be noted that the device area and the annular area only represent different areas in the semiconductor structure, and are not used to limit the function of the actual device. For example, the substrate 120 may be a substrate obtained after being processed by furnace tubes, yellow light, injection and other processes. A PN junction may be formed in the device area, and a cut-off ring may be formed in the annular area. After etching, initial interconnection holes are formed in the device area and the annular area. A layer of interlayer dielectric layer remains at the bottom of the initial interconnection holes. After thermal oxidation, the interlayer dielectric layer becomes a thermal oxide layer 150 of about 200 angstroms. After argon ion implantation, an ion damage layer will be formed on the surface of the substrate 120. After the ion damage layer is formed, the thermal oxide layer 150 will be removed to expose the ion damage layer. Then, a metal layer 160 and a metal compound layer are formed on the damaged layer on the surface of the substrate, and a protective layer 170 is formed on the surface of the interlayer dielectric layer away from the substrate 120, wherein the protective layer 170 covers the annular region and has an opening formed therein, wherein the opening exposes the metal layer 160 in the interconnection hole in the device region. Figure 8 As shown, a metal layer 160 and a metal compound layer are formed in the three interconnect holes. Layer 170 represents a protective layer 170 (layer 170 may specifically be a polyimide layer) formed on the surface of the interlayer dielectric layer away from the substrate 120. There is an opening in the middle of layer 170, and the opening exposes layer 160 located in the middle device area.

[0103] In this embodiment, a protective layer is formed on the surface of the metal layer away from the substrate, which is beneficial to the protection of the metal layer. In addition, the semiconductor structure involving the device area and the annular area is beneficial to meeting actual use requirements, such as facilitating the preparation of a fast recovery diode.

[0104] In one embodiment, the step S70 of forming the protective layer 170 on the surface of the interlayer dielectric layer away from the substrate 120 includes:

[0105] forming a protective material layer on a surface of the interlayer dielectric layer away from the substrate 120;

[0106] The protective material layer is patterned to obtain the protective layer 170 having the opening.

[0107] Specifically, the steps of forming the protective layer 170 may include coating, exposure, development, and curing in semiconductor processes. In the process of forming the protective layer 170, the protective material layer is patterned, so that the opening is obtained in the development process. In the process of forming the protective layer 170, for example, in the curing process, a heat treatment process may be included, and the heat treatment process has a certain repair effect on the damaged layer caused by ion implantation.

[0108] In this embodiment, by clarifying the formation method of the opening, it is helpful to form a semiconductor structure that meets actual use requirements.

[0109] In one embodiment, the step S70 of forming the protective layer 170 on the surface of the interlayer dielectric layer away from the substrate 120 includes:

[0110] forming a polyimide layer on a surface of the interlayer dielectric layer away from the substrate 120;

[0111] Patterning the polyimide layer to form the opening in the polyimide layer;

[0112] The patterned polyimide layer is cured to obtain the protective layer 170 .

[0113] Specifically, the protective layer 170 may be a polyimide layer. The English name of polyimide is polyimide, abbreviated as PI. A polyimide layer is formed on the surface of the interlayer dielectric layer away from the substrate 120, and the polyimide layer is patterned to form the opening in the polyimide layer. The patterned polyimide layer is cured to obtain the protective layer 170. The position of the protective layer 170 in the obtained semiconductor structure may be as follows: Figure 8 As shown, an opening is formed in the middle of the polyimide layer.

[0114] In this embodiment, by using a polyimide layer as a protective layer and clarifying the method for forming the protective layer, it is beneficial to form a semiconductor structure that meets actual use requirements.

[0115] In one embodiment, the substrate 120 is a silicon substrate, the metal in the metal layer 160 is aluminum, and the interlayer dielectric layer includes a low-pressure tetraethyl ortho silicate layer located on the surface of the substrate 120 and a borophosphosilicate glass layer located away from the surface of the substrate 120. The thickness of the low-pressure tetraethyl ortho silicate layer meets the thickness range ( represents one thousand angstroms), for example or The thickness of the borophosphosilicate glass layer satisfies the thickness range For example it could be or The formation process of the interlayer dielectric layer includes reflow and photolithography, and the temperature range of the reflow includes 900-950°C, for example, 900°C, 920°C, 935°C, 940°C or 950°C, etc. According to actual needs, the temperature used for the reflow may not be in the range of 900-950°C, but generally not less than 700°C. The total thickness of the thermal oxide layer 150 and the interlayer dielectric layer retained at the bottom of the initial interconnection hole meets the thickness range For example it could be or The ions 140 used in the ion implantation are argon ions, and the energy of the argon ions meets the energy range of 20-50 KeV, for example, 20 KeV, 30 KeV, 40 KeV or 50 KeV, etc. The implantation dose of the ion implantation meets the range of 1×10 12 ~1×10 13 ion / cm 3 , for example, it can be 1×10 12 ion / cm 3 , 1×10 12.5 ion / cm 3 or 1×10 13 ion / cm 3 The implantation angle of the ion implantation satisfies the angle range of 0 to 7°, for example, 0°, 1°, 2°, 3°, 4°, 5°, 6° or 7°, etc. The implantation angle may also be greater than 7°, but generally does not exceed 45°.

[0116] In this embodiment, Fig. 9 As shown, Figure b and Figure d are microscopic morphology images of a semiconductor structure prepared by the method in this embodiment (hereinafter referred to as the semiconductor structure in this embodiment) at different magnification ratios. The semiconductor structure is a device including the semiconductor structure prepared by the present disclosure, including a silicon substrate and metal aluminum sputtered on the silicon substrate. Fig. 9 Figures a and c in the figure are microscopic morphology images of semiconductor structures (hereinafter referred to as existing semiconductor structures) prepared using the existing technology (using wet etching means to etch interconnected holes that expose the substrate and then directly perform metal sputtering) at different magnification ratios. The magnification ratios of Figures a and b are the same, and the magnification ratios of Figures c and d are the same. Fig. 9It can be seen that the microstructure of the semiconductor structure of this example is more uniform, and the morphology is better than that of the existing semiconductor structure. The microstructure of the existing semiconductor structure presents an irregular flocculent pattern, the grain size is different, and the macroscopic appearance is abnormal color difference. Therefore, the improvement of this embodiment relative to the prior art leads to the improvement of the macroscopic and microscopic morphology of aluminum in the semiconductor structure. The X-ray diffraction results of the existing semiconductor structure and the semiconductor structure of this example are as follows: Fig.10 He Ru Fig.11 As shown in the figure, it can be seen that the main crystal plane of aluminum in the existing semiconductor structure is (200)(400), and the main crystal plane of aluminum in the semiconductor structure of this example is (111)(222). The improvement of this embodiment relative to the prior art leads to a change in the main crystal plane of aluminum in the semiconductor structure. The electrical performance test of the semiconductor structure of this example and the existing semiconductor structure is shown in FIG. Fig.12 , Fig.13 , Fig.14 and Fig.15 As shown, Fig.12 It represents the on-state voltage drop at 100uA. Fig.13 It represents the on-state voltage drop at 15A. Fig.14 Indicates the breakdown voltage at 100uA, Fig.15 Indicates the leakage current at 770V. In the four figures, the two columns of data on the left of each figure represent the test results of the existing semiconductor structure, and the two columns of data on the right of each figure represent the test results of the semiconductor structure of this example. Fig.12 It shows that there is no difference in the on-state voltage drop at 100uA between the existing semiconductor structure and the semiconductor structure of this example. Fig.13 This indicates that there is no difference in the on-state voltage drop at 15A between the existing semiconductor structure and the semiconductor structure of this example. Fig.14 This indicates that there is no difference in breakdown voltage between the existing semiconductor structure and the semiconductor structure of this example at 100uA. Fig.15 This indicates that there is no difference in leakage current between the existing semiconductor structure and the semiconductor structure of this example at 770V. Fig.12 , Fig.13 , Fig.14 and Fig.15 The measurement results in the examples all show that the improvement in this embodiment relative to the prior art has no effect on the electrical properties of the device, and also demonstrates the repairing effect of the alloying treatment and the heat treatment during the formation of the protective layer on the damaged layer caused by ion implantation.

[0117] In one embodiment, before the alloying, the metal material layer is further subjected to photolithography and etching treatments.

[0118] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0119] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0120] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: Providing a substrate, wherein an interlayer dielectric layer is formed on a surface of the substrate; Etching the interlayer dielectric layer to form an initial interconnection hole in the interlayer dielectric layer, with a portion of the interlayer dielectric layer remaining at the bottom of the initial interconnection hole; Performing thermal oxidation treatment on the structure obtained in the above steps, so that the portion of the interlayer dielectric layer at the bottom of the initial interconnection hole forms a thermal oxidation layer; Performing ion implantation into the substrate through the thermal oxidation layer to form a damaged layer on the surface of the substrate; Etching the thermal oxide layer to expose the damaged layer on the surface of the substrate; A metal layer and a metal compound layer are formed on the damaged layer on the surface of the substrate, wherein the metal compound layer is located on the surface of the substrate, and the metal layer is located on the surface of the metal compound layer away from the substrate.

2. The method according to claim 1, characterized in that: The step of performing thermal oxidation on the structure obtained in the above step so that the portion of the interlayer dielectric layer at the bottom of the initial interconnection hole forms a thermal oxidation layer comprises: The structure obtained in the above steps is subjected to rapid thermal oxidation treatment or low temperature thermal treatment, so that the portion of the interlayer dielectric layer at the bottom of the initial interconnection hole forms a thermal oxidation layer.

3. The method according to claim 1, characterized in that After the thermal oxide layer is formed, the total thickness of the thermal oxide layer and the interlayer dielectric layer retained at the bottom of the initial interconnection hole is 4. The method according to claim 1, characterized in that The step of forming the interlayer dielectric layer on the surface of the substrate comprises: forming an oxide layer on the surface of the substrate, wherein an opening exposing the substrate is formed in the oxide layer; forming a first dielectric layer in the opening and on a surface of the oxide layer away from the substrate; A second dielectric layer is formed on a surface of the first dielectric layer away from the substrate.

5. The method according to claim 1, characterized in that The substrate includes a silicon substrate, and the metal compound includes a metal silicide.

6. The method according to claim 1, characterized in that The interlayer dielectric layer comprises low-pressure tetraethyl orthosilicate and borophosphosilicate glass.

7. The method according to claim 1, characterized in that The step of forming a metal layer and a metal compound layer on the damaged layer on the surface of the substrate comprises: forming a metal material layer on the damaged layer on the surface of the substrate; removing the metal material layer located in the interlayer dielectric layer away from the surface of the substrate; The obtained structure is alloyed to form the metal layer and the metal compound layer.

8. The method according to claim 1, characterized in that: The ions used in the ion implantation are argon ions, the energy range of the argon ions is 20 KeV to 50 KeV, and the implantation dose range of the argon ions is 1×10 12 ion / cm 3 ~1×10 13 ion / cm 3 .

9. The method according to any one of claims 1 to 8, characterized in that The substrate includes a device region and an annular region located outside the device region, and interconnection holes are formed in the device region and the annular region; after forming a metal layer and a metal compound layer on the damaged layer on the surface of the substrate, the method further includes: A protective layer is formed on a surface of the interlayer dielectric layer away from the substrate, the protective layer covers the annular region, an opening is formed in the protective layer, and the opening exposes the metal layer in the interconnection hole in the device region.

10. The method according to claim 9, characterized in that The forming of a protective layer on a surface of the interlayer dielectric layer away from the substrate comprises: forming a protective material layer on a surface of the interlayer dielectric layer away from the substrate; The protective material layer is patterned to obtain the protective layer having the opening.

11. The method according to claim 9, characterized in that The forming of a protective layer on a surface of the interlayer dielectric layer away from the substrate comprises: forming a polyimide layer on a surface of the interlayer dielectric layer away from the substrate; Patterning the polyimide layer to form the opening in the polyimide layer; The patterned polyimide layer is cured to obtain the protective layer.

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