Integrated circuit lead frame and semiconductor device thereof

Abstract

An integrated circuit lead frame and a semiconductor device thereof are disclosed. The integrated circuit lead frame includes a die pad and a plurality of leads. The die pad is configured to receive a die. The plurality of leads is configured to be wire bonded to the die. The plurality of leads includes a pair of a first lead and a second lead. The first lead includes a first body and a first extension connected to the first body. The second lead includes a second body and a second extension connected to the second body. The first extension and the second extension extend toward each other.

Description

TECHNICAL FIELD

[0001] The present invention relates to a lead frame, and more particularly to an integrated circuit lead frame with optimized impedance matching of leads and a semiconductor device thereof. BACKGROUND

[0002] In order to comply with the requirement of high speed transmission, chips usually adopt high cost packaging technologies such as ball grid array (BGA) and flip chip to shorten the distance between the die and the substrate and to avoid the signal attenuation caused by wire bonding without impedance control. Although the cost of the traditional packaging technology of wire bonding is lower than the aforementioned packaging technologies, it is difficult to provide high speed signals due to the difficulty in controlling the electrical characteristics of the wire bonding. SUMMARY

[0003] In view of the above, the present invention provides an integrated circuit lead frame and a semiconductor device thereof. By designing the leads and using the packaging technology of wire bonding, the impedance matching of the leads in the package is optimized, the manufacturing cost is greatly reduced, and the number of leads in a single chip is greatly increased to achieve high density packaging (e.g., packaging with multiple rows of leads), thereby improving performance and further reducing manufacturing cost.

[0004] According to some embodiments, an integrated circuit lead frame includes a die seat and a plurality of leads. The die seat is configured to receive a die. The plurality of leads is configured to be wire bonded to the die. The leads include a pair of a first lead and a second lead. The first lead includes a first body and a first extension connected to the first body. The second lead includes a second body and a second extension connected to the second body. The first extension and the second extension extend in a direction approaching each other.

[0005] According to some embodiments, a semiconductor device includes a die, an integrated circuit lead frame, and a package. The integrated circuit lead frame includes a die seat and a plurality of leads. The die seat is configured to receive a die. The plurality of leads is configured to be wire bonded to the die. The leads include a pair of a first lead and a second lead. The first lead includes a first body and a first extension connected to the first body. The second lead includes a second body and a second extension connected to the second body. The first extension and the second extension extend in a direction approaching each other. The package encapsulates the die and part of the integrated circuit lead frame.

[0006] In summary, according to the embodiments of the present invention, by designing the shape of the leads (e.g., the wire bonding points of the pair of leads extend in a direction approaching each other) and using the packaging technology of wire bonding, the distance between the leads wire bonded by the pair of leads is shortened to achieve good impedance matching and to provide high speed signal transmission and reduce manufacturing cost. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a perspective view schematic of a semiconductor device of some embodiments of the present application.

[0008] Figure 2 is a perspective view schematic of a semiconductor device of some embodiments of the present application.

[0009] Figure 3 is a top view schematic of Figure 2

[0010] Figure 4 is a partial enlarged view schematic of Figure 3

[0011] Figure 5 is a partial enlarged view schematic of Figure 4

[0012] Figure 6 is a schematic of a first comparative example.

[0013] Figure 7 is a schematic of signal carrying insertion loss and reflection loss of an integrated circuit leadframe of some embodiments of the present application and a first comparative example.

[0014] Figure 8 is a partial enlarged top view schematic of an integrated circuit leadframe of some embodiments of the present application.

[0015] Figure 9 is a partial enlarged top view schematic of an integrated circuit leadframe of some embodiments of the present application.

[0016] Figure 10 is a schematic of a first pin and a second pin of a same pair of some embodiments of the present application.

[0017] Figure 11 is a schematic of a first pin and a second pin of a same pair of some embodiments of the present application.

[0018] Figure 12 is a partial enlarged top view schematic of an integrated circuit leadframe of some embodiments of the present application.

[0019] Figure 13 is a partial enlarged top view schematic of an integrated circuit leadframe of some embodiments of the present application.

[0020] Figure 14 is a schematic of a second comparative example.

[0021] Figure 15 is a schematic of a third comparative example.

[0022] Figure 16 is a partial enlarged top view schematic of an integrated circuit leadframe of some embodiments of the present application.​​​

[0023] Figure 17 is a partial enlarged plan view of an integrated circuit lead frame according to some embodiments of the present application.

[0024] Figure 18 is a bottom view of a semiconductor device according to some embodiments of the present application.

[0025] Figure 19 is a side cross-sectional view of the same pair of first and second pins according to some embodiments of the present application.

[0026] Figure 20 is a plan view of an integrated circuit lead frame according to some embodiments of the present application.

[0027] Figure 21 is a side cross-sectional view of a semiconductor device according to some embodiments of the present application.

[0028] Figure 22 is a schematic diagram of an impedance system according to some embodiments of the present application. DETAILED DESCRIPTION

[0029] Referring to Figure 1 , Figure 1 is a perspective view of a semiconductor device 10 according to some embodiments of the present application. The semiconductor device 10 includes a die 11, an integrated circuit lead frame 13, and a package 15. The die 11 is a die cut from a wafer. The integrated circuit lead frame 13 is a metal structure inside the semiconductor device 10 for transmitting signals from the die 11 to outside of the semiconductor device 10, so that a circuit outside of the semiconductor device 10 (e.g., a circuit board outside of the semiconductor device 10) can receive the signals from the die 11 via the integrated circuit lead frame 13. The package 15 covers the die 11 and part of the integrated circuit lead frame 13. The package 15 provides impact and scratch protection for the die 11. For convenience of explanation, the semiconductor device 10 is shown as including one die 11, but the present application is not limited thereto. The semiconductor device 10 can include multiple dies 11.

[0030] Referring to Figure 2 and Figure 3 . Figure 2 is a perspective view of a semiconductor device 10 according to some embodiments of the present application. Figure 3 is Figure 2A top view schematic diagram. The integrated circuit lead frame 13 of the semiconductor device 10 includes a die holder 33 and a plurality of pins 17. The die holder 33 is used to mount the die 11. For ease of explanation, only one die 11 is mounted on the die holder 33 as an example, but the present invention is not limited thereto. The die holder 33 can mount multiple dies 11, that is, multiple dies 11 can be mounted on the die holder 33 simultaneously. In some embodiments, the die holder 33 is used to attach and fix the die 11 to the die holder 33 with adhesive (e.g., silver paste) or die attach film, i.e., die bonding. These pins 17 are used for wire bonding to the die 11. That is, these pins 17 are connected to the pads 19 of the die 11 via wires 21. In some embodiments, the wires 21 are made of metals such as copper or gold. In some embodiments, if the material of the conductor 21 is copper, the diameter of the conductor 21 may be 0.7 mil to 1 mil; if the material of the conductor 21 is gold, the diameter of the conductor 21 may be 0.7 mil to 2 mil, but the present invention is not limited thereto.

[0031] Merge reference Figure 4 , Figure 4 yes Figure 3 A partially enlarged schematic diagram. These pins 17 include a pair of first pins 171 and second pins 173. The first pin 171 includes a first body 1711 and a first extension 1713 connected to the first body 1711. The second pin 173 includes a second body 1731 and a second extension 1733 connected to the second body 1731. The first extension 1713 and the second extension 1733 extend toward each other. In other words, the first extension 1713 and the second extension 1733 extend toward each other. Specifically, see attached reference. Figure 5 , Figure 5 yes Figure 4 The enlarged schematic diagram shows that the first extension 1713 has a connecting end 1715 connected to the first body 1711 and a free end 1716 relative to the connecting end 1715. The second extension 1733 has a connecting end 1735 connected to the second body 1731 and a free end 1736 relative to the connecting end 1735. The distance between the free ends 1716 and 1736 of the first extension 1713 and the second extension 1733 is shorter than the distance between the connecting ends 1715 and 1735 of the first extension 1713 and the second extension 1733.

[0032] Since the first extension 1713 and the second extension 1733 extend toward each other, when the first pin 171 and the second pin 173 are connected to the contact pad 19 of the die 11 through the first extension 1713 and the second extension 1733 via the wire 21, the pitch SP between the wires 21 (e.g., the short wire 21A and the long wire 21B described below) can be reduced (e.g., the wires 21 are closer to each other, or the pitch SP meets the specification of the wire bonding package), thereby optimizing or adjusting the impedance matching between the wires 21 to improve the signal quality transmitted by the wires 21, and high-speed signals can be transmitted. For example, the pitch SP is adjusted to adjust the equivalent inductance value and capacitance value of the wires 21, and the impedance value is calculated according to Equation 1 to perform impedance matching on the wires 21 to improve the performance of insertion loss and reflection loss. In Equation 1, Z is the impedance value of the wire 21, L is the unit inductance value of the wire 21, and C is the unit capacitance value of the wire 21. In some embodiments, the high-speed signal is a pair of differential signals. The high-speed signal is, for example but not limited to, a signal with a Nyquist frequency of 10 GHz to realize a USB4.0 or PCIE4.0 application circuit.

[0033]

[0034] The pitch SP is the distance between the shorter wire (hereinafter referred to as the short wire 21A) of the two wires 21 and the longer wire (hereinafter referred to as the long wire 21B) of the two wires 21 at the contact point 23 connected by the pin 17. For example, as shown in Figure 4 , the wire 21 connected by the second pin 173 is shorter than the wire 21 connected by the first pin 171, so the second pin 173 is connected to the short wire 21A, and the first pin 171 is connected to the long wire 21B. The pitch SP between the short wire 21A and the long wire 21B is the shortest distance from the contact point 23A connected to the second pin 173 of the short wire 21A to the long wire 21B.

[0035] Referring to Figure 6 , Figure 6 is a schematic diagram of a first comparative example. In the first comparative example, the first pin 171 and the second pin 173 do not have extensions that approach each other. Referring to Figure 4 and Figure 6 , it can be seen that the pitch SP shown in Figure 4 of the embodiment of the present application is much smaller than the pitch SP shown in Figure 6 of the first comparative example, so that the wires 21 can be closer to each other.

[0036] Referring to Figure 7 , Figure 7Fig. 6 is a schematic diagram showing the signal carrying insertion loss and reflection loss of the integrated circuit lead frame 13 of some embodiments of the present application and a first comparative example. As can be seen, the insertion loss and reflection loss of the embodiments of the present application are better than those of the first comparative example, resulting in a significant increase in bandwidth performance.

[0037] In some embodiments, as shown in Figs. 1A and 1B, the first body 1711 and the second body 1731 are circular, and the first extension 1713 and the second extension 1733 are rectangular, but the present application is not limited thereto and can be other shapes, such as those shown in Figs. 2A and 2B. Figure 4 Figure 5 In some embodiments, as shown in Figs. 1A and 1B, the first body 1711 and the second body 1731 are circular, and the first extension 1713 and the second extension 1733 are rectangular, but the present application is not limited thereto and can be other shapes, such as those shown in Figs. 2A and 2B. Figure 8 Figure 9 In some embodiments, as shown in Figs. 1A and 1B, the first body 1711 and the second body 1731 are circular, and the first extension 1713 and the second extension 1733 are rectangular, but the present application is not limited thereto and can be other shapes, such as those shown in Figs. 2A and 2B. Figure 8 Figure 9 Figs. 3A and 3B are partial enlarged top schematic diagrams of the integrated circuit lead frame 13 of some embodiments of the present application. Different shapes can result in different capacitive loads generated by the pins 17. For example, if the first pin 171 and the second pin 173 have relatively large areas due to their shapes, then the first pin 171 and the second pin 173 can generate (or provide) larger capacitive loads.

[0038] In some embodiments, as shown in Figs. 1A and 1B, the first body 1711 and the second body 1731 are circular, and the first extension 1713 and the second extension 1733 are rectangular, but the present application is not limited thereto and can be other shapes, such as those shown in Figs. 2A and 2B. Figure 4 In some embodiments, as shown in Figs. 1A and 1B, the first body 1711 and the second body 1731 are circular, and the first extension 1713 and the second extension 1733 are rectangular, but the present application is not limited thereto and can be other shapes, such as those shown in Figs. 2A and 2B.

[0039] In some embodiments, the distance between the first extension 1713 and the second extension 1733 can be configured to be no less than the minimum setting value of the process. For example, the distance between the first extension 1713 and the second extension 1733 can be no less than 0.1 mm.

[0040] In some embodiments, as shown in Figs. 1A and 1B, the first body 1711 and the second body 1731 are circular, and the first extension 1713 and the second extension 1733 are rectangular, but the present application is not limited thereto and can be other shapes, such as those shown in Figs. 2A and 2B. Figure 4 ​​​As shown, the extension lengths ED1, ED3 of the first and second extensions 1713, 1733, the pin spacing PS between the first and second pins 171, 173, and the body diameters BR1, BR3 of the first and second extensions 1713, 1733 are correlated. Specifically, the extension lengths ED1, ED3, the pin spacing PS, and the body diameters BR1, BR3 are positively correlated with each other. For example, when the pin spacing PS is larger, the body diameters BR1, BR3 and the extension lengths ED1, ED3 are relatively larger, and vice versa. The pin spacing PS is the distance between the center point of the first body 1711 and the center point of the second body 1731. High-density packaging (e.g., packaging of the multiple rows of pins 17 of the semiconductor device 10) is achieved by different proportional values of the pin spacing PS, the extension lengths ED1, ED3, and the body diameters BR1, BR3.

[0041] Referring to Figure 10 and Figure 11 . Figure 10 is a schematic view of the first and second pins 171, 173 of the same pair of the semiconductor device 10 according to some embodiments of the present application. Figure 11 is a schematic view of the first and second pins 171, 173 of the same pair of the semiconductor device 10 according to some embodiments of the present application. In some embodiments, the body diameters BR1, BR3 of the first and second bodies 1711, 1731 are respectively 0.4 to 2 times the extension lengths ED1, ED3 of the first and second extensions 1713, 1733. For example, as shown in Figure 10 when the pin spacing PS is 1 mm, the body diameters BR1, BR3 are 0.225 mm, and the extension lengths ED1, ED3 are about 2 times the body diameters BR1, BR3. As another example, as shown in Figure 11 when the pin spacing PS is 0.8 mm, the body diameters BR1, BR3 are 0.425 mm, and the extension lengths ED1, ED3 are about 0.46 times the body diameters BR1, BR3. Thus, high-density packaging of the chip pins 17 is achieved.

[0042] In some embodiments, the extension lengths ED1, ED3 can be set according to the spacing SP between the wires 21 connected by the first and second extensions 1713, 1733, respectively. For example, the extension lengths ED1, ED3 are configured according to the wire diameter of each wire 21 such that the spacing SP is not greater than 5 times. Thus, by setting the extension lengths ED1, ED3 of the first and second extensions 1713, 1733, the spacing SP complies with the specification of wire bonding packaging.

[0043] In some embodiments, as shown in Figure 10As shown, when the pin spacing PS between the first pin 171 and the second pin 173 is large, the extension lengths ED1, ED3 of the first pin 171 and the second pin 173 (i.e. the distances from the connecting ends 1715, 1735 to the free ends 1716, 1736) can be large, so that the first extension 1713 and the second extension 1733 are partially staggered, i.e. the free end 1716 of the first extension 1713 and the free end 1736 of the second extension 1733 are staggered. However, the present application is not limited thereto, and as shown in Figure 11 As shown, when the pin spacing PS between the first pin 171 and the second pin 173 is small, the extension lengths ED1, ED3 of the first pin 171 and the second pin 173 (i.e. the distances from the connecting ends 1715, 1735 to the free ends 1716, 1736) can be small, so that the first extension 1713 and the second extension 1733 can not be staggered, i.e. the free end 1716 of the first extension 1713 and the free end 1736 of the second extension 1733 can not be staggered.

[0044] Referring to Figure 12 and Figure 13 . Figure 12 is a partial enlarged top view of the integrated circuit lead frame 13 of some embodiments of the present application. Figure 13 is a partial enlarged top view of the integrated circuit lead frame 13 of some embodiments of the present application. The free ends 1716, 1736 of the first extension 1713 and the second extension 1733 (or the staggered portions of the free ends 1716, 1736 of the first extension 1713 and the second extension 1733) are located on a stagger axis SA, which points to the die 11 of the die seat 33. It can be seen that the leads 21 are relatively close to each other, i.e. the spacing SP between the two leads 21 is reduced, and the leads 21 can maintain a relatively consistent spacing SP from the die 11 to the first pin 171 and the second pin 173. Referring to Figure 14 and Figure 15 . Figure 14 is a schematic view of a second comparative example. Figure 15 is a schematic view of a third comparative example. In the second comparative example and the third comparative example, the stagger axis SA on which the free ends 1716, 1736 of the first extension 1713 and the second extension 1733 (or the staggered portions of the free ends 1716, 1736 of the first extension 1713 and the second extension 1733) are located does not point to the die 11 of the die seat 33. Referring to Figure 12 to Figure 15 It can be seen that the spacing SP shown in Figure 12 and Figure 13 of the embodiments of the present application is much smaller than the spacing SP shown in Figure 14 and Figure 15 of the second comparative example and the third comparative example, and Figure 12 and Figure 13The conductive lines 21 shown transmitting differential signals from the die 11 to the first and second pins 171, 173 are compared with Figure 14 and Figure 15 The second and third comparative examples can maintain a consistent pitch SP to maintain the quality of the differential signals.

[0045] Referring to Figure 16 , Figure 16 is a partial enlarged plan view of an integrated circuit lead frame 13 according to some embodiments of the present application. The pins 17 are located around the die pad 33. The edge region 35 on one side of the die pad 33 is divided into a first region 351 and a second region 353 by an axis DA passing through the die pad 33. The first and second extension directions D3, D4 of the first and second extension portions 1713, 1733 in the first region 351 are different from the first and second extension directions D4, D3 of the first and second extension portions 1713, 1733 in the second region 353.

[0046] In some embodiments, the position of the axis DA can be configured according to the position of the die 11 in the die pad 33 and the wire bonding direction thereof, so as to optimize the size of the pitch SP between the two conductive lines 21. For example, if a die 11 is disposed in the center of the die pad 33, the axis DA can be the central axis passing through the die pad 33; if a die 11 is disposed on the left (or right) side of the die pad 33, the axis DA can be the central axis of the die 11; if multiple dies 11 are disposed in the die pad 33, the axis DA can be the intermediate axis between the dies 11.

[0047] In some embodiments, the first and second extension directions D3, D4 are axisymmetric with respect to the axis DA. For example, as shown in Figure 16 , the first and second extension directions D3 of the first and second extension portions 1713, 1733 in the first region 351 extend towards the upper left and lower right respectively, and the second and first extension directions D4 of the first and second extension portions 1713, 1733 in the second region 353 extend towards the upper right and lower left respectively.

[0048] In some embodiments, the first and second pins 171, 173 transmit a pair of differential signals. Since differential signals generally need to be transmitted by two conductive lines 21 that are equal in length and width and closely adjacent, and different conductive lines 21 (such as the first and second extension portions 1713, 1733) are required to transmit different signals, the first and second extension portions 1713, 1733 are configured to be different in length and width. Figure 4The length of the short leads 21 A, the length of the long leads 21 B, and the spacing SP between the leads 21 have a substantial impact on the quality of the differential signals. Therefore, the length of the leads 21 and the spacing SP between the leads 21 for transmitting the differential signals need to be strictly regulated. By transmitting a pair of differential signals with the first pin 171 and the second pin 173 extending toward each other, the size of the spacing SP (e.g., the size of the spacing SP is reduced) can be controlled to comply with the wire bonding package regulations, and the characteristic impedance of the leads 21 can be controlled to maintain the quality of the differential signals, so that high-speed differential signals can be transmitted. The pair of differential signals can be two high-speed or low-speed signals with the same amplitude and opposite phase.

[0049] In some embodiments, the first pin 171 and the second pin 173 are the same shape, but the present application is not limited thereto, and the first pin 171 and the second pin 173 can be different shapes. When the first pin 171 and the second pin 173 are the same shape, the attenuation of the signals transmitted by the leads 21 connected to the first pin 171 and the second pin 173 can be consistent (e.g., the attenuation of a pair of high-speed differential signals at high frequencies is consistent), and the quality or amplitude of the signals (e.g., a pair of high-speed differential signals) between the leads 21 of the first pin 171 and the second pin 173 can be the same or uniform.

[0050] In some embodiments, the first pin 171 or the second pin 173 transmits a power signal. In some embodiments, the first pin 171 and the second pin 173 transmit a pair of power signals. The pair of power signals can be a positive power signal and a negative power signal. In some embodiments, the first pin 171 or the second pin 173 of one pair of the pair of pins 17 (i.e., the pair of the first pin 171 and the second pin 173) can transmit a pair of differential signals or a pair of power signals with the first pin 171 or the second pin 173 of another pair. In some embodiments, the first pin 171 and the second pin 173 can transmit non-paired signals (e.g., single-ended signals). For example, the first pin 171 and the second pin 173 can transmit non-differential clock signals, etc.

[0051] In some embodiments, as Figure 2 , Figure 3 and Figure 16As shown, the pins 17 also include a third pin 175. The third pin 175 can be the same shape as the first body 1711 or the second body 1731 to be consistent with the signal attenuation caused by the first pin 171 and the second pin 173, but the present application is not limited thereto, and the third pin 175 can be a different shape from the first body 1711 or the second body 1731. In some embodiments, the third pin 175 can transmit a non-paired signal (e.g., a single-ended signal). For example, the third pin 175 can transmit a non-differential clock signal, etc. In some embodiments, the first pin 171 or the second pin 173 can transmit a pair of power signals or a pair of differential signals with the third pin 175.

[0052] In some embodiments, the paired first pin 171 and the paired second pin 173 can be configured adjacently. In some embodiments, as shown in FIG. 1A, the paired first pin 171 and the paired second pin 173 can be configured adjacently. Figure 2 Figure 3 and Figure 16 As shown, at least one third pin 175 can be configured between two adjacent paired pins 17 (i.e., two adjacent paired first pins 171 and second pins 173) to enhance the isolation between different pairs of differential signals transmitted by the conductive wires 21 of different pairs of first pins 171 and second pins 173, so as to avoid mutual interference between the signals. In this embodiment, only one third pin 175 is configured between two adjacent paired pins 17, but the present application is not limited thereto, and a plurality of third pins 175 can be configured.

[0053] Referring to Figure 17 Figure 17 FIG. 1A is a partial enlarged top view of an integrated circuit lead frame 13 according to some embodiments of the present application. In some embodiments, the pins 17 can be wire-bonded to the pads 19 of the die 11 or the pads 29 of the die seat 33 via at least one conductive wire 21. That is, the contact points 23 of the pins 17 can be soldered to one end of the at least one conductive wire 21, and the other end of the conductive wire 21 can be soldered to the pads 19 of the die 11 or the pads 29 of the die seat 33. Specifically, one pin 17 (e.g., the first pin 171, the second pin 173, or the third pin 175) can be wire-bonded to the pads 19 of the die 11 or the pads 29 of the die seat 33 via more than one conductive wire 21, so that one pin 17 can transmit one or more identical signals to the outside of the aforementioned semiconductor device 10 at one time. Therefore, one pin 17 can have one or more contact points 23.

[0054] ​​In some embodiments, the contact pad 19 of the die 11 can be wire-bonded to the solder pad 29 of the die pad 33 to transmit a ground signal. Specifically, the solder pad 29 is soldered to one end of the at least one wire 21, and the other end of the at least one wire 21 is soldered to the contact pad 19 of the die 11, and the solder pad 29 receives the ground signal from the die 11 via the wire 21 and transmits the ground signal to the outside of the aforementioned semiconductor device 10. In some embodiments, when the pin 17 is wire-bonded to the solder pad 29 of the die pad 33, the pin 17 transmits the ground signal to the outside of the aforementioned semiconductor device 10.

[0055] Referring to Figure 4 and Figure 17 In some embodiments, the first pin 171 is wire-bonded to the contact pad 19 of the die 11 from the first extension 1713. The second pin 173 is wire-bonded to the contact pad 19 of the die 11 from the second extension 1733. That is, the contact point 23 of the first pin 171 can be at the first extension 1713, and the contact point 23 of the second pin 173 can be at the second extension 1733, so that the size of the control pitch SP and the impedance matching of the wire 21 are controlled, and the first pin 171 and the second pin 173 can transmit high-speed signals.

[0056] In some embodiments, the first extension 1713 and the second extension 1733 can be wire-bonded to the at least one wire 21 (i.e., the first extension 1713 and the second extension 1733 can have at least one contact point 23). If the first pin 171 and the second pin 173 are connected to the wire 21 only through the first extension 1713 and the second extension 1733, then the wire 21 connected to the first pin 171 and the second pin 173 can transmit high-speed signals (such as high-speed differential signals), but the present application is not limited thereto, and can also transmit low-speed signals (such as low-speed differential signals), power signals, or single-ended signals.

[0057] In some embodiments, the first pin 171 is wire-bonded to the contact pad 19 of the die 11 from the first body 1711. The second pin 173 is wire-bonded to the contact pad 19 of the die 11 from the second body 1731. That is, the contact point 23 of the first pin 171 can be at the first body 1711, and the contact point 23 of the second pin 173 can be at the second body 1731.

[0058] In some embodiments, the first body 1711 and the second body 1731 can be used to wire bond at least one wire 21 (i.e., the first body 1711 and the second body 1731 can have at least one contact 23). If the first pin 171 and the second pin 173 are connected to the wire 21 only through the first body 1711 and the second body 1731, then the wire 21 connected to the first pin 171 and the second pin 173 can transmit low-speed signals (e.g., low-speed differential signals), power signals, or single-ended signals. In some embodiments, the first pin 171 can be connected to multiple wires 21 through the first extension 1713 and the first body 1711, and the second pin 173 can be connected to multiple wires 21 through the second extension 1733 and the second body 1731, then the wires 21 connected to the first pin 171 and the second pin 173 can transmit low-speed signals, power signals, or single-ended signals.

[0059] In some embodiments, the spacing SP between each wire 21 connecting the first pin 171 and the second pin 173 of the same pair is not greater than five times the wire diameter of each wire 21, so that the lengths of the wires 21 of the first pin 171 and the second pin 173 are approximately the same, and the spacing SP meets the requirements, and the impedance matching of the wires 21 is optimized to transmit high-speed signals. In this embodiment, the same pair of the first pin 171 and the second pin 173 having the spacing SP between the wires 21 not greater than five times the wire diameter can transmit high-speed signals (e.g., a pair of high-speed differential signals), but the present application is not limited thereto, and can also transmit low-speed signals (e.g., a pair of low-speed differential signals), power signals, or single-ended signals, etc.

[0060] In some embodiments, as shown in FIG. 1A, the first pin 171 and the second pin 173 are respectively wire bonded to the die 11 through at least one wire 21, and each wire 21 connecting the first pin 171 and the second pin 173 of the same pair has the same wire arc height LH. In this embodiment, the same pair of the first pin 171 and the second pin 173 having the same wire arc height LH can transmit high-speed signals (e.g., a pair of high-speed differential signals), but the present application is not limited thereto, and can also transmit low-speed signals (e.g., a pair of low-speed differential signals), power signals, or single-ended signals, etc. Figure 1 Figure 1 For ease of illustration, only the first pin 171 and the second pin 173 are respectively wire bonded to the die 11 through one wire 21, but the present application is not limited thereto, and the first pin 171 and the second pin 173 can be respectively wire bonded to the die 11 through multiple wires 21. By the wires 21 of the first pin 171 and the second pin 173 having the same wire arc height LH, the lengths of the wires 21 of the first pin 171 and the second pin 173 can be more approximately the same, so that the spacing SP of the wires 21 and the impedance matching of the wires 21 can be controlled, and high-speed signals can be transmitted. In this embodiment, the same pair of the first pin 171 and the second pin 173 having the same wire arc height LH can transmit high-speed signals (e.g., a pair of high-speed differential signals), but the present application is not limited thereto, and can also transmit low-speed signals (e.g., a pair of low-speed differential signals), power signals, or single-ended signals, etc.​

[0061] Reference Figure 18 , Figure 18 This is a bottom view schematic diagram of a semiconductor device 10 according to some embodiments of the present invention. In some embodiments, Figure 18 It can also be a bottom view of the integrated circuit lead frame 13. In some embodiments, the first body 1711 and the second body 1731 are exposed outside the package 15, and the first extension 1713 and the second extension 1733 (in) Figure 18 (Not shown) is located within the package 15. Specifically, the bottoms of the first body 1711 and the second body 1731 protrude outside the package 15 for connection to external circuitry (e.g., a circuit board outside the semiconductor device 10) to receive signals from the die 11 (e.g., high-speed / low-speed differential signals, power signals, single-ended signals, etc.) or to transmit signals to the die 11. When the first extension 1713 and the second extension 1733 are enclosed within the package 15, interference caused by external circuitry connections can be reduced, such as short circuits with other circuitry. In some embodiments, the bottom of the pad 29 of the die holder 33 may protrude outside the package 15 for connection to external circuitry of the semiconductor device 10 to transmit signals (e.g., ground signals, etc.). In some embodiments, the bottom of the third pin 175 may protrude outside the package 15 for connection to external circuitry of the semiconductor device 10 to transmit signals (e.g., single-ended signals, etc.). In some embodiments, the area of ​​pin 17 where the wire 21 is wire-connected (or the area where the contact 23 can be positioned) (hereinafter referred to as the wire-connection area LA) may be slightly larger than or the same as the area of ​​the bottom of pin 17 exposed outside the package 15 (hereinafter referred to as the exposed area OA). For example, refer to Figure 19 , Figure 19 This is a side cross-sectional view of the same pair of first pins 171 and second pins 173 in some embodiments of the present invention. The bonding areas LA1 and LA3 of the first body 1711 of the first pin 171 and the second body 1731 of the second pin 173 can be slightly larger than or the same as the exposed areas OA1 and OA3 at their bottom exposed outside the package body 15.

[0062] Reference Figure 3 and Figure 20 . Figure 20 This is a top view schematic diagram of the integrated circuit lead frame 13 according to some embodiments of the present invention. It can be seen that, through the design of the pins 17 of the present invention, the pins 17 (such as the first pin 171, the second pin 173, and the third pin 175) are arranged in multiple rows around the die holder 33. For example, as... Figure 3 As shown, each side of the die holder 33 has two rows of pins 17 arranged in a specific order; as Figure 20As shown, each side of the die pad 33 has three columns of pins 17 arranged thereon. This results in a significant increase in the number of pins 17 for a single semiconductor device 10.

[0063] Referring to Figure 21 , Figure 21 is a side view of a semiconductor device 10 according to some embodiments of the present application. In some embodiments, the packaging technology of the semiconductor device 10 can employ an Advanced Quad Flat No leads (AQFN) package. For example, the semiconductor device 10 can be first formed on a molding line F upper half as an integrated circuit lead frame 13. After the molding line F upper half is encapsulated (e.g., overmolded) with an encapsulant 15A, the molding line F lower half is formed by etching a metal portion (e.g., copper metal of the integrated circuit lead frame 13) and filling the etched portion with an encapsulant 15B. The metal portion is then exposed outside the encapsulant 15. Because the process of forming an AQFN package is more flexible than that of a conventional Quad Flat No leads (QFN) package, the design of the pins 17 can be more varied and less limited. In some embodiments, the material used for the encapsulant 15A of the molding line F upper half can be different from the material used for the encapsulant 15B of the molding line F lower half, but the present application is not limited thereto. The material used for the encapsulant 15A of the molding line F upper half can be the same as the material used for the encapsulant 15B of the molding line F lower half. Figure 21 Referring to

[0064] , Figure 22 , Figure 22 is a schematic diagram of an impedance system according to some embodiments of the present application. In some embodiments, the material of the encapsulant 15 can be selected according to the impedance system to which the semiconductor device 10 is applied. For example, if the semiconductor device 10 is applied to a 100-ohm impedance system, the material of the encapsulant 15 can be a general epoxy encapsulant material. If the semiconductor device 10 is applied to an 85-ohm or 90-ohm impedance system, the material of the encapsulant 15 can be an alumina-type epoxy encapsulant material, but the present application is not limited thereto.

[0065] In some embodiments, the integrated circuit lead frame 13 can have a different distribution of pins 17 or a different number of pins 17 at one of the corners than at the other corners (e.g., as shown in FIG. 2A). For example, the integrated circuit lead frame 13 can have a different number of pins 17 at the corner 31 than at the other corners 32, 33, 34. In some embodiments, the integrated circuit lead frame 13 can have a different distribution of pins 17 at the corner 31 than at the other corners 32, 33, 34. In some embodiments, the integrated circuit lead frame 13 can have a different number of pins 17 at the corner 31 than at the other corners 32, 33, 34, and a different distribution of pins 17 at the corner 31 than at the other corners 32, 33, 34. Figure 20As shown, the number of pins 17 of one of the corners of the IC leadframe 13 can be less than the number of pins 17 of the other corners, for the user to identify the orientation of the IC leadframe 13 and the semiconductor device 10 including the IC leadframe 13 (e.g., the orientation of the IC leadframe 13 in the semiconductor device 10 or the orientation of the semiconductor device 10 on a circuit board). In some embodiments, the shape of one of the corners of the die pad 33 can be configured to be different from the shape of the other corners. For example, as shown in FIG. 1, one of the corners of the die pad 33 is a notched corner, while the other corners are not notched, to assist in identifying the orientation of the IC leadframe 13 and the semiconductor device 10. Figure 2 and Figure 3 As shown, one of the corners of the die pad 33 is a notched corner, while the other corners are not notched, to assist in identifying the orientation of the IC leadframe 13 and the semiconductor device 10.

[0066] In summary, according to embodiments of the present application, by the design of the shape of the pins (e.g., the contact points of the two pins of a pair for wire bonding extending towards each other) and the wire bonding packaging technique, the pitch of the wires of the pair of pins is reduced, to achieve good impedance matching and to provide high speed signal transmission and to reduce the manufacturing cost.

[0067] REFERENCE NUMERALS:

[0068] 10: semiconductor device

[0069] 11: die

[0070] 19: pad

[0071] 13: IC leadframe

[0072] 33: die pad

[0073] 29: solder pad

[0074] 17: pin

[0075] 171: first pin

[0076] 1711: first body

[0077] 1713: first extension

[0078] 1715: connecting end

[0079] 1716: free end

[0080] D1: first direction

[0081] 173: second pin

[0082] 1731: second body

[0083] 1733: second extension

[0084] 1735: connection end

[0085] 1736: free end

[0086] D2: second direction

[0087] 175: third pin

[0088] 21, 21A, 21B: wire

[0089] 23, 23A, 23B: contact

[0090] SP: spacing

[0091] SA: stagger axis

[0092] ED1, ED3: extension length

[0093] 35: edge region

[0094] 351: first region

[0095] 353: second region

[0096] DA: axis

[0097] D3: first extension direction

[0098] D4: second extension direction

[0099] BR1, BR3: body diameter

[0100] PS: pin spacing

[0101] LH: wire arc height

[0102] LA, LA1, LA3: wire bonding region

[0103] OA, OA1, OA3: exposed region

[0104] 15, 15A, 15B: package

[0105] F: formed wire

Claims

1. An integrated circuit leadframe, comprising: a die pad for disposing a die; and a plurality of leads for wire bonding to the die, wherein the leads include a pair of a first lead and a second lead, the first lead includes a first body and a first extension connected to the first body, the second lead includes a second body and a second extension connected to the second body, wherein the first extension and the second extension extend in a direction approaching each other, and the first extension and the second extension are both configured for wire bonding to the die.

2. The integrated circuit leadframe of claim 1, wherein the first extension extends in a first direction and the second extension extends in a second direction, and the first direction and the second direction are parallel to each other.

3. The integrated circuit leadframe of claim 1, wherein the first lead and the second lead are of a same shape.

4. The integrated circuit leadframe of claim 1, wherein the first extension and the second extension are partially interleaved.

5. The integrated circuit leadframe of claim 1, wherein the first lead and the second lead carry a pair of differential signals.

6. The integrated circuit leadframe of claim 1, wherein the first lead carries a power signal.

7. The integrated circuit leadframe of claim 1, wherein the first lead also wire bonds to the die from the first body.

8. The integrated circuit leadframe of claim 1, wherein the leads further include a third lead, and the third lead is of a same shape as the first body or the second body.

9. A semiconductor device, comprising: a die; an integrated circuit leadframe, comprising: a die pad for disposing the die; and a plurality of leads for wire bonding to the die, wherein the leads include a pair of a first lead and a second lead, the first lead includes a first body and a first extension connected to the first body, the second lead includes a second body and a second extension connected to the second body, wherein the first extension and the second extension extend in a direction approaching each other, and the first extension and the second extension are both configured for wire bonding to the die; and a package encapsulating the die and part of the integrated circuit leadframe.

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