Semiconductor structure and method of fabricating the same

Abstract

A semiconductor structure and a method of fabricating the same are disclosed. The semiconductor structure includes a substrate having a plurality of fin structures thereon, an insulating oxide structure disposed in the substrate, the insulating oxide structure being disposed between two adjacent fin structures, wherein the insulating oxide structure has a concave arc-shaped top surface, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the gate and the plurality of fin structures, and a drain / source doped region disposed in each of the plurality of fin structures.

Description

[0001] This application is a divisional application of a Chinese patent application with the application number 201810579878.3 and the application date 07 / 06 / 2018, which is entitled "Semiconductor structure and manufacturing method thereof". TECHNICAL FIELD

[0002] The present application relates to a semiconductor structure and a manufacturing method thereof, and more particularly to a fin field effect transistor (FinFET) device structure. BACKGROUND

[0003] Higher integration of semiconductor memory devices helps to meet the needs of consumers for superior performance and low prices. However, as the density of circuit elements in a chip or die increases, the distance between adjacent elements becomes smaller and smaller, and the semiconductor manufacturing process encounters more and more challenges.

[0004] During the manufacturing process of nanoscale fin field effect transistor devices, the residue of high molecular polymer has become a serious problem. After the dummy polysilicon gate is patterned on the fin structure, the high molecular polymer residue can remain on the chip and cause reliability problems. The high molecular polymer residue tends to accumulate at the uneven corners between the sidewalls of the upward protruding fin and the top surface of the surrounding shallow trench isolation (STI) region. These high molecular polymer residues are difficult to remove and can cause silicon holes to be formed in the source / drain regions in the subsequent replacement metal gate (RMG) manufacturing process. SUMMARY

[0005] The main purpose of the present application is to provide an improved fin field effect transistor (FinFET) device structure and a manufacturing method thereof to solve the above-mentioned problems and shortcomings of the prior art.

[0006] According to an embodiment, the semiconductor structure of the present application comprises a substrate having a plurality of fin structures thereon; an insulating oxide structure disposed in the substrate, the insulating oxide structure being between two adjacent fin structures, wherein the insulating oxide structure has a concave arc-shaped top surface; a gate disposed on the plurality of fin structures; a gate dielectric layer disposed between the gate and the plurality of fin structures; and a drain / source doped region disposed in each of the plurality of fin structures.

[0007] According to another embodiment, a semiconductor structure includes a substrate having a fin structure thereon; a first insulating oxide structure having a first arc-shaped top surface formed on one side of the fin structure; a second insulating oxide structure having a second arc-shaped top surface formed on another side of the fin structure opposite to the first insulating oxide structure, wherein the first insulating oxide structure and the second insulating oxide structure have different depths; a gate formed on the fin structure; a gate dielectric layer formed between the gate and the fin structure; and a drain / source doping region formed in the fin structure.

[0008] A method for fabricating a semiconductor device is also disclosed. A substrate having a fin structure thereon is provided. A first insulating oxide structure having a first arc-shaped top surface is formed on one side of the fin structure. A second insulating oxide structure having a second arc-shaped top surface is formed on another side of the fin structure opposite to the first insulating oxide structure, wherein the first insulating oxide structure and the second insulating oxide structure have different depths. A gate is formed on the fin structure. A drain / source doping region is formed in the fin structure.

[0009] The present disclosure avoids the problem of polymer residue accumulation and prevents the formation of silicon voids in the source / drain region by forming a concave arc-shaped top surface in the insulating oxide structure or shallow trench isolation region, thereby avoiding the formation of uneven corners at the junction with the sidewall of the adjacent fin or fin structure.

[0010] In order to make the above objects, features and advantages of the present disclosure more clear and comprehensible, preferred embodiments will be described in detail below with reference to the accompanying drawings. However, the following preferred embodiments and drawings are only for reference and illustration, and are not intended to limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figures 1 to 8 FIG. 1 is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure, wherein a substrate having a fin structure thereon is provided;

[0012] Figures 1 to 5 FIG. 2 is a schematic diagram illustrating a cross-sectional view of the semiconductor device according to an embodiment of the present disclosure, wherein a first insulating oxide structure having a first arc-shaped top surface is formed on one side of the fin structure;

[0013] Figure 4 FIG. 3 is a schematic diagram illustrating an enlarged view of the fin structure according to an embodiment of the present disclosure;

[0014] Figure 6 FIG. 4 is a schematic diagram illustrating a perspective side view of the semiconductor device according to an embodiment of the present disclosure, wherein a gate is formed on the fin structure;

[0015] Figure 7 FIG. 5 is a schematic diagram illustrating a perspective side view of the semiconductor device according to an embodiment of the present disclosure, wherein a drain / source doping region is formed in the fin structure on both sides of the gate;

[0016] Figure 8Example completed replacement metal gate process from a perspective side view.

[0017] Explanation of main elements

[0018] 10 substrate

[0019] 101-105 fin structures

[0020] 101a-105a top surface

[0021] 104SL first sidewall

[0022] 104SR second sidewall

[0023] 110 liner layer

[0024] 110a top surface

[0025] 112 hard mask layer

[0026] 112a top surface

[0027] 200 insulating oxide structure

[0028] 201 first insulating oxide structure

[0029] 201ac first arcuate top surface

[0030] 201ap top surface

[0031] 201t highest upper edge

[0032] 201b lowest point

[0033] 201tl tangent line

[0034] 202 second insulating oxide structure

[0035] 202ac second arcuate top surface

[0036] 202ap top surface

[0037] 202t highest upper edge

[0038] 202b lowest point

[0039] 202tl tangent line

[0040] 260 gate oxide layer

[0041] 280 dummy gate

[0042] 290 spacer

[0043] 302, 304 drain / source doped regions

[0044] 360 high-k gate dielectric

[0045] 380 metal gate

[0046] hi-h4 depth

[0047] P1, P2 pitch

[0048] T ROX drop

[0049] θ1, θ2 angle DETAILED DESCRIPTION

[0050] Hereinafter, details will be described with reference to the accompanying drawings, which constitute a part of the detailed description of the specification and are drawn in a manner of describing specific examples that can implement the embodiments. The embodiments are described in sufficient details so that those skilled in the art can implement them.

[0051] Of course, other embodiments can be implemented, or any structural, logical, and electrical changes can be made without departing from the embodiments described herein. Therefore, the detailed description below should not be regarded as limiting, but the embodiments contained therein will be defined by the appended claims.

[0052] Please refer to Figures 1 to 8 which illustrates a method for manufacturing a semiconductor device according to an embodiment of the present application. As shown in Figure 1 , a substrate 10, such as a semiconductor substrate of silicon, silicon germanium, etc., having fin structures 101-105 thereon is provided first. The fin structures 101-104 are four continuous fin structures densely and parallelly arranged together, and the fin structure 105 is an isolated (or semi-isolated) fin structure. For example, the pitch P1 between the four continuous fin structures 101-104 can be between 90 nm and 200 nm, and the pitch P2 between the isolated fin structure 105 and the nearest fin structure 104 can be between 400 nm and 1000 nm, but not limited thereto. Such continuous, densely and parallelly arranged four fin structures 101-104 and the isolated fin structure 105 can be applied in static random access memory (SRAM) circuits, but not limited thereto.

[0053] Since the method for manufacturing the fin structures 101-105 is a prior art, including photolithography and etching manufacturing processes, which will not be described again. According to the embodiment of the present application, a liner layer 110 and a hard mask layer 112 are provided on the fin structures 101-105 at this time. For example, the liner layer 110 can be a silicon dioxide layer, and the hard mask layer 112 can be a silicon nitride layer, but not limited thereto.

[0054] After defining the fin structures 101-105, an insulating oxide structure 200 is then formed between the fin structures 101-105. For example, a first insulating oxide structure 201 is formed between the fin structures 101-104 on one side of the fin structure 104 (e.g., the left side of the fin structure 104 in the figure), and a second insulating oxide structure 202 is formed between the fin structures 104-105 on the other side of the fin structure 104 opposite to the first insulating oxide structure 201 (e.g., the right side of the fin structure 104 in the figure). Since the method for fabricating the insulating oxide structure 200 is existing shallow trench insulation or shallow trench isolation technology, including insulating layer deposition and chemical mechanical polishing processes, it will not be described in detail here. At this time, after polishing, the top surface 201ap of the first insulating oxide structure 201 and the top surface 202ap of the second insulating oxide structure 202 are approximately flush with the top surface 112a of the hard mask layer 112.

[0055] like Figure 2 As shown, the hard mask layer 112 is then selectively removed to expose the top surface 110a of the pad layer 110. For example, the hard mask layer 112 can be removed using a wet etching method. At this time, there will be a height difference T between the first insulating oxide structure 201 and the top surface 110a of the pad layer 110. ROX According to an embodiment of the present invention, the aforementioned drop T ROX It needs to be less than 140 angstroms, for example, between 20 and 140 angstroms. According to an embodiment of the present invention, the aforementioned drop T... ROX The thickness of the hard mask layer 112 can be controlled by chemical mechanical polishing.

[0056] like Figure 3 As shown, an etching process is then performed, for example, on SiConi. TM Etching, selective etching, exposes the pad layer 110 and the insulating oxide structure 200. It is known that SiConi... TM Etching is a remote plasma-assisted dry etching process that involves exposing a substrate or wafer to plasma byproducts of hydrogen, nitrogen trifluoride (NF3), and ammonia (NH3). For example, NF3 and NH3 are first excited to convert into ammonium fluoride (NH4F) and ammonium difluoride (NH4F·HF), respectively. Then, NH4F and NH4F·HF react with silicon oxide to etch, generating solid hexafluorosilane ammonia ((NH4)2SiF6) etching byproducts. This silicate prevents further etching. Next, annealing is performed to sublimate the solid etching byproducts ((NH4)2SiF6), which decompose at high temperatures into gaseous silicon tetrafluoride (SiF4), ammonia (NH3), and hydrogen fluoride (HF).

[0057] After the foregoing etching process, the top surfaces 101a-105a of the fin structures 101-105 and portions of the sidewalls are exposed, wherein the top surfaces 101a-105a are approximately planar, and the insulating oxide structures 200 are lower than the top surfaces 101a-105a and form arcuate top surfaces. Hereinafter, the term "arcuate top surface" refers to a curved top surface that has a curvature when viewed in cross-section, in other words, the arcuate top surfaces formed do not include planar surfaces.

[0058] For example, the first arcuate top surface 201ac of the first insulating oxide structure 201 and the second arcuate top surface 202ac of the second insulating oxide structure 202 are both lower than the top surfaces 101a-105a. The first arcuate top surface 201ac of the first insulating oxide structure 201 and the second arcuate top surface 202ac of the second insulating oxide structure 202 are both concave arcuate top surfaces when viewed in cross-section, and more specifically, the first arcuate top surface 201ac of the first insulating oxide structure 201 and the second arcuate top surface 202ac of the second insulating oxide structure 202 are both concave silicon dioxide arcuate top surfaces. Herein, the term "concave" refers to a vertical distance downward into the major surface of the substrate 10.

[0059] The first arcuate top surface 201ac of the first insulating oxide structure 201 has a highest upper edge 201t that is adjacent to a first sidewall 104SL of the fin structure 104, wherein the highest upper edge 201t has a depth hi. Hereinafter, the term "depth" refers to a vertical distance downward from the top surfaces 101a-105a of the fin structures 101-105, unless otherwise specified. The second arcuate top surface 202ac of the second insulating oxide structure 202 has a highest upper edge 202t that is adjacent to a second sidewall 104SR of the fin structure 104, and the highest upper edge 202t has a depth h2, wherein the depth h2 is greater than the depth hi. According to embodiments of the present application, for example, the depth hi is between 400-500 Angstroms, and the depth h2 is between 450-550 Angstroms.

[0060] According to embodiments of the present application, the concave first arcuate top surface 201ac has a lowest point 201b that is approximately centrally located on the concave arcuate top surface 201ac between the adjacent fin structures 103 and 104, and the lowest point 201b has a depth h3 that is between 500-700 Angstroms. The concave second arcuate top surface 202ac has a lowest point 202b that is approximately centrally located on the concave arcuate top surface 202ac between the adjacent fin structures 104 and 105, and the lowest point 202b has a depth h4 that is between 500-600 Angstroms. According to embodiments of the present application, the depth h3 is greater than the depth h4.

[0061] As shown in FIG. 1, the first insulating oxide structure 201 is formed on the first sidewall 104SL of the fin structure 104, and the second insulating oxide structure 202 is formed on the second sidewall 104SR of the fin structure 104. The first insulating oxide structure 201 and the second insulating oxide structure 202 are formed on the sidewalls 104SL and 104SR of the fin structure 104, and the first insulating oxide structure 201 and the second insulating oxide structure 202 are formed on the sidewalls 103SL and 103SR of the fin structure 103, and the first insulating oxide structure 201 and the second insulating oxide structure 202 are formed on the sidewalls 105SL and 105SR of the fin structure 105. Figure 4As shown, the angle θ1 between the tangent 201tl at the contact point between the highest upper edge 201t and the first sidewall 104SL and the first sidewall 104SL is approximately between 130 and 140 degrees, while the angle θ2 between the tangent 202tl at the contact point between the highest upper edge 202t and the second sidewall 104SR and the second sidewall 104SR is approximately between 125 and 135 degrees.

[0062] like Figure 5 and Figure 6 As shown, a dummy gate 280, for example, a polysilicon gate, is then formed on the fin structures 101-105 and the insulating oxide structure 200. A gate oxide layer 260 may be formed between the dummy gate 280 and the fin structures 101-105, and between the dummy gate 280 and the insulating oxide structure 200. The dummy gate 280 may be composed of a single layer of polysilicon or a multilayer material, such as polysilicon and a silicon nitride capping layer, but is not limited thereto.

[0063] like Figure 7 As shown, spacer walls 290, such as silicon nitride spacer walls, are then formed on both sides of the dummy gate 280. Drain / source doped regions 302 and 304 are then formed in the fin structures 101-105 on both sides of the dummy gate 280. The drain / source doped regions 302 and 304 include an epitaxial stress layer, such as a silicon-phosphorus (SiP) epitaxial layer or a silicon-germanium (SiGe) epitaxial layer, but are not limited thereto. The formation steps of the drain / source doped regions 302 and 304 described above are well-known processes, and their details will not be elaborated further. For example, trenches can be etched first in the fin structures 101-105 on both sides of the dummy gate 280, followed by an epitaxial step and ion implantation to inject N-type or P-type dopants into the drain / source doped regions 302 and 304.

[0064] like Figure 8 As shown, drain / source doped regions 302 and 304 are completed, and finally, a replacement metal gate (RMG) process is performed to replace the dummy gate 280 and gate oxide layer 260 with a metal gate 380 and a high-k dielectric gate layer 360, respectively. The above-mentioned replacement metal gate process is a well-known process, so its details will not be elaborated further. For example, an interlayer dielectric layer (not shown) can be deposited first, followed by a chemical mechanical polishing (CMP) process to remove part of the interlayer dielectric layer and part of the dummy gate 280. Then, the remaining dummy gate 280 and gate oxide layer 260 are removed by etching to form a gate trench. A high-k dielectric gate layer 360 and a metal gate 380 are then filled into the gate trench, and a second chemical mechanical polishing can be performed.

[0065] The present application avoids the uneven corner at the joint with the sidewall of the adjacent fin structure 101-105 by forming the concave arc top surface 201ac, 202ac in the insulating oxide structure 200, solves the polymer residue accumulation problem and prevents the silicon cavity in the source / drain region.

[0066] The above description is only the preferred embodiment of the present application, any equivalent changes and modifications made according to the claims of the present application shall be within the scope of the present application.

Claims

1. A semiconductor structure comprising: The substrate has multiple fin-like structures, including four consecutive first fin-like structures arranged in parallel and densely, and isolated second fin-like structures. The four first fin-like structures have a first spacing between them, and the one of the four first fin-like structures closest to the second fin-like structure has a second spacing with the second fin-like structure. The first spacing is smaller than the second spacing. A first insulating oxide structure and a second insulating oxide structure are disposed in the substrate. The first insulating oxide structure is located between two adjacent first fin structures among the four first fin structures. The second insulating oxide structure is located between the first fin structure closest to the second fin structure and the second fin structure. The first insulating oxide structure has a concave first arc-shaped top surface, and the second insulating oxide structure has a concave second arc-shaped top surface. The first arc-shaped top surface has a first highest upper edge adjacent to the first sidewall of the first fin structure, and the second arc-shaped top surface has a second highest upper edge adjacent to the second sidewall of the first fin structure. The first highest upper edge has a first depth, and the second highest upper edge has a third depth, wherein the first depth is less than the third depth. A gate is disposed on the plurality of fin structures; A gate dielectric layer is disposed between the gate and the plurality of fin structures; as well as Drain / source doped regions are located in each of the plurality of fin structures.

2. The semiconductor structure as claimed in claim 1, wherein the first and second arc-shaped top surfaces are both concave silicon dioxide arc-shaped top surfaces.

3. The semiconductor structure of claim 1, wherein the first depth is between 400 and 500 angstroms.

4. The semiconductor structure of claim 1, wherein the concave first arcuate top surface has a lowest bottom surface located at the center of the concave arcuate top surface between two adjacent first fin structures.

5. The semiconductor structure of claim 4, wherein the lowest bottom surface has a second depth between 500 and 700 angstroms.

6. The semiconductor structure of claim 1, wherein the gate is a metal gate.

7. The semiconductor structure of claim 1, wherein the drain / source doped region comprises an epitaxial stress layer.

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