superjunction device

Abstract

A super junction device is disclosed. The super junction device includes a semiconductor substrate and a super junction structure on a first surface of the semiconductor substrate, the super junction structure including a plurality of first semiconductor pillars and a plurality of second semiconductor pillars. The super junction device includes a cell region and a termination region surrounding the cell region. A portion of the super junction structure is in the cell region and another portion of the super junction structure is in the termination region. The super junction device further includes a guard ring in the termination region and surrounding the cell region. The guard ring includes a plurality of doped regions extending in segments and a top portion of a first set of semiconductor pillars connecting the plurality of doped regions into a continuous ring. The top portion of the first set of semiconductor pillars in the guard ring of the super junction device is not doped, thus improving impurity distribution of the guard ring and charge balance in the termination region, and improving the withstand voltage performance of the super junction device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a superjunction device. Background Technology

[0002] Superjunction devices are an important type of power device. In a superjunction device, alternating P-type and N-type semiconductor pillars are formed in the lightly doped drift region of a MOS (Metal-Oxide-Semiconductor) transistor, with a PN junction formed between them. In the on-state of the superjunction device, the N-type semiconductor pillars provide the conductive path, and the highly doped N-type pillars reduce the on-resistance. In the off-state, both the P-type and N-type semiconductor pillars share the reverse bias voltage. A lateral local electric field is formed between the P-type and N-type semiconductor pillars. The lateral termination of the charge lines allows the entire drift region to approximate an intrinsic layer in the longitudinal direction of the breakdown voltage, thus modulating the longitudinal electric field and optimizing its distribution. This utilizes the charge balance principle to improve the breakdown voltage of the MOS transistor. Therefore, superjunction devices can simultaneously achieve good on-resistance and breakdown voltage of a MOS transistor.

[0003] Because the actual area of ​​superjunction devices is limited, the periodic arrangement of the superjunction structure will be interrupted at the cell boundaries. Under reverse bias, charge imbalance will occur in the edge cells of the cell region, leading to premature breakdown. Therefore, practical superjunction devices form a termination region surrounding the cell region, with a guard ring within the termination region to optimize the edge electric field distribution and ensure normal breakdown voltage. This guard ring may be formed by continuously doping the tops of P-type and N-type semiconductor pillars to create a P-type doped region. Since the guard ring is a heavily doped P-type doped region, in the termination region, the adjacent area below the P-type semiconductor pillar is overdoped while the adjacent area below the N-type semiconductor pillar is underdoped, which disrupts the charge balance between the P-type and N-type semiconductor pillars. Therefore, premature breakdown of the superjunction device may still occur.

[0004] Therefore, it is desirable to further optimize the structure of the termination region of the superjunction device to ensure the normal withstand voltage of the termination region, so as to improve the withstand voltage reliability of the superjunction device. Summary of the Invention

[0005] In view of the above problems, the object of the present invention is to provide a superjunction device, wherein the termination region surrounds the cell region, and the guard ring in the termination region includes segmented doped regions and undoped semiconductor pillars between adjacent doped regions, thereby improving the impurity distribution of the guard ring and the charge balance in the termination region.

[0006] According to one aspect of the present invention, a superjunction device is provided, comprising: a semiconductor substrate; and a superjunction structure located on a first surface of the semiconductor substrate, the superjunction structure comprising a plurality of first semiconductor pillars and a plurality of second semiconductor pillars, the plurality of first semiconductor pillars and the plurality of second semiconductor pillars being alternately arranged and adjacent to each other on the first surface, the plurality of first semiconductor pillars and the plurality of second semiconductor pillars having opposite doping types, and adjacent first semiconductor pillars and second semiconductor pillars forming a PN junction, wherein the superjunction device comprises a cell region and a terminal region surrounding the cell region, a portion of the superjunction structure being located in the cell region and another portion being located in the terminal region, the superjunction device further comprising a guard ring located in the terminal region and surrounding the cell region, the guard ring comprising a plurality of segmented doped regions and a top portion of a first set of semiconductor pillars connecting the plurality of doped regions into a continuous ring.

[0007] Preferably, the plurality of doped regions are located at the top of the second group of semiconductor pillars, and adjacent doped regions in the plurality of doped regions are adjacent to a corresponding semiconductor pillar in the first group of semiconductor pillars.

[0008] Preferably, the first group of semiconductor pillars is selected from the plurality of first semiconductor pillars, and the second group of semiconductor pillars is selected from the plurality of second semiconductor pillars.

[0009] Preferably, each of the plurality of first semiconductor pillars and the plurality of second semiconductor pillars extends parallel to each other along a first direction and is arranged alternately along a second direction.

[0010] Preferably, the width of the guard ring in the first direction corresponds to the length of the corresponding doped region in the first direction among the plurality of doped regions.

[0011] Preferably, the width of the guard ring in the second direction corresponds to the sum of the width of the corresponding doped region in the second direction and the width of the first semiconductor pillar adjacent to the corresponding doped region.

[0012] Preferably, in the cell region, the superjunction device further includes a body region located at the top of the plurality of first semiconductor pillars, and a source region located in the body region.

[0013] Preferably, the junction depth of the plurality of doped regions is comparable to the junction depth of the bulk region.

[0014] Preferably, the guard ring includes a plurality of sub-rings, each of the plurality of sub-rings including a plurality of segmented doped regions and the top portion of a first set of semiconductor pillars connecting the plurality of doped regions into a continuous ring.

[0015] Preferably, the plurality of sub-rings are separated from each other by undoped regions of the second set of semiconductor pillars.

[0016] Preferably, the distance between the plurality of sub-rings increases accordingly with the distance from the edge of the cell region.

[0017] Preferably, the semiconductor substrate, the plurality of second semiconductor pillars, and the source region are each of the first doping types, and the plurality of first semiconductor pillars, the body region, and the plurality of doped regions are each of the second doping types.

[0018] Preferably, the first doping type is N-type and the second doping type is P-type.

[0019] In the superjunction device according to an embodiment of the present invention, the termination region surrounds the cell region, and the guard ring in the termination region includes multiple segmented doped regions and undoped semiconductor pillars between adjacent doped regions. On one hand, the guard ring is a continuously extending semiconductor ring of a single doped type, which can optimize the edge electric field distribution of the cell region. On the other hand, the guard ring includes multiple segmented doped regions, including only heavy doping of the top of the second semiconductor pillar, inverting the doping type of the top portion of the second semiconductor pillar, while the top portion of the first semiconductor pillar remains entirely undoped. Therefore, in the termination region, the charge balance between adjacent semiconductor pillars can be improved in the adjacent region below the doped regions, which is beneficial to improving the breakdown voltage reliability of the termination region of the superjunction device.

[0020] In a preferred embodiment, the junction depth of the guard ring doped region formed in the termination region is comparable to that of the body region formed in the cell region, both having shallow junction depths. Therefore, between the cell region and the termination region, the charge balance between adjacent semiconductor pillars can be improved in the adjacent region below the doped region, thereby enhancing the overall breakdown voltage reliability of the superjunction device's cell region and termination region. Attached Figure Description

[0021] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0022] Figure 1a , Figure 1b A perspective view and a top view of a portion of the structure of a superjunction device according to the prior art are shown respectively;

[0023] Figure 2a , Figure 2b and Figure 2c Perspective view, top view and cross-sectional view of a portion of the structure of the superjunction device according to an embodiment of the present invention are shown respectively. Detailed Implementation

[0024] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0025] In this application, the term "semiconductor structure" refers to the collective term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. Many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details.

[0026] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0027] Figure 1a , Figure 1b Perspective and top views of a portion of the structure of a superjunction device according to the prior art are shown respectively. For clarity, in Figure 1a and Figure 1b Only the main semiconductor structure is shown, while the interlayer insulating layer, interconnect structure, gate stack structure, and electrode structure are not shown.

[0028] like Figure 1a and Figure 1b As shown, the superjunction device 100 includes a semiconductor substrate 110, and a plurality of first semiconductor pillars 121 and a plurality of second semiconductor pillars 122 located on the semiconductor substrate 110. For clarity, in Figure 1aOnly the first semiconductor pillar 121 is shown, while the second semiconductor pillar 122 is not shown. The semiconductor substrate 110 is, for example, a heavily doped N-type silicon substrate, and the first semiconductor pillar 121 and the second semiconductor pillar 122 are, for example, lightly doped P-type epitaxial layers and N-type epitaxial layers relative to the semiconductor substrate 110, respectively. A plurality of first semiconductor pillars 121 and a plurality of second semiconductor pillars 122 are arranged alternately and adjacent to each other, and adjacent first semiconductor pillars 121 and second semiconductor pillars 122 form a PN junction.

[0029] Further, see Figure 1b As shown in the top view, the device region of the superjunction device 100 is divided into a cell region CA and a termination region TA surrounding the cell region CA. One set of semiconductor pillars from a plurality of first semiconductor pillars 121 and a plurality of second semiconductor pillars 122 on the semiconductor substrate 110 is located in the cell region CA, and the other set of semiconductor pillars is located in the termination region TA. For clarity, Figure 1b Only a portion of the cell region CA and the termination region TA is shown. It can be understood that in the complete device structure, the termination region TA, for example, forms a closed region surrounding the cell region CA.

[0030] Further, see Figure 1a The perspective view shown illustrates that in the cell region CA, a body region 131 is formed at the top of a first semiconductor pillar 121, and a source region 132 is formed within the body region 131. The processes used to form the body region 131 and the source region 132 include ion implantation and thermal annealing. The body region 131 and the source region 132 are, for example, P-type doped and N-type doped regions, respectively. The body region 131 extends laterally into an adjacent second semiconductor pillar 122, and the source region 132 is located within the body region 131. Preferably, a plurality of source regions 132 are formed within the body region 131, and contact regions 133 are formed between adjacent source regions of the plurality of source regions 132. The contact regions 133 are, for example, heavily doped P-type doped regions relative to the body region 131. The function of the contact regions 133 is to form an ohmic contact between the source metal and the body region, ensuring that the source region and the body region are at the same potential and preventing parasitic transistors from turning on.

[0031] Further, see Figure 1aThe perspective view shown depicts a guard ring 141 formed in the termination region TA. This guard ring 141 is a continuously doped region surrounding the cell region CA. The guard ring 141 has the same doping type as the body region 131, for example, both being P-type doped regions. The continuously doped region of the guard ring 141 includes the top portions of the first semiconductor pillar 121 and the top portions of the second semiconductor pillar 122. The process for forming the guard ring 141 includes ion implantation and thermal annealing. Because the doping type of the guard ring 141 is the same as that of the first semiconductor pillar 121 and opposite to that of the second semiconductor pillar 122, in the process of forming the guard ring 141, the top portion of the first semiconductor pillar 121 in the termination region TA is overdoped, and the top portion of the second semiconductor pillar 122 is compensated from N-type to P-type.

[0032] Due to the electric field distribution characteristics of superjunction devices, the periodic arrangement of the cell regions terminates in the termination region. Under reverse bias, electric field concentration occurs in the termination region, easily leading to premature breakdown and a sharp decrease in breakdown voltage. The aforementioned superjunction device includes a termination region surrounding the cell region, forming a guard ring within the termination region to optimize the edge electric field distribution of the cell region. This guard ring may, for example, consist of a P-type doped region formed by doping the tips of P-type and N-type semiconductor pillars. However, although this method optimizes the electric field in the termination region and ensures normal breakdown voltage of the cell region, it easily leads to charge imbalance on the surface of the termination region. Therefore, premature breakdown in the termination region of the superjunction device may still occur.

[0033] Figure 2a , Figure 2b and Figure 2c Perspective view, top view, and cross-sectional view of a portion of the structure of the superjunction device according to an embodiment of the present invention are shown respectively. For clarity, in Figure 2a and Figure 2b Only the main semiconductor structure is shown, while the interlayer insulating layer, interconnect structure, gate stack structure, and electrode structure are not shown.

[0034] like Figure 2a , Figure 2b and Figure 2c As shown, the superjunction device 200 includes a semiconductor substrate 110, and a plurality of first semiconductor pillars 121 and a plurality of second semiconductor pillars 122 located on the semiconductor substrate 110. For clarity, in Figure 2aOnly the first semiconductor pillar 121 is shown, while the second semiconductor pillar 122 is not shown. The semiconductor substrate 110 is, for example, a heavily doped N-type silicon substrate, and the first semiconductor pillar 121 and the second semiconductor pillar 122 are, for example, lightly doped P-type pillars and N-type pillars relative to the semiconductor substrate 110, respectively. A plurality of first semiconductor pillars 121 and a plurality of second semiconductor pillars 122 are arranged alternately and adjacent to each other, and adjacent first semiconductor pillars 121 and second semiconductor pillars 122 form a PN junction.

[0035] In the following text, the plurality of first semiconductor pillars 121 and the plurality of second semiconductor pillars 122 are collectively referred to as a “superjunction structure”.

[0036] The processes described above for forming a plurality of first semiconductor pillars 121 and a plurality of second semiconductor pillars 122 are known. In one process, an N-type epitaxial layer is formed on a semiconductor substrate 110, and then P-type dopant ions are implanted into the N-type epitaxial layer to form a plurality of periodic P-type doped regions, thereby forming a plurality of first semiconductor pillars 121. The portions of the N-type epitaxial layer located between adjacent first semiconductor pillars 121 form a plurality of second semiconductor pillars 122. In another process, an N-type epitaxial layer is formed on the semiconductor substrate 110, and then a plurality of deep trenches are etched to form a plurality of deep trenches. Then, a P-type epitaxial layer is filled in the deep trenches by multiple epitaxial growth, and the P-type epitaxial layer in the plurality of deep trenches forms a plurality of first semiconductor pillars 121. The portions of the N-type epitaxial layer located between adjacent second semiconductor pillars 121 form a plurality of second semiconductor pillars 122.

[0037] Further, see Figure 2b As shown in the top view, the device region of the superjunction device 200 is divided into a cell region CA and a termination region TA surrounding the cell region CA. One set of semiconductor pillars from a plurality of first semiconductor pillars 121 and a plurality of second semiconductor pillars 122 on the semiconductor substrate 110 is located in the cell region CA, and the other set of semiconductor pillars is located in the termination region TA. For clarity, Figure 2b Only a portion of the cell region CA and the termination region TA is shown. It can be understood that in the complete device structure, the termination region TA, for example, forms a closed region surrounding the cell region CA.

[0038] Further, see Figure 2aThe perspective view shown illustrates that a body region 131 is formed at the top of a first semiconductor pillar 121 within the cell region CA, and a source region 132 is formed within the body region 131. The processes used to form the body region 131 and the source region 132 include ion implantation and thermal annealing. The body region 131 and the source region 132 are, for example, P-type doped regions and N-type doped regions, respectively. The body region 131 extends laterally into an adjacent second semiconductor pillar 122, and the source regions 132 are located within the body region 131. Preferably, a plurality of source regions 132 are formed within the body region 131, and contact regions 133 are formed between adjacent source regions of the plurality of source regions 132. The contact regions 133 serve to form an ohmic contact between the source metal and the body region, ensuring that the source region and the body region are at the same potential and preventing parasitic transistors from turning on.

[0039] Further, see Figure 2a The perspective view shown depicts a protective ring 141 forming around the cell region CA in the terminal region TA. This protective ring 141 includes a plurality of segmented doped regions 1411 and a top portion 1412 of a first semiconductor pillar 121 located between adjacent doped regions 1411. The doped regions 1411 have the same doping type as the body region 131, for example, both being P-type doped regions.

[0040] The process for forming the doped region 1411 of the guard ring 141 includes ion implantation and thermal annealing. Unlike prior art processes for forming the guard ring 141, in the superjunction device 200 according to an embodiment of the present invention, the doped region 1411 of the guard ring 141 is only heavily doped at the top of the second semiconductor pillar 122, converting the top portion of the second semiconductor pillar 122 from N-type to P-type. Due to the diffusion effect of thermal annealing, the doped region 1411 may laterally extend into the top portion of the first semiconductor pillar 121. The top portion of the first semiconductor pillar 121 is generally undoped, and the charge balance between the P-type and N-type semiconductor pillars is maintained in the adjacent region below the doped region, further preventing premature breakdown of the termination region while ensuring normal breakdown voltage of the device's cell region and termination region. Since the doped region 1411 is adjacent to the top portion 1412 of the first semiconductor pillar 121, they together form a continuous P-type doped guard ring 141.

[0041] Preferably, each of the plurality of first semiconductor pillars 121 and the plurality of second semiconductor pillars 122 extends parallel to each other along a first direction and is arranged alternately along a second direction. In the termination region TA, the width of the guard ring 141 in the first direction is equal to the length of the doped region in the first direction, and the width in the second direction is equal to the sum of the width of the doped region and the width of the first semiconductor pillar 121 adjacent to the doped region.

[0042] See Figure 2b The top view shown and Figure 2c The cross-sectional view shown. Figure 2bLine AA in the middle shows Figure 2c The cut-off position, in Figure 2c The diagram shows a more detailed structure of the superjunction device 200.

[0043] Furthermore, the superjunction device 200 also includes a gate stack on the body region 131, which includes, for example, a gate dielectric (shown as part of the interlayer dielectric layer 152) and a gate conductor 151 on the body region 131. The gate conductor 151 extends laterally, for example, from the edge of the source region 131 over the second semiconductor pillar 122. The gate dielectric is, for example, a silicon oxide layer with a thickness of 10-50 nanometers, and the gate conductor 151 is, for example, a polysilicon layer with a thickness of 600 to 1000 nanometers.

[0044] Furthermore, the superjunction device 200 also includes an interlayer dielectric layer 152 covering the gate stack and the superjunction structure, a source electrode 161 and a terminal electrode 163 located on the interlayer dielectric layer 152, and a drain electrode 162 located on the surface of the semiconductor substrate 101 opposite to the superjunction structure. The interlayer insulating layer 152 may be composed of silicon oxide, silicon nitride, or other known insulating materials, for example. The source electrode 161, drain electrode 162, and terminal electrode 163 may be composed of any one or any alloy of gold, silver, copper, aluminum, and tungsten, for example. The source electrode 161 is connected to the source region 131 via a conductive channel penetrating the interlayer dielectric layer 152, and the terminal electrode 163 is connected to the doped region 1411 of the guard ring 141 via a conductive channel penetrating the interlayer dielectric layer 152. In this embodiment, the semiconductor substrate 110 also serves as the drain region, and the drain electrode 162 is in direct contact with the semiconductor substrate 110.

[0045] In the above embodiments, a case is described where the termination region of a superjunction device forms a guard ring containing a single sub-ring. Preferably, in the termination region of the superjunction device, adjacent doped regions among a plurality of doped regions are adjacent to a corresponding first semiconductor pillar in a second set of semiconductor pillars to form a plurality of sub-rings, the plurality of sub-rings being separated from each other by undoped second semiconductor pillars in the second set of semiconductor pillars. More preferably, the number of undoped second semiconductor pillars between the plurality of sub-rings increases with the distance from the edge of the cell region so that the spacing between adjacent sub-rings increases accordingly.

[0046] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.

Claims

1. A superjunction device, comprising: Semiconductor substrate; as well as A superjunction structure is located on a first surface of the semiconductor substrate. The superjunction structure includes a plurality of first semiconductor pillars and a plurality of second semiconductor pillars. The plurality of first semiconductor pillars and the plurality of second semiconductor pillars are alternately arranged and adjacent to each other on the first surface. The plurality of first semiconductor pillars and the plurality of second semiconductor pillars have opposite doping types. Adjacent first semiconductor pillars and second semiconductor pillars form a PN junction. The superjunction device includes a cell region and a terminal region surrounding the cell region. A portion of the superjunction structure is located in the cell region, and another portion is located in the terminal region. The superjunction device also includes a protective ring located in the terminal region and surrounding the cell region. The guard ring includes multiple segmented doped regions and the top portion of a first set of semiconductor pillars connecting the multiple doped regions into a continuous ring. The doped regions are located at the top portion of a second set of semiconductor pillars in the terminal region. The first set of semiconductor pillars is selected from the multiple first semiconductor pillars, and the second set of semiconductor pillars is selected from the multiple second semiconductor pillars. When forming the guard ring, only the top portion of the second set of semiconductor pillars is heavily doped to invert its doping type, while the top portion of the first set of semiconductor pillars maintains its original doping type and concentration.

2. The superjunction device according to claim 1, wherein, Adjacent doped regions in the plurality of doped regions are adjacent to a corresponding semiconductor pillar in the first group of semiconductor pillars.

3. The superjunction device according to claim 1, wherein, Each of the plurality of first semiconductor pillars and the plurality of second semiconductor pillars extends parallel to each other along a first direction and is arranged alternately along a second direction.

4. The superjunction device according to claim 3, wherein, The width of the guard ring in the first direction corresponds to the length of the corresponding doped region in the first direction among the plurality of doped regions.

5. The superjunction device according to claim 3, wherein, The width of the guard ring in the second direction corresponds to the sum of the width of the corresponding doped region in the second direction and the width of the first semiconductor pillar adjacent to the corresponding doped region.

6. The superjunction device according to claim 2, wherein, In the cell region, the superjunction device further includes a body region located at the top of the plurality of first semiconductor pillars, and a source region located in the body region.

7. The superjunction device according to claim 6, wherein, The junction depth of the plurality of doped regions is comparable to the junction depth of the bulk region.

8. The superjunction device according to claim 2, wherein, The guard ring includes multiple sub-rings, each of which includes multiple segmented doped regions and the top portion of a first set of semiconductor pillars that connect the multiple doped regions into a continuous ring.

9. The superjunction device according to claim 8, wherein, The plurality of sub-rings are separated from each other by undoped regions of the second set of semiconductor pillars.

10. The superjunction device according to claim 9, wherein, The distance between the plurality of sub-rings increases accordingly with the distance from the edge of the cell region.

11. The superjunction device according to claim 6, wherein, The semiconductor substrate, the plurality of second semiconductor pillars, and the source region are each of the first doping types, and the plurality of first semiconductor pillars, the body region, and the plurality of doped regions are each of the second doping types.

12. The superjunction device according to claim 11, wherein, The first doping type is N-type, and the second doping type is P-type.

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