Packaging structure and manufacturing method thereof

Abstract

The present invention provides a packaging structure and a method for making the same. The method for making the packaging structure comprises the following steps. A carrier having a surface is provided. A copper foil layer is laminated on the surface of the carrier. The copper foil layer is subjected to a subtractive process to form a copper foil circuit layer on the carrier. The copper foil circuit layer exposes a portion of the surface of the carrier. A build-up structure layer is formed on the copper foil circuit layer and the surface of the carrier. The first surface of the copper foil circuit layer is flush with the second surface of the build-up structure layer. At least one electronic component is arranged on the build-up structure layer. A packaging colloid is formed to cover the electronic component and the build-up structure layer. The carrier is removed to expose the first surface of the copper foil circuit layer. The packaging structure and the method for making the same of the present invention have better structural reliability and better process yield.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a packaging structure and a manufacturing method thereof. Background Art

[0002] When manufacturing a micro LED substrate or a sub-millimeter LED substrate, the surface flatness of the metal pads on the outermost layer that is bonded to the LED chip must be less than 2 microns. However, in the process of manufacturing the substrate or the reconfigured circuit layer, the use of liquid or dry film materials as dielectric layers to increase the layer, coupled with the subsequent electroplating process, can easily cause the surface of the formed metal pads to be uneven, and thus make it impossible to smoothly assemble the micro LEDs or sub-millimeter LEDs transferred from the mass production on the metal pads of the substrate, thereby reducing the reliability of the product. Summary of the invention

[0003] The present invention is directed to a packaging structure having better structural reliability.

[0004] The present invention is also directed to a method for manufacturing a packaging structure, which is used to manufacture the above packaging structure and has a better process yield.

[0005] According to an embodiment of the present invention, a method for manufacturing a packaging structure includes the following steps. A carrier is provided, wherein the carrier has a surface. A copper foil layer is laminated on the surface of the carrier. The copper foil layer is subjected to a subtractive process to form a copper foil circuit layer on the carrier. The copper foil circuit layer exposes a portion of the surface of the carrier. A build-up structure layer is formed on the copper foil circuit layer and the surface of the carrier. The first surface of the copper foil circuit layer is flush with the second surface of the build-up structure layer. At least one electronic component is arranged on the build-up structure layer. A packaging colloid is formed to cover the electronic component and the build-up structure layer. The carrier is removed to expose the first surface of the copper foil circuit layer.

[0006] In the method for manufacturing a packaging structure according to an embodiment of the present invention, the carrier includes a substrate, a release film and an adhesive layer. The release film is disposed on the substrate. The adhesive layer is disposed on the release film and is located between the release film and the copper foil layer.

[0007] In the method for manufacturing the package structure according to the embodiment of the present invention, the step of removing the carrier includes: performing a laser removal process to remove the substrate to expose the release film, peeling off the release film to expose the adhesive layer, and performing an etching process to remove the adhesive layer to expose the first surface of the copper foil circuit layer.

[0008] In the method for manufacturing a package structure according to an embodiment of the present invention, the method for manufacturing a package structure further includes: forming a surface treatment layer on the first surface of the copper foil circuit layer.

[0009] In the method for manufacturing the package structure according to the embodiment of the present invention, the step of removing the carrier includes: performing a laser removal process to remove the substrate to expose the release film, peeling off the release film to expose the adhesive layer, and performing a laser drilling process to remove a portion of the adhesive layer to expose a portion of the first surface of the copper foil circuit layer.

[0010] In the method for manufacturing a package structure according to an embodiment of the present invention, the method for manufacturing a package structure further includes: forming a surface treatment layer on the first surface of the copper foil circuit layer exposed by the adhesive layer.

[0011] In the method for manufacturing a packaging structure according to an embodiment of the present invention, the build-up structure layer includes at least one insulating layer, at least one build-up circuit layer and at least one conductive hole. The insulating layer covers the copper foil circuit layer, the build-up circuit layer is arranged on the insulating layer, and the conductive hole penetrates the insulating layer and electrically connects the build-up circuit layer and the copper foil circuit layer.

[0012] In the method for manufacturing the packaging structure according to the embodiment of the present invention, before forming the packaging colloid, it also includes: forming a surface treatment layer on a third surface of the build-up structure layer opposite to the second surface, wherein the electronic component directly contacts the surface treatment layer.

[0013] In the manufacturing method of the packaging structure according to an embodiment of the present invention, the electronic components include at least one micro light emitting diode, at least one resistor, at least one capacitor, at least one driving integrated circuit (IC), at least one application processor (AP), at least one memory or at least one high performance computing (HPC) chip.

[0014] According to an embodiment of the present invention, a method for manufacturing a packaging structure includes the following steps. A first carrier is provided, the first carrier having a surface. A copper foil layer is laminated on the surface of the first carrier. A subtractive process is performed on the copper foil layer to form a copper foil circuit layer on the first carrier. The copper foil circuit layer exposes a portion of the surface of the first carrier. A build-up structure layer is formed on the copper foil circuit layer and the surface of the first carrier. The first surface of the copper foil circuit layer is aligned with the second surface of the build-up structure layer. A second carrier is provided on a third surface of the build-up structure layer relative to the second surface. After providing the second carrier, the first carrier is removed to expose the first surface of the copper foil circuit layer and the second surface of the build-up structure layer. At least one electronic component is configured on the first surface of the copper foil circuit layer. A packaging colloid is formed to cover the electronic component and the build-up structure layer. The second carrier is removed to expose the third surface of the build-up structure layer.

[0015] In the method for manufacturing a package structure according to an embodiment of the present invention, the first carrier includes a substrate, a release film and an adhesive layer. The release film is disposed on the substrate. The adhesive layer is disposed on the release film and is located between the release film and the copper foil layer.

[0016] In the method for manufacturing the package structure according to the embodiment of the present invention, after forming the build-up structure layer and before providing the second carrier, the method further includes: forming a surface treatment layer on the third surface of the build-up structure layer.

[0017] In the manufacturing method of the packaging structure according to the embodiment of the present invention, after removing the first carrier and before configuring the electronic components on the first surface of the copper foil circuit layer, it also includes: forming a surface treatment layer on the first surface of the copper foil circuit layer.

[0018] In the method for manufacturing a packaging structure according to an embodiment of the present invention, the build-up structure layer includes at least one insulating layer, at least one build-up circuit layer and at least one conductive hole. The insulating layer covers the copper foil circuit layer, the build-up circuit layer is arranged on the insulating layer, and the conductive hole penetrates the insulating layer and electrically connects the build-up circuit layer and the copper foil circuit layer.

[0019] In the manufacturing method of the packaging structure according to an embodiment of the present invention, the electronic components include at least one micro light emitting diode, at least one resistor, at least one capacitor, at least one driving integrated circuit (IC), at least one application processor (AP), at least one memory or at least one high performance computing (HPC) chip.

[0020] According to an embodiment of the present invention, a packaging structure includes a copper foil circuit layer, a build-up structure layer, at least one electronic component and a packaging colloid. The build-up structure layer is arranged on the copper foil circuit layer, wherein the first surface of the copper foil circuit layer is aligned with the second surface of the build-up structure layer. The electronic component is arranged on the build-up structure layer. The packaging colloid covers the electronic component and the build-up structure layer.

[0021] In the packaging structure according to an embodiment of the present invention, the packaging structure further includes an adhesive layer, a first surface treatment layer and a second surface treatment layer. The adhesive layer is disposed on the second surface of the build-up structure layer and exposes a portion of the copper foil circuit layer. The first surface treatment layer is disposed on a third surface of the build-up structure layer relative to the second surface. The electronic component directly contacts the first surface treatment layer. The second surface treatment layer is disposed on the copper foil circuit layer exposed by the adhesive layer.

[0022] In the packaging structure according to an embodiment of the present invention, the packaging structure further includes a first surface treatment layer and a second surface treatment layer. The first surface treatment layer is arranged on a third surface of the build-up structure layer relative to the second surface, wherein the electronic component directly contacts the first surface treatment layer. The second surface treatment layer is arranged on the first surface of the copper foil circuit layer.

[0023] In the packaging structure according to an embodiment of the present invention, the packaging structure further includes a first surface treatment layer and a second surface treatment layer. The first surface treatment layer is disposed on the first surface of the copper foil circuit layer, wherein the electronic component directly contacts the first surface treatment layer. The second surface treatment layer is disposed on a third surface of the build-up structure layer relative to the second surface.

[0024] In the packaging structure according to the embodiment of the present invention, the build-up structure layer includes at least one insulating layer, at least one build-up circuit layer and at least one conductive hole. The insulating layer covers the copper foil circuit layer, the build-up circuit layer is arranged on the insulating layer, and the conductive hole penetrates the insulating layer and electrically connects the build-up circuit layer and the copper foil circuit layer.

[0025] In the packaging structure according to the embodiment of the present invention, the orthographic projection of the electronic component on the build-up structure layer does not overlap the conductive via.

[0026] Based on the above, in the method for manufacturing the packaging structure of the present invention, the copper foil layer is first pressed onto the carrier, and then the copper foil layer is subjected to a subtractive process to form a copper foil circuit layer on the carrier, and then a build-up structure layer is formed on the copper foil circuit layer. By setting and manufacturing the copper foil circuit layer, the flatness of the build-up circuit layer is controlled, and the subsequent coplanar assembly pads are obtained, which can improve the yield of subsequent electronic components when docking with the build-up structure layer. In this way, the packaging structure of the present invention can have better structural reliability. In addition, the subtractive process has fewer steps, which is conducive to reducing production costs and simplifying process steps, and can achieve the advantage of the surface coplanarity of the copper foil circuit layer being less than 2 microns. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figures 1A to 1G is a cross-sectional schematic diagram of a method for manufacturing a packaging structure according to an embodiment of the present invention;

[0028] Figure 2 is a cross-sectional schematic diagram of a packaging structure according to an embodiment of the present invention;

[0029] FIG. 3A to FIG. 3D It is a cross-sectional schematic diagram of partial steps of a method for manufacturing a packaging structure according to another embodiment of the present invention.

[0030] Description of Reference Numerals

[0031] 10, 20: carrier board;

[0032] 11: surface;

[0033] 12: substrate;

[0034] 14: release film;

[0035] 16: adhesive layer;

[0036] 100a, 100b, 100c: packaging structure;

[0037] 110a: copper foil layer;

[0038] 110: copper foil circuit layer;

[0039] 111: first surface;

[0040] 120: build-up structure layer;

[0041] 121: second surface;

[0042] 122, 124: build-up circuit layer;

[0043] 125: insulating layer;

[0044] 123: third surface;

[0045] 126, 128: conductive holes;

[0046] 130, 150a, 150b, 160, 165: surface treatment layer;

[0047] 140: encapsulation colloid;

[0048] 145: adhesive layer;

[0049] 147: Open your mouth;

[0050] E1, E2, E3: electronic components. DETAILED DESCRIPTION

[0051] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0052] Figures 1A to 1G FIG. 1 is a cross-sectional schematic diagram of a method for manufacturing a packaging structure according to an embodiment of the present invention. Regarding the method for manufacturing the packaging structure of this embodiment, first, please refer to Figure 1A, providing a carrier 10, wherein the carrier 10 has a surface 11. In detail, the carrier 10 of the present embodiment includes a substrate 12, a release film 14 and an adhesive layer 16. The release film 14 is disposed on the substrate 12, and the adhesive layer 16 is disposed on the release film 14, wherein the release film 14 is located between the substrate 12 and the adhesive layer 16. Here, the carrier 10 is, for example, a glass substrate, a glass fiber (FR4) substrate, a BT resin substrate or a ceramic substrate. The adhesive layer 16 includes a surface 11, and the material of the adhesive layer 16 is, for example, ABF (Ajinomoto build-up film) resin, polyimide or epoxy resin, but is not limited thereto.

[0053] Next, please refer to Figure 1A , the copper foil layer 110a is laminated on the surface 11 of the carrier 10, wherein the adhesive layer 16 is located between the release film 14 and the copper foil layer 110a. That is, in this embodiment, the copper foil layer 110a is adhered to the carrier 10 through the adhesive layer 16.

[0054] Next, please refer to Figure 1B , the copper foil layer 110a is subjected to a subtractive process to form a copper foil circuit layer 110 on the carrier 10. At this time, the copper foil circuit layer 110 exposes a portion of the surface 11 of the carrier 10. The subtractive process is a method of selectively removing a portion of the copper foil on the surface of the copper clad laminate to obtain a conductive circuit pattern.

[0055] Next, please refer to Figure 1C , forming a build-up structure layer 120 on the copper foil circuit layer 110 and the surface 11 of the carrier 10. In detail, the build-up structure layer 120 includes at least one insulating layer (schematically showing two insulating layers 125), at least one build-up circuit layer (schematically showing two build-up circuit layers 122 and 124) and at least one conductive hole (schematically showing a plurality of conductive holes 126 and 128). The insulating layer 125 covers the copper foil circuit layer 110, and the build-up circuit layer 124 is disposed on the insulating layer 125. The conductive holes 126 and 128 penetrate the insulating layer 125, and the conductive hole 126 electrically connects the build-up circuit layer 122 and the copper foil circuit layer 110, and the conductive hole 126 electrically connects the build-up circuit layer 122 and the build-up circuit layer 124. In particular, the first surface 111 of the copper foil circuit layer 110 is flush with the second surface 121 of the build-up structure layer 120. Here, the insulating layer 125 is, for example, Ajinomoto build-up film (ABF) resin, polyimide, or epoxy resin, but is not limited thereto.

[0056] Next, please refer to Figure 1C, a surface treatment layer 130 is formed on the third surface 123 of the build-up structure layer 120 opposite to the second surface 121 to protect the build-up circuit layer 124 from oxidation. Here, the material of the surface treatment layer 130 is, for example, a nickel layer, a gold layer, a silver layer, or a nickel-palladium-gold layer, but is not limited thereto.

[0057] Next, please refer to Figure 1D , at least one electronic component (schematically showing three electronic components E1, E2, E3) is configured on the build-up structure layer 120, wherein the electronic components E1, E2, E3 directly contact the surface treatment layer 130. The electronic components E1, E2, E3 are configured by mass transfer, so that the electronic components E1, E2, E3 are bonded to the build-up circuit layer 124 of the build-up structure layer 120. Here, the electronic components E1, E2, E3 are, for example, micro light emitting diodes, but not limited thereto. In other embodiments, the electronic components E1, E2, E3 may also be resistors, capacitors, driver integrated circuits (ICs), application program processors (APs), memories, or high performance computing (HPC) chips, but not limited thereto.

[0058] Next, please refer to Figure 1D , forming a packaging colloid 140 to cover the electronic components E1 , E2 , E3 , the build-up structure layer 120 and the surface treatment layer 130 .

[0059] Next, please refer to Figure 1E , a laser removal process is performed to remove the substrate 12 and expose the release film 14. Next, please refer to Figure 1E and Figure 1F , peel off the release film 14 to expose the adhesive layer 16. Figure 1G , a laser drilling process is performed to remove a portion of the adhesive layer 16 to form an adhesive layer 145 having an opening 147 , and the opening 147 exposes a portion of the first surface 111 of the copper foil circuit layer 110 .

[0060] Finally, please refer to Figure 1G , a surface treatment layer 150a is formed on the first surface 111 of the copper foil circuit layer 110 exposed by the adhesive layer 145 to protect the copper foil circuit layer 110 exposed by the opening 147 from oxidation. Here, the material of the surface treatment layer 150a is, for example, a nickel layer, a gold layer, a silver layer, or a nickel-palladium-gold layer, but is not limited thereto. At this point, the manufacturing of the package structure 100a has been completed.

[0061] In terms of structure, please refer to Figure 1GThe package structure 100a includes a copper foil circuit layer 110, a build-up structure layer 120, electronic components E1, E2, E3, and a packaging colloid 140. The build-up structure layer 120 is disposed on the copper foil circuit layer 110, wherein the first surface 111 of the copper foil circuit layer 110 is aligned with the second surface 121 of the build-up structure layer 120. The electronic components E1, E2, E3 are disposed on the build-up structure layer 120, and the packaging colloid 140 covers the electronic components E1, E2, E3 and the build-up structure layer 120. The build-up structure layer 120 includes an insulating layer 125, build-up circuit layers 122, 124, and conductive vias 126, 128. The insulating layer 125 covers the copper foil circuit layer 110 . The build-up circuit layer 124 is disposed on the insulating layer 125 . The conductive vias 126 , 128 penetrate the insulating layer 124 and electrically connect the build-up circuit layers 122 , 124 and the copper foil circuit layer 110 .

[0062] In addition, the package structure 100a of the present embodiment further includes an adhesive layer 145, a surface treatment layer 130, and a surface treatment layer 150a. The adhesive layer 145 is disposed on the second surface 121 of the build-up structure layer 120, and exposes a portion of the copper foil circuit layer 110. The surface treatment layer 130 is disposed on the third surface 123 of the build-up structure layer 120 relative to the second surface 121, and the electronic components E1, E2, and E3 directly contact the surface treatment layer 130. The surface treatment layer 150a is disposed on the copper foil circuit layer 110 exposed by the adhesive layer 145. Here, the surface treatment layers 130 and 150a can be used to protect the build-up circuit layer 124 and the copper foil circuit layer 110 to prevent oxidation, wherein the material of the surface treatment layers 130 and 150a is, for example, a nickel layer, a gold layer, a silver layer, or a nickel-palladium-gold layer, but is not limited thereto.

[0063] In short, since the present embodiment replaces the formation method of the existing reconfiguration circuit layer by electroplating copper by semi-additive process (SPA) or modified semi-additive process (MSAP) by laminating the copper foil layer 110a and the subtractive process, the uniformity of the copper thickness during circuit production can be increased, and since the subtractive process has fewer steps, it has a relatively lower cost and can simplify the production process, and can achieve the ability of the copper foil circuit layer 110 to have good flatness (less than 2 microns). In addition, through the setting and production of this copper foil circuit layer 110, the flatness of the subsequent build-up structure layer 120 formed thereon can be controlled, and the subsequent coplanar assembly pads can be obtained, which can improve the yield of the subsequent electronic components E1, E2, E3 when docking with the build-up structure layer 120. In this way, the packaging structure 100a of the present embodiment can have better structural reliability.

[0064] It must be noted that the following embodiments use the same component numbers and some contents of the previous embodiments, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the previous embodiments, and the following embodiments will not be repeated.

[0065] Figure 2 is a cross-sectional schematic diagram of a packaging structure according to an embodiment of the present invention. Figure 1G and Figure 2 The package structure of this embodiment is similar to the above package structure. The difference between the two is that: this embodiment does not have an adhesive layer 145, and in order to have better coplanarity, the orthographic projections of the electronic components E1, E2, and E3 of this embodiment on the build-up structure layer 120 do not overlap with the conductive holes 126 and 128. In detail, the surface treatment layer 150b is disposed on the first surface 111 of the copper foil circuit layer 110 and completely covers the entire first surface 111. For the process, please also refer to Figure 1F and Figure 2 After peeling off the release film 14 to expose the adhesive layer 16, an etching process is performed to remove the adhesive layer 16 and expose the first surface 111 of the copper foil circuit layer 110. Here, the etching process is, for example, chemical etching or plasma etching. At this point, the carrier 10 has been completely removed to expose the entire first surface 111 of the copper foil circuit layer 110. Please refer to Figure 2 , a surface treatment layer 150b is formed on the first surface 111 of the copper foil circuit layer 110. So far, the manufacturing of the package structure 100b has been completed.

[0066] FIG. 3A to FIG. 3D is a cross-sectional schematic diagram of a partial step of a method for manufacturing a packaging structure according to another embodiment of the present invention. Figure 1C and Figure 3A The manufacturing method of the packaging structure of this embodiment is similar to the manufacturing method of the packaging structure described above, and the difference between the two is that: in this embodiment, after forming the surface treatment layer 160 on the third surface 123 of the build-up structure layer 120 relative to the second surface 121, a carrier 20 is provided on the surface treatment layer 160 located on the third surface 123 of the build-up structure layer 120.

[0067] Next, please refer to Figure 3A and Figure 3B After providing the carrier 20 , the carrier 10 is removed and the carrier 20 is turned so that the carrier 20 carries the copper foil circuit layer 110 and the build-up structure layer 120 , so as to expose the first surface 111 of the copper foil circuit layer 110 and the second surface 121 of the build-up structure layer 120 .

[0068] Next, please refer to Figure 3B, a surface treatment layer 165 is formed on the first surface 111 of the copper foil circuit layer 110 to prevent oxidation, wherein the material of the surface treatment layer 165 is, for example, a nickel layer, a gold layer, a silver layer or a nickel-palladium-gold layer, but is not limited thereto.

[0069] Afterwards, please refer to Figure 3C , electronic components E1, E2, E3 are disposed on the first surface 111 of the copper foil circuit layer 110. Next, a packaging colloid 140 is formed to cover the electronic components E1, E2, E3, the build-up structure layer 120 and the surface treatment layer 165.

[0070] Finally, please refer to Figure 3D , the carrier 20 is removed to expose the surface treatment layer 160 on the third surface 123 of the build-up structure layer 120. At this time, the build-up circuit layer 124 of the build-up structure layer 120 protrudes from the insulating layer 125, and the surface treatment layer 160 is formed on the build-up circuit layer 124. At this point, the manufacturing of the package structure 100c has been completed.

[0071] In summary, in the method for manufacturing the packaging structure of the present invention, a copper foil layer is first pressed onto a carrier, and then the copper foil layer is subjected to a subtractive process to form a copper foil circuit layer on the carrier, and then a build-up structural layer is formed on the copper foil circuit layer. By setting and manufacturing the copper foil circuit layer, the flatness of the build-up circuit layer is controlled, and the subsequent coplanar assembly pads are obtained, which can improve the yield of subsequent electronic components when docking with the build-up structural layer. In this way, the packaging structure of the present invention can have better structural reliability. In addition, the subtractive process has fewer steps, which is conducive to reducing production costs and simplifying process steps, and can achieve the advantage of the surface coplanarity of the copper foil circuit layer being less than 2 microns.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a packaging structure, characterized in that: include: providing a carrier having a surface; Laminating a copper foil layer on the surface of the carrier board; Performing a subtractive process on the copper foil layer to form a copper foil circuit layer on the carrier, wherein the copper foil circuit layer exposes a portion of the surface of the carrier; Forming a build-up structure layer on the copper foil circuit layer and directly on the surface of the carrier, wherein the first surface of the copper foil circuit layer is flush with the second surface of the build-up structure layer and the surface of the carrier; Disposing at least one electronic component on the build-up structure layer; forming a surface treatment layer on a third surface of the build-up structure layer opposite to the second surface, wherein the at least one electronic component directly contacts the surface treatment layer; Forming a packaging colloid to cover the at least one electronic component and the build-up structure layer; as well as The carrier board is removed to expose the first surface of the copper foil circuit layer.

2. The method for manufacturing a packaging structure according to claim 1, characterized in that: The carrier board comprises: Base material; A release film is disposed on the substrate; and The adhesive layer is disposed on the release film and located between the release film and the copper foil layer.

3. The method for manufacturing a packaging structure according to claim 2, characterized in that: The step of removing the carrier board comprises: Performing a laser removal process to remove the substrate and expose the release film; peeling off the release film to expose the adhesive layer; and An etching process is performed to remove the adhesive layer to expose the first surface of the copper foil circuit layer.

4. The method for manufacturing a packaging structure according to claim 3, characterized in that: Also includes: A surface treatment layer is formed on the first surface of the copper foil circuit layer.

5. The method for manufacturing a packaging structure according to claim 2, characterized in that: The step of removing the carrier board comprises: Performing a laser removal process to remove the substrate and expose the release film; peeling off the release film to expose the adhesive layer; and A laser drilling process is performed to remove a portion of the adhesive layer to expose a portion of the first surface of the copper foil circuit layer.

6. The method for manufacturing a packaging structure according to claim 5, characterized in that: Also includes: A surface treatment layer is formed on the first surface of the copper foil circuit layer exposed by the adhesive layer.

7. The method for manufacturing a packaging structure according to claim 1, characterized in that: The build-up structure layer includes at least one insulating layer, at least one build-up circuit layer and at least one conductive hole, the at least one insulating layer covers the copper foil circuit layer, the at least one build-up circuit layer is configured on the at least one insulating layer, and the at least one conductive hole penetrates the at least one insulating layer and electrically connects the at least one build-up circuit layer and the copper foil circuit layer.

8. The method for manufacturing a packaging structure according to claim 1, characterized in that: The at least one electronic component includes at least one micro light emitting diode, at least one resistor, at least one capacitor, at least one driving integrated circuit, at least one application processor, at least one memory or at least one high performance computing chip.

9. A method for manufacturing a packaging structure, characterized in that: include: Providing a first carrier having a surface; Laminating a copper foil layer on the surface of the first carrier board; Performing a subtractive process on the copper foil layer to form a copper foil circuit layer on the first carrier, wherein the copper foil circuit layer exposes a portion of the surface of the first carrier; Forming a build-up structure layer on the copper foil circuit layer and the surface of the first carrier, wherein the first surface of the copper foil circuit layer is flush with the second surface of the build-up structure layer; Providing a second carrier on a third surface of the build-up structure layer opposite to the second surface; Removing the first carrier after providing the second carrier to expose the first surface of the copper foil circuit layer and the second surface of the build-up structure layer; Disposing at least one electronic component on the first surface of the copper foil circuit layer; Forming a packaging colloid to cover the at least one electronic component and the build-up structure layer; as well as The second carrier is removed to expose the third surface of the build-up structure layer.

10. The method for manufacturing a packaging structure according to claim 9, characterized in that: The first carrier board comprises: Base material; A release film is disposed on the substrate; and The adhesive layer is disposed on the release film and located between the release film and the copper foil layer.

11. The method for manufacturing a packaging structure according to claim 9, characterized in that: After forming the build-up structure layer and before providing the second carrier, the method further includes: A surface treatment layer is formed on the third surface of the build-up structure layer.

12. The method for manufacturing a packaging structure according to claim 9, characterized in that: After removing the first carrier board and before configuring the at least one electronic component on the first surface of the copper foil circuit layer, the method further includes: A surface treatment layer is formed on the first surface of the copper foil circuit layer.

13. The method for manufacturing a packaging structure according to claim 9, characterized in that: The build-up structure layer includes at least one insulating layer, at least one build-up circuit layer and at least one conductive hole, the at least one insulating layer covers the copper foil circuit layer, the at least one build-up circuit layer is configured on the at least one insulating layer, and the at least one conductive hole penetrates the at least one insulating layer and electrically connects the at least one build-up circuit layer and the copper foil circuit layer.

14. The method for manufacturing a packaging structure according to claim 9, characterized in that: The at least one electronic component includes at least one micro light emitting diode, at least one resistor, at least one capacitor, at least one driving integrated circuit, at least one application processor, at least one memory or at least one high performance computing chip.

15. A packaging structure, characterized in that: include: Copper foil circuit layer; A build-up structure layer is disposed on the copper foil circuit layer and includes at least one insulating layer, wherein a first surface of the copper foil circuit layer is flush with a second surface of the build-up structure layer, and the at least one insulating layer covers the copper foil circuit layer, wherein a first surface treatment layer is disposed on a third surface of the build-up structure layer relative to the second surface; At least one electronic component is disposed on the build-up structure layer; A packaging colloid covering the at least one electronic component and the build-up structure layer; as well as The second surface treatment layer is disposed on the first surface of the copper foil circuit layer.

16. The packaging structure according to claim 15, characterized in that: Also includes: An adhesive layer is disposed on the second surface of the build-up structure layer and exposes a portion of the copper foil circuit layer; wherein the at least one electronic component directly contacts the first surface treatment layer; as well as The second surface treatment layer is disposed on the copper foil circuit layer exposed by the adhesive layer.

17. The packaging structure according to claim 15, characterized in that: The at least one electronic component directly contacts the first surface treatment layer.

18. The packaging structure according to claim 15, characterized in that: The at least one electronic component directly contacts the second surface treatment layer.

19. The packaging structure according to claim 15, characterized in that: The build-up structure layer includes at least one build-up circuit layer and at least one conductive hole. The at least one build-up circuit layer is configured on the at least one insulating layer, and the at least one conductive hole penetrates the at least one insulating layer and electrically connects the at least one build-up circuit layer and the copper foil circuit layer.

20. The packaging structure according to claim 19, characterized in that: The orthographic projection of the at least one electronic component on the build-up structure layer does not overlap the at least one conductive hole.

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