A phase-change memory cell and its fabrication method

Abstract

This invention discloses a phase-change memory (PCM) cell and its fabrication method. The PCM cell, from bottom to top, includes: a first electrode, a PCM unit, and a second electrode. The PCM unit is a vertically arranged cylindrical structure, which includes, from the inside out, a select device layer, a barrier layer, and a PCM material layer connected sequentially. Multiple first electrodes are present and connected to the PCM material layers. The select device layer is connected to the second electrode and includes a vertically arranged two-dimensional crystal diode layer. This invention achieves storage by forming a structure where multiple phase-change resistors share a single select device. The use of two-dimensional crystal diodes to form the select device effectively reduces device power consumption and ensures compatibility with standard CMOS process lines, thereby reducing production costs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a phase-change memory cell and its preparation method. Background Technology

[0002] Small cell size, high performance, and low power consumption have always been the goals pursued in memory device development. However, as process nodes continue to shrink, transistors, due to their use of three-dimensional devices such as FinFETs, are no longer compatible with some existing embedded memory devices. Furthermore, the emergence of new information technologies such as big data, the Internet of Things, cloud computing, and artificial intelligence has placed high demands on memory devices for computing power, which existing DRAM and NAND flash memory cannot meet. Therefore, new memory technologies, such as phase-change memory, are gaining increasing popularity.

[0003] refer to Figure 1 Existing phase-change memory cells, taking Intel's 3DX-point technology as an example, consist from bottom to top of a bottom electrode 01, a select device layer 02, a barrier layer 03, a phase-change material layer 04, and a top electrode 05. Furthermore, each phase-change unit is composed of a select device S and a phase-change resistor R, forming a 1S1R structure.

[0004] Figure 1 The 3DX-point technology shown employs a vertical stacking technique of two phase-change cells to form the memory cell. However, this structure has two main problems: First, because the phase-change material layer 04 in the first phase-change cell is highly temperature-sensitive, the thermal budget for fabricating the second phase-change cell is very limited, requiring a temperature below 350°C. This places high demands on the material selection and fabrication process for both the device layer 02 and the phase-change material layer 04, and also affects the device's performance and yield. Second, the bidirectional threshold voltage of the 3DX-point bidirectional threshold switch is relatively high, typically 3-5V, resulting in high power consumption of the phase-change cell. Furthermore, the materials used in the bidirectional threshold switch often contain toxic substances such as As or Se, requiring the deposition equipment to be equipped with special protective devices, thus increasing the cost of large-scale production and compatibility with CMOS production lines.

[0005] Therefore, it is necessary to design a novel phase-change memory cell and its fabrication method to solve the above-mentioned problems caused by insufficient technology. Summary of the Invention

[0006] The purpose of this invention is to overcome the above-mentioned defects in the prior art and provide a phase change memory cell and its fabrication method to improve the storage density of the phase change memory cell and improve device performance.

[0007] To achieve the above objectives, the technical solution of the present invention is as follows:

[0008] The present invention provides a phase change memory cell, comprising, from bottom to top: a first electrode, a phase change unit, and a second electrode. The phase change unit is a vertically arranged cylindrical structure, and the cylindrical structure includes, from the inside out, a selection device layer, a blocking layer, and a phase change material layer connected in sequence. There are multiple first electrodes, which are respectively connected to the phase change material layer. The selection device layer is connected to the second electrode, and the selection device layer includes a vertically arranged two-dimensional crystal diode layer.

[0009] Furthermore, the two-dimensional crystal diode layer includes a two-dimensional crystal PN diode layer, which is configured to be connected to a two-dimensional crystal material layer having N-type semiconductor properties and a two-dimensional crystal material layer having P-type semiconductor properties, and the second electrode is connected to the two-dimensional crystal material layer having P-type semiconductor properties.

[0010] Furthermore, the two-dimensional crystal diode layer includes a two-dimensional crystal Schottky diode layer configured to be connected to a two-dimensional crystal material layer with semiconductor properties and a two-dimensional crystal material layer with metallic properties, wherein the second electrode is connected to the two-dimensional crystal material layer with metallic properties.

[0011] Furthermore, the selection device layer also includes a conductor material layer connected to the inside of the two-dimensional crystal diode layer, and the second electrode is connected to the conductor material layer.

[0012] Furthermore, the first electrode includes a bottom electrode and a heating electrode connected to the bottom electrode. The lower end of the heating electrode is connected to the upper end of the bottom electrode, and the upper end of the heating electrode is connected to the lower end of the phase change material layer.

[0013] This invention also provides a method for fabricating a phase-change memory cell, comprising the following steps:

[0014] S01: A substrate is provided, a first dielectric layer is deposited on the substrate, and a plurality of first electrodes are formed in the substrate and the first dielectric layer;

[0015] S02: Deposit a second dielectric layer on the first dielectric layer, and form a through first groove structure in the second dielectric layer corresponding to each of the first electrode positions;

[0016] S03: A phase change material layer and a barrier layer are sequentially formed on the sidewall surface of the first groove, thereby forming a second groove in the first groove within the barrier layer, and connecting the phase change material layer to each of the first electrodes;

[0017] S04: A selection device layer is formed in the second groove, and the second groove is filled; wherein the formed selection device layer includes a two-dimensional crystal diode layer;

[0018] S05: Remove excess phase change material layer, barrier layer and selector layer material outside the first groove to form a columnar phase change unit in the first groove;

[0019] S06: Deposit a third dielectric layer on the second dielectric layer, and form a second electrode in the third dielectric layer that connects to the selection device layer.

[0020] Further, in step S04, when forming the two-dimensional crystal diode layer, a two-dimensional crystal material layer with N-type semiconductor properties and a two-dimensional crystal material layer with P-type semiconductor properties are sequentially formed on the sidewall surface of the second groove, thereby forming a two-dimensional crystal PN diode layer; in step S06, the formed second electrode is connected to the two-dimensional crystal material layer with P-type semiconductor properties.

[0021] Further, in step S04, when forming the two-dimensional crystal diode layer, a two-dimensional crystal material layer with semiconductor properties and a two-dimensional crystal material layer with metallic properties are sequentially formed on the sidewall surface of the second groove, thereby forming a two-dimensional crystal Schottky diode layer; in step S06, the formed second electrode is connected to the two-dimensional crystal material layer with metallic properties.

[0022] Further, in step S04, when forming the selection device layer, the two-dimensional crystal diode layer is first formed on the sidewall surface of the second groove, and then a conductor material layer is formed inside the two-dimensional crystal diode layer; in step S06, the formed second electrode is connected only to the conductor material layer.

[0023] Further, in step S01, forming a plurality of first electrodes in the substrate and the first dielectric layer includes: forming a plurality of bottom electrodes in the substrate and the first dielectric layer, and further forming a plurality of first heating electrodes corresponding to and connected to the bottom electrodes on the bottom electrodes; in step S03, connecting the formed phase change material layer to each of the first heating electrodes.

[0024] As can be seen from the above technical solution, this invention combines cylindrical phase-change units with multiple first electrodes to form a structure in which multiple phase-change resistors R share a single selection device S, i.e., a 1SnR structure, where n is the number of phase-change resistors. The tops of the multiple first electrodes are connected to the outermost phase-change material layer of the same cylindrical phase-change unit, and the first electrodes can be connected to different metal interconnect layers. Since the 1SnR structure of this invention eliminates n-1 selectors compared to the traditional 1S1R structure, and different phase-change resistors can be connected to different metal interconnect layers through their respective first electrodes, the horizontal area of ​​the chip is not increased, thus achieving storage. Secondly, the selection device uses a two-dimensional transistor, which has a low threshold voltage, effectively reducing device power consumption. Furthermore, the material used in the two-dimensional transistor layer does not contain toxic elements, is environmentally friendly, and is compatible with standard CMOS process lines, thereby overcoming the problems existing in the previous use of bidirectional threshold switches and reducing production costs. Furthermore, the phase change unit is fabricated using groove filling and chemical mechanical polishing to form a cylindrical annular nested structure. Since the phase change material layers are all crystalline, only the phase change region in contact with the first electrode undergoes a phase change during device operation. Moreover, the phase change material on the outer side of the cylindrical structure is very thin, thus significantly reducing the volume of the phase change operation region and lowering device power consumption. Additionally, the first electrode can include a heating electrode with a sidewall structure. By connecting the heating electrode to the phase change material layer and utilizing its thin thickness, a higher current density can be generated, thereby improving heating efficiency and further reducing device power consumption. In summary, this invention effectively reduces device power consumption and achieves storage. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of a traditional phase-change memory cell.

[0026] Figure 2 This is a schematic diagram of the structure of a phase-change memory cell according to the first embodiment of the present invention.

[0027] Figure 3 It is the preparation Figure 2 The diagram shows the corresponding cross-sectional and top views of the structure obtained after depositing the first dielectric layer and bottom electrode on the substrate.

[0028] Figure 4 Is Figure 3 The diagram shows the corresponding cross-sectional and top views of the structure obtained after depositing the fourth dielectric layer and grooves on the structure shown.

[0029] Figure 5 Is Figure 4 The diagram shows the corresponding cross-sectional view and top view of the structure obtained after depositing a heating electrode on the structure shown.

[0030] Figure 6 Is Figure 5 The diagram shows the corresponding cross-sectional and top views of the structure obtained after depositing the second dielectric layer and the first groove on the structure shown.

[0031] Figure 7 Is Figure 6 The diagram shows the corresponding cross-sectional and top views of the structure obtained after depositing a phase change material layer and a barrier layer on the structure shown.

[0032] Figure 8 Is Figure 7 The diagram shows the corresponding cross-sectional and top views of the structure obtained after depositing the selective device layer on the structure shown.

[0033] Figure 9 Is Figure 8 The diagram shows the corresponding cross-sectional and top views of the structure obtained after chemical mechanical polishing to form phase change units.

[0034] Figure 10 This is a schematic diagram of the phase change operation region of the phase change material layer.

[0035] Figure 11 This is a schematic diagram of the structure of a phase-change memory cell according to the second embodiment of the present invention.

[0036] Figure 12 It is the preparation Figure 11 The top view of the structure shown is obtained after the first dielectric layer and the bottom electrode are deposited on the substrate.

[0037] Figure 13 yes Figure 12 The structure shown is a cross-sectional view along the X-ray.

[0038] Figure 14 yes Figure 12 The structure shown is a cross-sectional view along the Y-line;

[0039] Figure 15 Is Figure 12 A top view of the structure obtained after depositing a fourth dielectric layer and grooves on the structure shown;

[0040] Figure 16 yes Figure 15 The structure shown is a cross-sectional view along the X-ray.

[0041] Figure 17 Is Figure 15 A top view of the structure obtained after depositing a heating electrode onto the structure shown;

[0042] Figure 18 yes Figure 17 The structure shown is a cross-sectional view along the X-ray.

[0043] Figure 19 Is Figure 17 A top view of the structure obtained after depositing a second dielectric layer and a first groove on the structure shown;

[0044] Figure 20 yes Figure 19 The structure shown is a cross-sectional view along the X-ray.

[0045] Figure 21 Is Figure 19 A top view of the structure obtained after depositing a phase change material layer and a barrier layer on the structure shown;

[0046] Figure 22 yes Figure 21 The structure shown is a cross-sectional view along the X-ray.

[0047] Figure 23 Is Figure 21 A top view of the structure obtained after depositing a selective device layer on the structure shown;

[0048] Figure 24 yes Figure 23 The structure shown is a cross-sectional view along the X-ray.

[0049] Figure 25 Is Figure 23 A top view of the structure obtained after chemical mechanical polishing to form phase change units;

[0050] Figure 26 yes Figure 25 The structure shown is a cross-sectional view along the X-ray.

[0051] Figure 27 Is Figure 25 A top view of the structure obtained after depositing the third dielectric layer and the second electrode onto the structure shown;

[0052] Figure 28 Figure 27 The structure shown is a cross-sectional view along the X-ray.

[0053] Figure 29 This is a schematic diagram of the structure of a phase-change memory cell according to the third embodiment of the present invention. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0055] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0056] A phase-change memory cell of the present invention, referenced Figure 2 From bottom to top, it includes: a first electrode 103, a phase change unit 114, and a second electrode 116. The phase change unit 114 is a vertically arranged cylindrical structure; the cylindrical structure includes, from the inside to the outside, a selection device layer 111, a barrier layer 110, and a phase change material layer 109 connected in sequence. Multiple first electrodes 103 are present and connected to the phase change material layer 109 respectively; the selection device layer 111 is correspondingly connected to the second electrode 116. The selection device layer 111 includes a vertically arranged two-dimensional crystal diode layer.

[0057] A phase-change memory cell can be fabricated on a substrate 101. One or more dielectric layers can be disposed on the substrate 101, for example, a first dielectric layer 102, a second dielectric layer 107, and a third dielectric layer 115; a fourth dielectric layer 104 can also be disposed between the first dielectric layer 102 and the second dielectric layer 107, and a fifth dielectric layer can be disposed on the third dielectric layer 115. The fourth dielectric layer 104 can be considered an extension of the first dielectric layer 102, and the fifth dielectric layer can be considered an extension of the third dielectric layer 115. The phase-change memory cell can be embedded within the aforementioned dielectric layers.

[0058] Substrate 101 may include semiconductor materials, such as silicon substrate, gallium arsenide substrate, germanium substrate, germanium silicon substrate, or fully depleted silicon-on-insulator substrate. Substrate 101 may also be an integrated circuit, including integrated circuits with gates such as transistors, diodes, etc.

[0059] In an optional embodiment, the first electrode 103 may include a bottom electrode 103a and a heating electrode 103b; the top of the bottom electrode 103a and the bottom of the heating electrode 103b are connected.

[0060] The bottom electrode 103a may be located in both the substrate 101 and the first dielectric layer 102. For example, the lower part of the bottom electrode 103a may be located in the substrate 101, while the upper part may be exposed on the surface of the substrate 101 and located in the first dielectric layer 102.

[0061] The bottom electrode 103a can adopt a structure with multiple through holes, such as the structure with two through holes shown in the figure. The two through holes can be symmetrically distributed on both sides of the phase change memory cell. The bottom electrode 103a can be made of tungsten electrode, but is not limited to this.

[0062] The phase change unit 114 may be located in the second dielectric layer 107, and from the inside out, it includes: a cylindrical selector layer 111, an annular barrier layer 110, and an annular phase change material layer 109. Preferably, the phase change unit 114 may include, from the inside out, a cylindrical selector layer 111, an annular barrier layer 110, and an annular phase change material layer 109.

[0063] Two heating electrodes 103b are disposed on the bottom electrode 103a and correspond to the bottom electrode 103a; the heating electrodes 103b can be disposed in the fourth dielectric layer 104. The heating electrodes 103b can adopt a fan-shaped (three-dimensional fan-shaped ring) structure, a cubic structure, an L-shaped structure, or a through-hole structure that is longitudinally disposed on the upper surface of the bottom electrode 103a. When an L-shaped structure is adopted, the horizontal bottom edge of the L-shaped structure is connected to the upper surface of the bottom electrode 103a, and the upper end of the vertical sidewall of the L-shaped structure is correspondingly connected to the lower end of the ring of the phase change material layer 109.

[0064] In this way, a higher current density can be generated using the heating electrode 103b with a smaller thickness, which significantly improves the heating efficiency and further reduces the power consumption of the device.

[0065] In this embodiment, two heating electrodes 103b in a fan-shaped structure are used (please refer to...). Figure 5 (For further understanding). The two heating electrodes 103b have their arc surfaces facing each other; preferably, the inner and outer sidewalls of the fan-shaped bottom surface of the heating electrode 103b are located within the upper surface region of the bottom electrode 103a. The fan-shaped top surface of each heating electrode 103b is correspondingly connected to the annular lower end surface of the annular phase change material layer 109 and is located within the annular lower end surface of the phase change material layer 109.

[0066] The second electrode 116 may include an upper top electrode 118 and a lower contact hole 117 connected together, with the contact hole 117 connecting to the selection device layer 111. The top electrode 118 may be a metal layer.

[0067] The lower end of the heating electrode 103b is connected only to the bottom electrode 103a, and the upper end of the heating electrode 103b is connected only to the outermost phase change material layer 109 of the cylindrical phase change unit 114; the contact hole 117 of the second electrode 116 is connected only to the innermost selector layer 111 of the cylindrical phase change unit 114.

[0068] Select device layer 111 employs a two-dimensional crystal diode layer. Replacing the OTS switch with a two-dimensional crystal diode offers advantages such as a low threshold voltage, effectively reducing device power consumption. Furthermore, the materials used in this layer do not contain toxic elements such as aspergillium, making it environmentally friendly and compatible with standard CMOS process lines, thus reducing production costs. Additionally, the material in select device layer 111 with its two-dimensional crystal diode layer does not undergo a phase transition during phase-change memory device operation.

[0069] In an optional embodiment, the device layer 111 may be a two-dimensional crystal PN diode layer, which includes a two-dimensional crystal material layer 112 having N-type semiconductor properties and a two-dimensional crystal material layer 113 having P-type semiconductor properties connected together. The material of the two-dimensional crystal material layer 112 having N-type semiconductor properties may be at least one of silylene, germanene, black phosphorus, tinene, triazine-based graphitic carbon nitride, or transition metal disulfides such as molybdenum disulfide, tungsten disulfide, and molybdenum diselenide; the material of the two-dimensional crystal material layer 113 having P-type semiconductor properties may be at least one of silylene, germanene, black phosphorus, tinene, and triazine-based graphitic carbon nitride.

[0070] In an optional embodiment, the device layer 111 may also be a two-dimensional crystal Schottky diode layer, which includes a two-dimensional crystal material layer 112 with semiconductor properties and a two-dimensional crystal material layer 113 with metallic properties connected together. The material of the two-dimensional crystal material layer 112 with semiconductor properties may be at least one of tungsten disulfide and molybdenum disulfide, molybdenum ditelluride, tantalum disulfide, tantalum ditelluride, niobium disulfide, and niobium ditelluride; the material of the two-dimensional crystal material layer 113 with metallic properties may be at least one of titanium disulfide, molybdenum disulfide, and tungsten ditelluride.

[0071] In the above embodiments, the contact hole 117 of the second electrode 116 is only connected to the upper end of the two-dimensional crystal material layer 113 with P-type semiconductor properties or the two-dimensional crystal material layer 113 with metallic properties in the selection device layer 111.

[0072] The barrier layer 110 material includes a conductive material with high thermal and electrical conductivity and stable chemical properties. It will not chemically react with the material of the selective device layer 111 or the phase change material layer 109, nor will element diffusion occur. It prevents mutual reactions and element diffusion between the selective device layer 111 and the phase change material layer 109, and is beneficial for the growth of two-dimensional crystal materials. The barrier layer 110 material can be graphene, a carbon-containing compound, a two-dimensional material, or at least one of the following: Ti, Pt, W, Ta, Cu, WCN, WN, and TaN.

[0073] The initial state of the phase change material layer 109 is crystalline. The material of the phase change material layer 109 can be at least one of the following: GeTe-Sb2Te3 system, GeTe-SnTe system, Sb2Te system, In3SbTe2 system, Sb-doped system, GeTe-Sb2Te3 system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements, GeTe-SnTe system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements, Sb2Te system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements, In3SbTe2 system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements, and Sb-doped system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements.

[0074] The following detailed embodiments and accompanying drawings illustrate one preparation method of the present invention. Figure 2 The method of one phase-change memory cell will be further explained.

[0075] like Figures 3 to 9 As shown, a method for fabricating a phase-change memory cell according to the present invention may include the following steps:

[0076] S11: As Figure 3 As shown, to clearly illustrate the structure of the present invention, the upper figure shows a cross-sectional view and the lower figure shows a top view (the same below). A first dielectric layer 102 is deposited on the substrate 101, and two through-hole type bottom electrodes 103a are formed in the substrate 101 and the first dielectric layer 102.

[0077] The bottom electrode 103a can be positioned such that the lower half is located in the substrate 101 and the upper half is located in the first dielectric layer 102. In this embodiment, the bottom electrode 103a can be a tungsten electrode via with a diameter of 30–100 nm, which is 40 nm in this embodiment.

[0078] like Figure 4As shown, a fourth dielectric layer 104 is deposited on the first dielectric layer 102 and the bottom electrode 103a, and a through groove 105 structure is formed in the fourth dielectric layer 104 at the position corresponding to the bottom electrode 103a. From a top view, the groove 105 can be circular, elliptical, rectangular, or polygonal. In this embodiment, an annular groove 105 is formed in the fourth dielectric layer 104. The diameter of the groove 105 is slightly smaller than the sum of the diameters of the two bottom electrodes 103a and the distance between the two bottom electrodes 103a.

[0079] like Figure 5 As shown, a heating electrode 103b is formed on the inner wall surface of the groove 105, and the heating electrode 103b is connected to the bottom electrode 103a.

[0080] The heating electrode 103b can be at least one of a fan-shaped body, a through-hole, and a three-dimensional L-shaped sidewall structure. The heating electrode 103b thin film can be deposited using atomic layer deposition, chemical vapor deposition, or plasma-enhanced chemical vapor deposition.

[0081] In this embodiment, a thin film of heating electrode 103b is deposited on the sidewall of the groove 105 using plasma chemical vapor deposition (PCVD). The PCVD process involves deposition-etching-deposition-etching, allowing the heating electrode 103b film to be deposited only on the sidewall of the groove 105, with no film deposited at the bottom of the groove 105, resulting in a three-dimensional annular heating electrode 103b. Then, through photolithography and etching processes, the annular heating electrode 103b is divided into two fan-shaped heating electrodes 103b. Finally, by depositing a dielectric layer material in the groove 105 and performing polishing, two three-dimensional fan-shaped heating electrodes 103b are formed.

[0082] The heating electrode 103b can be made of TaN. The thickness of the heating electrode 103b, i.e. the difference between the outer and inner radii of the fan-shaped ring, can be 3 to 10 nm, and in this embodiment it is 6 nm.

[0083] S12: As Figure 6 As shown, a second dielectric layer 107 is deposited on the fourth dielectric layer 104 and the heating electrode 103b. A through-type first groove 108 structure is formed in the second dielectric layer 107 above the corresponding two bottom electrodes 103a. There is one first groove 108. The first groove 108 can be one of an elliptical cylinder, a cylinder, a cuboid, or a prism. In this embodiment, the first groove 108 is a cylindrical groove, and its diameter should match that of the groove 105 to ensure effective contact between the subsequently formed phase change material layer 109 and the heating electrode 103b.

[0084] S13: As Figure 7As shown, a three-dimensional annular phase change material layer 109 and a barrier layer 110 are sequentially formed on the sidewall surface of the first groove 108, and the phase change material layer 109 is connected to the heating electrode 103b.

[0085] In this embodiment, the phase change material layer 109 and the barrier layer 110 are annular.

[0086] The phase change material layer 109 can be deposited as a thin film by plasma chemical vapor deposition, that is, a three-dimensional annular thin film is deposited only on the sidewall of the first groove 108, the deposition temperature is 200 to 500°C, and the deposited phase change material is crystalline.

[0087] The barrier layer 110 can be deposited by plasma chemical vapor deposition, thus allowing it to be deposited in the same apparatus as the phase change material layer 109.

[0088] The top of the heating electrode 103b in the first electrode 103 is connected only to the outermost phase change material layer 109 of the cylindrical phase change unit 114.

[0089] In this embodiment, the phase change material layer 109 is made of, for example, C-doped GeSbTe, and its thickness can be 10-100 nm, such as 25 nm. The barrier layer 110 is made of, for example, graphene, and its thickness can be 3-15 nm, such as 5 nm. The phase change material layer 109 and the barrier layer 110 are deposited in the same device using plasma chemical vapor deposition to form annular phase change material layer 109 and barrier layer 110.

[0090] The plasma chemical vapor deposition method is a deposition-etching-deposition-etching method, which ensures that the barrier layer 110 and the phase change material layer 109 are deposited only on the sidewall of the first groove 108, making the phase change material layer 109 and the barrier layer 110 three-dimensional rings.

[0091] The phase change material was deposited at a temperature of 300℃, and the C-doped GeSbTe film after deposition was crystalline. Graphene, as the barrier layer, exhibited stable chemical properties and excellent electrical and thermal conductivity, which is beneficial for improving the performance of phase change memory devices.

[0092] In this embodiment, the inner diameter of the fan-shaped heating electrode 103b is larger than the inner diameter of the annular phase change material layer 109, and the outer diameter of the fan-shaped heating electrode 103b is smaller than the outer diameter of the annular phase change material layer 109. Therefore, the contact area between the two is equal to the fan-shaped surface area of ​​the fan-shaped heating electrode 103b. By utilizing the smaller fan-shaped surface area of ​​the fan-shaped heating electrode 103b, the contact area with the annular phase change material layer 109 can be reduced, thereby increasing heating efficiency and reducing power consumption.

[0093] Since the barrier layer 110 is formed only on the sidewall of the first groove 108, a second groove is formed in the first groove 108 inside the barrier layer 110.

[0094] S14: As Figure 8 As shown, a selectable device layer 111 material is deposited in a second groove within the barrier layer 110, and the second groove is filled. The selectable device layer 111 includes a two-dimensional crystal diode layer.

[0095] Device layer 111 can be either a two-dimensional crystal PN diode layer or a two-dimensional crystal Schottky diode layer.

[0096] Selective device layer 111 can be deposited using chemical vapor deposition or atomic layer deposition (ALD). The deposition process must ensure that the three-dimensional cylindrical selective device layer 111 is free of gaps and voids.

[0097] In this embodiment, the material for the selector layer 111 is deposited using chemical vapor deposition. The selector layer 111 is a two-dimensional crystal Schottky diode layer, wherein the two-dimensional crystal material layer 112 with semiconductor properties is MoS2, and the two-dimensional crystal material layer 113 with metallic properties is WTe2. The selector layer 111, composed of the two-dimensional crystal material layer 112 with semiconductor properties and the two-dimensional crystal material layer 113 with metallic properties, will not change during the operation of the phase change unit 114.

[0098] S15: As Figure 9 As shown, the excess material of the selector layer 111, barrier layer 110 and phase change material layer 109 outside the first groove 108 can be removed by chemical mechanical polishing, forming a columnar phase change unit 114 in the first groove 108.

[0099] The formed cylindrical phase change unit 114 comprises, from the inside out: a selection device layer 111, a barrier layer 110, and a phase change material layer 109. The cylindrical phase change unit 114 can be one of an elliptical cylinder, a cylinder, a cuboid, or a prism. The top of the heating electrode 103b is connected only to the outermost phase change material layer 109 of the cylindrical phase change unit 114, and the bottom of the heating electrode 103b is connected only to the bottom electrode 103a. The tops of the two heating electrodes 103b are connected only to the outermost phase change material layer 109 of the same cylindrical phase change unit 114, and the bottoms of each heating electrode 103b are connected to different bottom electrodes 103a in a one-to-one correspondence. Different bottom electrodes 103a can connect to different metal interconnect layers in the substrate 101. In this embodiment, the phase change unit 114 is cylindrical, consisting of, from the inside out, a selector layer 111 composed of a metallic WTe2 layer and a semiconductor MoS2 layer, a graphene barrier layer 110, and a C-doped Ge2Sb2Te5 phase change material layer 109. One phase change unit 114 is connected to the top of two three-dimensional fan-shaped heating electrodes 103b, forming a 1S2R structure, meaning that two phase change resistors share one selector.

[0100] S16: A third dielectric layer 115 is deposited on the second dielectric layer 107 and the phase change unit 114, and a second electrode 116 connecting the selection device layer 111 is formed in the third dielectric layer 115, forming as shown in the figure. Figure 2 The 1S2R phase change memory cell shown has a three-dimensional fan-shaped heating electrode 103b and a cylindrical phase change unit 114.

[0101] The formed second electrode 116 is connected only to the innermost selector layer 111 of the cylindrical phase transition unit 114. In this embodiment, the second electrode 116 is a connection structure between a contact hole 117 and a metal layer top electrode 118. The contact hole 117 is made of tungsten, and the metal layer top electrode 118 is made of copper. The tungsten contact hole 117 is connected only to the innermost WTe2 layer of the selector layer 111 in the cylindrical phase transition unit 114, which has metallic properties.

[0102] The phase-change memory cell disclosed in the above embodiments comprises, from bottom to top, two through-hole bottom electrodes 103a, two three-dimensional fan-shaped heating electrodes 103b, a cylindrical phase-change unit 114, and a second electrode 116. The phase-change unit 114 includes, from the inside out, a selector layer 111, a barrier layer 110, and a phase-change material layer 109. The selector layer 111 is a two-dimensional crystal Schottky diode layer, composed from the inside out of a two-dimensional crystal material layer 113 with metallic properties and a two-dimensional crystal material layer 112 with semiconductor properties. The top ends of the two heating electrodes 103b are connected to the outermost phase-change material layer 109 of the same cylindrical phase-change unit 114, and the bottom ends of the two heating electrodes 103b are connected to different bottom electrodes 103a, forming a structure where two phase-change resistors R1 and R2 share a single selector S, i.e., a 1S2R structure. Compared to the existing 1S1R structure, the 1S2R structure eliminates one selector. Different phase-change resistors can be connected to the bottom electrodes of different metal interconnect layers through their respective heating electrodes, thus not increasing the horizontal area of ​​the chip and achieving storage.

[0103] In addition, such as Figure 10 As shown, during the operation of the phase change device, only a portion of the phase change material above the heating electrode 103b undergoes a phase change in the phase change region. That is, the initial state of the phase change material layer 109 is crystalline. After the write operation, the phase change operation region 109a in the phase change material layer 109 changes from crystalline to amorphous, while the other regions 109b in the phase change material layer 109 remain crystalline.

[0104] Since the phase change material layer 109 film thickness can be only 10-100nm, the volume of the phase change operation region 109a and the required heat energy are greatly reduced, thereby reducing the power consumption of the device.

[0105] Furthermore, the heating electrode 103b, deposited with a three-dimensional fan-shaped sidewall, has a thickness of only 3-10 nm. This results in a higher current density and improved heating efficiency, further reducing device power consumption. Therefore, this phase-change memory unit not only achieves storage but also effectively reduces device power consumption.

[0106] In this embodiment, all dielectric layers are stacked together in the area outside the phase change memory unit 114. The materials of each dielectric layer can be the same or different, and the specific materials can be the dielectric layer materials in the prior art.

[0107] It is worth noting that, compared to previous bidirectional threshold switches containing toxic elements such as asphalt (As) as selection devices, this invention uses a two-dimensional crystal diode to form the selection device. Since it does not contain toxic elements, it has the advantages of being safer and more environmentally friendly. Furthermore, the performance of two-dimensional crystal diodes far surpasses that of existing silicon transistors, making them the most promising new type of transistor below advanced process nodes. Using two-dimensional crystal diodes as selection devices is more suitable for phase-change memories at advanced process nodes and below. In addition, two-dimensional crystal diodes have similar properties to barrier layers (typically graphene), resulting in very low contact resistance at the interface, which improves device performance and also offers better process compatibility.

[0108] It should also be noted that by using a conductive material as the barrier layer and incorporating a conductive material layer, this invention not only facilitates the growth of the two-dimensional crystal but also further reduces the contact resistance with the second electrode. Furthermore, by employing a process that grows the phase change material, barrier layer material, and two-dimensional crystal material in the same vacuum equipment, this invention effectively avoids contact between the two-dimensional crystal film and air, thereby improving the stability of the selected device's performance. In addition, this invention also utilizes some phase change materials with the same elemental composition as the two-dimensional crystal material, enabling the sharing of process equipment.

[0109] In another specific embodiment of the present invention, reference is made to... Figure 11 The phase-change memory cell of the present invention can also be built on a substrate 201. The substrate 201 can also be provided with one or more dielectric layers, such as a first dielectric layer 202, a second dielectric layer 207, a third dielectric layer 215 and a fourth dielectric layer 204; the phase-change memory cell can also be embedded in the above dielectric layers.

[0110] The substrate 201 may include semiconductor materials, such as a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, or a fully depleted silicon-on-insulator. The substrate 201 may also be an integrated circuit, including an integrated circuit with a gate, such as a transistor or diode. In this embodiment, the substrate 201 is a substrate having two metal interconnect layers, Metal1 and Metal2. The first electrode 203 may consist of a bottom electrode 203a and a heating electrode 203b.

[0111] The bottom electrode 203a can be located simultaneously in the substrate 201 and the first dielectric layer 202. For example, the lower portion of the bottom electrode 203a is located in the substrate 201, and the upper portion is exposed on the surface of the substrate 201 and located in the first dielectric layer 202. The bottom electrode 203a can adopt a structure with multiple through holes, such as a structure with six through holes (see reference). Figure 12 The top view shows through-holes Via1 to Via6; the six through-holes can form a symmetrically distributed hexagon and are located below the phase change memory cell. The bottom electrode 203a can be made of TiN electrode, but is not limited to this.

[0112] Among them, vias Via1, Via3 and Via5 in the six bottom electrodes 203a can be connected to the first metal interconnect layer Metal1 through the second metal interconnect layer Metal2, while vias Via2, Via4 and Via6 are only connected to the second metal interconnect layer. Figure 12 Cross-sectional views in the X and Y directions from the top view are shown separately, which more clearly illustrates the relationship between the bottom electrodes Via1 to Via6.

[0113] In this embodiment, the phase change unit 214 includes, from the inside out: a cubic columnar selector layer 211, a rectangular ring barrier layer 210 surrounding the selector layer 211, and a rectangular ring phase change material layer 209.

[0114] The heating electrode 203b adopts six vertical strip-shaped cubic structures respectively disposed on the upper surface of the corresponding bottom electrode 203a. The bottom edge of the strip structure of the heating electrode 203b is connected to the surface of the bottom electrode 203a, and the upper edges of the six strip structures are connected to the lower ends of the four sides of the rectangular annular phase change material layer 209, corresponding to the directions of the sides of the phase change material layer 209 (please refer to...). Figure 19 (Top view).

[0115] The second electrode 216 may include a connected upper metal layer top electrode and a lower contact hole, with the contact hole connected to the device selection layer 211.

[0116] In this configuration, the lower end of each heating electrode 203b is connected to only one corresponding bottom electrode 203a, the upper end of each heating electrode 203b is connected to only one corresponding side of the phase change material layer 209 located at the outermost edge of the cylindrical phase change unit 214, and the second electrode 216 is connected to only the selection device layer 211 located at the innermost edge of the cylindrical phase change unit 214.

[0117] Alternatively, the heating electrode can be a structure of six conductive through holes on the bottom electrode, filled with heating electrode material, with the upper and lower ends of the through holes respectively connected to the lower annular end of the phase change material layer and the upper surface of the bottom electrode. Alternatively, the heating electrode can be an L-shaped structure disposed on the bottom electrode; wherein the horizontal bottom edge of the L-shaped structure is connected to the surface of the bottom electrode, and the upper end of the vertical sidewall of the L-shaped structure is connected to the corresponding side of the lower annular end of the phase change material layer.

[0118] Device layer 211 is selected as a two-dimensional crystal diode layer. The material of device layer 111 is selected so that it will not undergo a phase transition during the operation of the phase change memory device.

[0119] The device layer 211 can be a two-dimensional crystal PN diode layer, which has a two-dimensional crystal material layer 212 with N-type semiconductor properties and a two-dimensional crystal material layer 213 with P-type semiconductor properties.

[0120] Alternatively, device layer 211 can also be a two-dimensional crystal Schottky diode, which has a two-dimensional crystal material layer 212 with semiconductor properties and a two-dimensional crystal material layer 213 with metallic properties.

[0121] Other aspects of the aforementioned phase-change memory unit can be found in [reference]. Figure 2 The structure shown in the first embodiment is understood and will not be described again.

[0122] The following detailed embodiments and accompanying drawings illustrate one preparation method of the present invention. Figure 11 The method of one phase-change memory cell will be further explained.

[0123] like Figures 12 to 28 As shown, a method for fabricating a phase-change memory cell according to the present invention may include the following steps:

[0124] S21: As Figures 12 to 14 A first dielectric layer 202 is deposited on a substrate 201, and a bottom electrode 203a is formed in the substrate 201 and the first dielectric layer 202.

[0125] In this embodiment, substrate 201 is a substrate 201 having two metal interconnect layers, Metal2 and Metal1. A first dielectric layer 202 is deposited on substrate 201, and a bottom electrode 203a is formed in the first dielectric layer 202. The lower half of the bottom electrode 203a is located in substrate 201 and connected to the second metal interconnect layer Metal2 in substrate 201. From the top view, the bottom electrode 203a consists of six vias Via1 to Via6, and the material of the bottom electrode 203a is TiN. Among them, vias Via1, Via3, and Via5 are connected to the first metal interconnect layer Metal1 through the second metal interconnect layer Metal2, while vias Via2, Via4, and Via6 are only connected to the second metal interconnect layer Metal2. The relationship between each bottom electrode Via1 to Via6 can be more clearly illustrated by the cross-sectional views in the X and Y directions.

[0126] like Figure 15 and Figure 16 As shown, a fourth dielectric layer 204 is deposited on the first dielectric layer 202 and the bottom electrode 203a, and a groove 205 is formed in the fourth dielectric layer 204.

[0127] From a top view, the groove 205 can be one of a circle, an ellipse, a rectangle, or a polygon. In this embodiment, a rectangular groove 205 is formed in the dielectric layer, and the four edges of the rectangular groove 205 intersect with the upper end face of one or two bottom electrodes 203a on the corresponding side in the vertical direction. For example, the top and bottom edges of the rectangular groove 205 intersect with through holes Via1 and Via4 respectively, the left side intersects with through holes Via2 and Via3 simultaneously, and the right side intersects with through holes Via5 and Via6 simultaneously.

[0128] like Figure 17 and Figure 18 As shown, six strip-shaped, e.g., cuboid-shaped heating electrodes 203b are formed in the fourth dielectric layer 204, with the lower end of each heating electrode 203b connected to a corresponding bottom electrode 203a. The heating electrode 203b film can be deposited using atomic layer deposition, chemical vapor deposition, or plasma chemical vapor deposition. In this embodiment, by depositing the film on the sidewall of the rectangular groove 205 using plasma chemical vapor deposition, the heating electrode 203b film can be deposited only on the sidewall of the rectangular groove 205, while no film is deposited at the bottom of the groove 205, resulting in a three-dimensional rectangular ring-shaped heating electrode 203b. Then, through photolithography and etching processes, the ring-shaped heating electrode 203b is divided into six rectangular strip heating electrodes 203b. Finally, through the deposition of the fourth dielectric layer 204 material and polishing processes, six three-dimensional rectangular heating electrodes 203b are formed. The heating electrodes 203b can be made of TiN material, with a TiN thickness (the difference between the outer and inner sides) of 2-8 nm.

[0129] S22: As Figure 19 and Figure 20 As shown, a second dielectric layer 207 is deposited on the fourth dielectric layer 204 and the heating electrode 203b, and a first groove 208 is formed in the second dielectric layer 204. The first groove 208 can be one of an elliptical cylinder, a cylinder, a cuboid, and a prism. In this embodiment, the first groove 208 is a rectangular groove, and its length in each direction should match that of the rectangular groove 205 to ensure effective contact between the subsequently formed phase change material layer 209 and the heating electrode 203b.

[0130] S23: As Figure 21 and Figure 22 As shown, a rectangular annular phase change material layer 209 and a barrier layer 210 are sequentially formed in the first groove 208. The phase change material layer 209 is then connected to the heating electrode 203b.

[0131] The phase change material layer 209 can be deposited as a thin film by plasma chemical vapor deposition, that is, a three-dimensional annular thin film is deposited only on the sidewall of the first groove 208, the deposition temperature is 200-500℃, and the deposited phase change material is crystalline.

[0132] The barrier layer 210 can also be deposited by plasma chemical vapor deposition, and can be deposited in the same equipment as the phase change material layer 209.

[0133] The top of the heating electrode 203b is connected only to the outermost phase change material layer 209 of the cylindrical phase change unit 214.

[0134] In this embodiment, the phase change material layer 209 is made of Sc. 0.2 The Sb₂Te₃ material has a thickness of 10-100 nm, for example, 15 nm. The barrier layer 210 is made of WCN and has a thickness of 3-15 nm, for example, 10 nm.

[0135] Plasma-chemical vapor deposition (PCVDC) is used to deposit phase change material (PCM) and barrier layer material in the same device, forming a rectangular annular PCM layer 209 and a barrier layer 210. This ensures that the barrier layer 210 and PCM layer 209 are deposited only on the sidewalls of the first groove 208, with no thin film deposition at the bottom, making the PCM layer 209 and barrier layer 210 a three-dimensional rectangular annular structure. The PCM deposition temperature is 300℃, and after deposition, Sc... 0.2 The Sb₂Te₃ thin film is crystalline. The WCN thin film, as a barrier layer, is chemically stable and can effectively prevent interdiffusion between the phase change material and the selective device layer material.

[0136] S24: As Figure 23 and Figure 24 As shown, the material of the selected device layer 211 continues to be deposited in the gap of the first groove 208 within the barrier layer 210, and the first groove 208 is filled.

[0137] Device layer 211 is selected as a two-dimensional crystal diode layer, which can be a two-dimensional crystal PN diode layer or a two-dimensional crystal Schottky diode layer. The material of device layer 111 is selected so that it will not undergo phase change during the operation of the phase change memory device.

[0138] The selective device layer 211 can be deposited using either chemical vapor deposition or atomic layer deposition (ALD). The deposition process must ensure that the three-dimensional cylindrical selective device layer 211 is free of gaps and voids.

[0139] In this embodiment, the material for the selector layer 211 is deposited using chemical vapor deposition. The selector layer 211 is a two-dimensional crystal PN diode layer, wherein the two-dimensional crystal material layer 212 with N-type semiconductor properties is WS2, and the two-dimensional crystal material layer 213 with P-type semiconductor properties is TiS2. The selector layer 211, composed of WS2 and TiS2, will not change during the operation of the phase change unit 214.

[0140] S25: As Figure 25 and Figure 26 As shown, excess material outside the first groove 208 is removed by chemical mechanical polishing to form a cuboid phase change unit 214. The formed cuboid phase change unit 214 includes, from the inside out: a selection device layer 211, a barrier layer 210, and a phase change material layer 209.

[0141] In this embodiment, the phase change unit 214 is a cubic column, consisting of TiS2 with P-type semiconductor properties, WS2 selector layer 211 with N-type semiconductor properties, WCN barrier layer 210, and Sc0.2Sb2Te3 phase change material layer 209 from the inside out.

[0142] S26: As Figure 27 and Figure 28 As shown, a third dielectric layer 215 is deposited on the second dielectric layer 207 and the phase change unit 214, and a second electrode 216 is formed in the third dielectric layer 215. The second electrode 216 is only connected to the innermost selector layer 211 of the cuboid phase change unit 214. The top of each heating electrode 203b is only connected to the outermost phase change material layer 209 of the same cylindrical phase change unit 214, and the bottom of each heating electrode 203b is connected to a corresponding bottom electrode 203a. Different bottom electrodes 203a can be connected to different metal interconnect layers.

[0143] In this embodiment, the second electrode 216 is a groove with a double damask structure, and the metal of the second electrode 216 is copper. The contact hole in the double damask structure is only connected to the innermost layer of the selector layer 211 in the cylindrical phase transition unit 214, which has P-type semiconductor properties, TiS2. The final result is as follows: Figure 29 The 1S6R phase change memory cell shown has six strip heating electrodes 203b and cubic columnar phase change units 214.

[0144] The phase-change memory cell disclosed in the above embodiments comprises, from bottom to top, six through-hole type bottom electrodes 203a, six corresponding strip-shaped heating electrodes 203b, a cylindrical phase-change unit 214, and a second electrode 216. The phase-change unit 214 is a cuboid and includes, from the inside out, a selector layer 211, a barrier layer 210, and a phase-change material layer 209. The top ends of the six heating electrodes 203b are connected to the outermost phase-change material layer 209 of the same cylindrical phase-change unit 214, and the bottom ends of the six heating electrodes 203b are connected to different bottom electrodes 203a, forming a 1S6R structure where six phase-change resistors R share a single selector S. Compared to the existing 1S1R structure, the 1S6R structure eliminates five selectors. In the bottom electrode 203a, vias Via1, Via3, and Via5 are connected to the first metal interconnect layer Metal1 via the second metal interconnect layer Metal2, while vias Via2, Via4, and Via6 are only connected to the second metal interconnect layer Metal2. Although an additional metal layer is added, the horizontal area of ​​the chip is not increased, thus enabling memory storage.

[0145] Alternatively, a through-hole structure can be formed in the fourth dielectric layer at the corresponding bottom electrode position, and heating electrode material can be filled in the through-hole to form a solid heating electrode. The upper and lower ends of the through-hole heating electrode are respectively connected to the lower annular end of the phase change material layer and the upper surface of the bottom electrode. Alternatively, an L-shaped heating electrode can be formed in the fourth dielectric layer at the corresponding bottom electrode position. This can include: depositing heating electrode material on the inner wall surface of the groove, patterning the heating electrode material, removing excess heating electrode material from the sidewalls and bottom surface of the groove, depositing dielectric layer material again in the groove to fill it, and then planarizing it to form the heating electrode.

[0146] As another alternative, see [reference] Figure 29The selection device layer 311 has a graphene or chemically stable conductor material layer 314 at its center, surrounded by a ring-shaped two-dimensional crystal diode layer. The phase change unit 315, from the inside out, includes a selection device layer 311 composed of the conductor material layer 314 and ring-shaped two-dimensional crystal diode layers 313 and 312, a barrier layer 310, and a phase change material layer 309. The second electrode 317 is only connected to the innermost conductor material layer 314 of the cuboid phase change unit 315. This further reduces the contact resistance between the two-dimensional crystal diode layers 313 and 312 and the second electrode 317. The tops of the six heating electrodes 303b are connected to the outermost phase change material layer 309 of the same cylindrical phase change unit 315, and the bottoms of the six heating electrodes 303b are connected to different bottom electrodes 303a in a one-to-one correspondence. Each pair of heating electrodes 303b and bottom electrodes 303a forms a first electrode 303, ultimately forming a 1S6R structure where six phase change resistors R share a single selection device S. The 1S6R structure is built on substrate 301 and can be embedded in multilayer dielectric layers 302, 304, 307 and 316.

[0147] A conductor material layer 314 is formed inside the two-dimensional crystal diode layers 313 and 312, which is beneficial to the growth of the two-dimensional crystal. The conductor material layer 314 has the characteristics of high thermal conductivity and electrical conductivity, as well as chemical stability at high temperature, which can further reduce the contact resistance between it and the second electrode 317.

[0148] Other aspects of the aforementioned phase-change memory unit and its fabrication method can be found in the above description. Figure 11 The structure of the second embodiment shown Figures 12-28 The preparation method is explained through examples and will not be repeated here.

[0149] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A phase change memory cell, comprising: From bottom to top, comprising: a first electrode, a phase change unit and a second electrode, the phase change unit is a longitudinally arranged columnar structure, the columnar structure comprises a selector device layer, a barrier layer and a phase change material layer connected in sequence from inside to outside; wherein the first electrode is multiple and respectively connected with the phase change material layer, the selector device layer is connected with the second electrode, the selector device layer comprises a longitudinally arranged two-dimensional crystal diode layer and a conductor material layer arranged in the inside of the two-dimensional crystal diode layer, and the second electrode is connected with the conductor material layer; the material of the conductor material layer is a chemically stable conductor material.

2. The phase change memory cell of claim 1, wherein, The two-dimensional crystal diode layer comprises a two-dimensional crystal PN diode layer configured as a two-dimensional crystal material layer with N-type semiconductor property and a two-dimensional crystal material layer with P-type semiconductor property connected in sequence, and the second electrode is connected with the two-dimensional crystal material layer with P-type semiconductor property.

3. The phase change memory cell of claim 1, wherein, The two-dimensional crystal diode layer comprises a two-dimensional crystal Schottky diode layer configured as a two-dimensional crystal material layer with semiconductor property and a two-dimensional crystal material layer with metal property connected in sequence, and the second electrode is connected with the two-dimensional crystal material layer with metal property.

4. The phase change memory cell of claim 1, wherein, The first electrode comprises a bottom electrode and a heating electrode connected with the bottom electrode in correspondence, the lower end of the heating electrode is connected with the upper end of the bottom electrode, and the upper end of the heating electrode is connected with the lower end of the phase change material layer.

5. A method for manufacturing a phase change memory cell as claimed in any one of the claims 1 to 4, characterized in that Comprising the following steps: S01: providing a substrate, depositing a first dielectric layer on the substrate, and forming a plurality of first electrodes in the substrate and the first dielectric layer; S02: depositing a second dielectric layer on the first dielectric layer, and forming a first recess structure penetrating the second dielectric layer corresponding to the position of each first electrode; S03: sequentially forming a phase change material layer and a barrier layer on the sidewall surface of the first recess, thereby forming a second recess in the first recess inside the barrier layer, and connecting the phase change material layer with each first electrode; S04: forming a selector device layer in the second recess and filling the second recess; wherein the formed selector device layer comprises a two-dimensional crystal diode layer; when forming the selector device layer, the two-dimensional crystal diode layer is first formed on the sidewall surface of the second recess, and then a conductor material layer is formed inside the two-dimensional crystal diode layer; S05: removing the excess phase change material layer, barrier layer and selector device layer material outside the first recess to form a columnar structure phase change unit in the first recess; S06: depositing a third dielectric layer on the second dielectric layer, and forming a second electrode connected with the selector device layer in the third dielectric layer, wherein the second electrode is only connected with the conductor material layer.

6. The method of claim 5, wherein the phase change memory cell is formed by: In the step S04, when the two-dimensional crystal diode layer is formed, the step of sequentially forming a two-dimensional crystal material layer with N-type semiconductor property and a two-dimensional crystal material layer with P-type semiconductor property on the sidewall surface of the second groove is included, so as to form a two-dimensional crystal PN diode layer; in the step S06, the second electrode formed is connected with the two-dimensional crystal material layer with P-type semiconductor property.

7. The method of claim 5, wherein the phase change memory cell is formed by: In the step S04, when the two-dimensional crystal diode layer is formed, the step of sequentially forming a two-dimensional crystal material layer with semiconductor property and a two-dimensional crystal material layer with metal property on the sidewall surface of the second groove is included, so as to form a two-dimensional crystal Schottky diode layer; in the step S06, the second electrode formed is connected with the two-dimensional crystal material layer with metal property.

8. The method of claim 5, wherein the phase change memory cell is formed by: In the step S01, the plurality of first electrodes formed in the substrate and the first dielectric layer includes: forming a plurality of bottom electrodes in the substrate and the first dielectric layer, and continuing to form a plurality of first heating electrodes connected with the bottom electrodes correspondingly on the bottom electrodes; in the step S03, the phase change material layer formed is connected with each first heating electrode.

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