A phase-change memory cell and its fabrication method

Abstract

This invention discloses a phase-change memory (PCM) cell and its fabrication method. The PCM cell, from bottom to top, includes a first electrode, a PCM unit, and a second electrode. The PCM unit is configured as a vertically arranged cylindrical structure. From the inside out, the cylindrical structure includes a PCM material layer, a barrier layer, and a selector layer connected sequentially. The first electrode is connected to the selector layer, and the second electrode is connected to the PCM material layer. The selector layer includes a vertically arranged two-dimensional crystal diode layer. This invention fabricates a cylindrical PCM unit with a ring-shaped nested structure using a groove-filling method, which improves the device's performance and reliability. Furthermore, by using a two-dimensional crystal diode layer to form the selector layer, its lower threshold voltage effectively reduces device power consumption and saves production costs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a phase-change memory cell and its fabrication method. Background Technology

[0002] Small cell size, high performance, and low power consumption have always been the goals pursued in memory device development. However, as process nodes continue to shrink, transistors, due to their use of three-dimensional devices such as FinFETs, are no longer compatible with some existing embedded memory devices. Furthermore, the emergence of new information technologies such as big data, the Internet of Things, cloud computing, and artificial intelligence has placed high demands on memory devices for computing power, which existing DRAM and NAND flash memory cannot meet. Therefore, new memory technologies, such as phase-change memory, are gaining increasing popularity.

[0003] refer to Figure 1 Existing phase-change memory (PCM) cells, taking Intel's X-point technology as an example, typically consist of a bottom electrode 01, a selectable device layer 02, a barrier layer 03, a phase-change material layer 04, and a top electrode 05, from bottom to top. In the actual fabrication process of these PCM cells, since the selectable device layer 02, barrier layer 03, and phase-change material layer 04 are etched into their patterns using a single photolithography and etching process after their respective thin film deposition, this etching process presents the following three problems:

[0004] First, due to the different materials used in the three thin films—device layer 02, barrier layer 03, and phase change material layer 04—the etching rates differ among them. Therefore, the sidewalls of the etched pattern are not ideally straight lines, but rather exhibit twists and turns, such as... Figure 2 As shown. The tortuous shape of this pattern's sidewalls may lead to a decrease in device reliability.

[0005] Second, during the etching process, the plasma can damage the sidewalls of the etched pattern, causing an increase in the edge roughness of the thin film sidewalls of the device selection layer 02, barrier layer 03, and phase change material layer 04, such as... Figure 3 As shown, the increased roughness of the line edges on the sidewalls of this pattern will affect the performance of the phase change device.

[0006] Third, the bidirectional threshold switch used in Intel's 3DX-point technology has a high threshold voltage, reaching 3-5V, resulting in high power consumption of the phase-change unit. Furthermore, the materials used in bidirectional threshold switches mostly contain toxic substances such as As or Se, requiring the deposition equipment to be equipped with special protective devices, thus increasing the cost of large-scale production and making compatibility with CMOS production lines more difficult.

[0007] Therefore, it is necessary to design a low-power phase-change memory cell and its fabrication method to solve the above-mentioned problems caused by insufficient process technology. Summary of the Invention

[0008] The purpose of this invention is to overcome the above-mentioned defects in the prior art and provide a phase change memory cell and its preparation method, so as to effectively improve the device performance and reliability of the phase change memory cell, reduce device power consumption, and save production costs.

[0009] To achieve the above objectives, the technical solution of the present invention is as follows:

[0010] The present invention provides a phase change memory cell, comprising, from bottom to top, a first electrode, a phase change unit, and a second electrode, wherein the phase change unit is configured as a vertical cylindrical structure, and the cylindrical structure comprises, from the inside out, a phase change material layer, a barrier layer, and a selection device layer connected in sequence; wherein the first electrode is connected to the selection device layer, the second electrode is connected to the phase change material layer, and the selection device layer comprises a vertically arranged two-dimensional crystal diode layer.

[0011] Furthermore, the two-dimensional crystal diode layer includes a two-dimensional crystal PN diode layer, which is configured to be connected to a two-dimensional crystal material layer having N-type semiconductor properties and a two-dimensional crystal material layer having P-type semiconductor properties, and the first electrode is connected to the two-dimensional crystal material layer having P-type semiconductor properties.

[0012] Furthermore, the two-dimensional crystal diode layer includes a two-dimensional crystal Schottky diode layer, which is configured to be connected to a two-dimensional crystal material layer with semiconductor properties and a two-dimensional crystal material layer with metallic properties, and the first electrode is connected to the two-dimensional crystal material layer with metallic properties.

[0013] Furthermore, the selection device layer also includes a conductor material layer connected to the outside of the two-dimensional crystal diode layer, and the first electrode is connected to the conductor material layer.

[0014] Further, the first electrode includes a bottom electrode and a first heating electrode, the lower end of the first heating electrode is connected to the upper end of the bottom electrode, the upper end of the first heating electrode is connected to the lower end of the selector layer, and / or the second electrode includes a top electrode and a second heating electrode, the upper end of the second heating electrode is connected to the lower end of the top electrode, and the lower end of the second heating electrode is connected to the upper end of the phase change material layer.

[0015] This invention also provides a method for fabricating a phase-change memory cell, comprising the following steps:

[0016] S01: A substrate is provided, a first dielectric layer is deposited on the substrate, and a first electrode is formed in the substrate and the first dielectric layer;

[0017] S02: Deposit a second dielectric layer on the first dielectric layer, and form a through first groove structure in the second dielectric layer corresponding to the position of the first electrode;

[0018] S03: A selectable device layer and a barrier layer are sequentially formed on the sidewall surface of the first groove, thereby forming a second groove in the first groove within the barrier layer, and connecting the selectable device layer to the first electrode; wherein the formed selectable device layer includes a two-dimensional crystal diode layer;

[0019] S04: A phase change material layer is formed in the second groove, and the second groove is filled;

[0020] S05: Remove excess phase change material layer, barrier layer and selector layer material outside the first groove to form a columnar phase change unit in the first groove;

[0021] S06: Deposit a third dielectric layer on the second dielectric layer, and form a second electrode in the third dielectric layer that connects to the phase change material layer.

[0022] Further, in step S03, when forming the two-dimensional crystal diode layer, a two-dimensional crystal material layer with P-type semiconductor properties and a two-dimensional crystal material layer with N-type semiconductor properties are sequentially formed on the sidewall surface of the first groove, thereby forming a two-dimensional crystal PN diode layer, and the two-dimensional crystal material layer with P-type semiconductor properties is connected to the first electrode.

[0023] Further, in step S03, when forming the two-dimensional crystal diode layer, a two-dimensional crystal material layer with metallic properties and a two-dimensional crystal material layer with semiconductor properties are sequentially formed on the sidewall surface of the first groove, thereby forming a two-dimensional crystal Schottky diode layer, and the two-dimensional crystal material layer with metallic properties is connected to the first electrode.

[0024] Further, in step S03, when forming the selected device layer, a conductor material layer is first formed on the sidewall surface of the first groove, and then a two-dimensional crystal diode layer is formed inside the conductor material layer, and the conductor material layer is connected to the first electrode.

[0025] Further, in step S01, forming a first electrode in the substrate and the first dielectric layer includes: forming a bottom electrode in the substrate and the first dielectric layer, and continuing to form a first heating electrode connected to the bottom electrode on the bottom electrode; in step S03, connecting the formed selection device layer to the first heating electrode; and / or in step S06, forming a second electrode connected to the phase change material layer in the third dielectric layer includes: forming a second heating electrode in the third dielectric layer, connecting the second heating electrode to the phase change material layer, and continuing to form a top electrode connected to the second heating electrode on the second heating electrode.

[0026] As can be seen from the above technical solution, this invention prepares a cylindrical phase change unit with a ring-shaped nested structure of a phase change material layer, a barrier layer, and a selector layer through groove filling and chemical mechanical polishing. This not only maintains the smooth sidewall morphology of the phase change unit but also avoids damage to the critical operating area of ​​the phase change material, namely the contact area between the phase change material and the second electrode, thus improving the performance and reliability of the device. Simultaneously, the groove filling method can form a cylindrical phase change material layer with a smaller volume, significantly reducing the power consumption required for phase change and enabling full phase change, thereby improving the consistency between units. Furthermore, by using a two-dimensional transistor layer as the selector layer and placing it outside the cylindrical structure of the phase change unit, its lower threshold voltage effectively reduces device power consumption. The material used in the two-dimensional transistor layer does not contain toxic elements, making it environmentally friendly and compatible with standard CMOS process lines. This overcomes the problems associated with previous bidirectional threshold switches, reducing production costs. In summary, this invention effectively improves the device performance and reliability of phase change memory units, reduces device power consumption, and saves production costs. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a traditional phase-change memory cell.

[0028] Figure 2 This is a schematic diagram of the defect morphology generated during the fabrication of the first existing phase-change memory cell.

[0029] Figure 3 This is a schematic diagram of the defect morphology generated during the fabrication of the second type of existing phase-change memory cell.

[0030] Figure 4 This is a schematic diagram of the structure of a phase-change memory cell according to the first embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram of the structure obtained after depositing and forming a first dielectric layer and a bottom electrode on a substrate in an embodiment of the present invention;

[0032] Figure 6 Is Figure 5 The diagram shows the corresponding cross-sectional and top views of the structure obtained after depositing the fourth dielectric layer and the first heating electrode on the structure shown.

[0033] Figure 7 Is Figure 6 The diagram shows the corresponding cross-sectional and top views of the structure obtained after depositing the second dielectric layer and the first groove on the structure shown.

[0034] Figure 8 Is Figure 7 The diagram shows the corresponding cross-sectional and top views of the structure obtained after depositing the selective device layer and the barrier layer on the structure shown.

[0035] Figure 9 Is Figure 8 The diagram shows the corresponding cross-sectional and top views of the structure obtained after depositing a phase change material layer on the structure shown.

[0036] Figure 10 Is Figure 9 The diagram shows the corresponding cross-sectional and top views of the structure obtained after chemical mechanical polishing to form phase change units.

[0037] Figure 11 Is Figure 10 The diagram shows the corresponding cross-sectional and top views of the structure obtained after depositing the third dielectric layer and the second heating electrode on the structure shown.

[0038] Figure 12 Is Figure 11 The diagram shows the corresponding cross-sectional and top views of the structure obtained after depositing the fifth dielectric layer and the top electrode on the structure shown.

[0039] Figure 13 These are corresponding schematic diagrams of the cross-sectional view and top view of the phase-change memory cell structure according to the second embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0041] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0042] Figure 4 This is a schematic diagram of the structure of a phase-change memory cell according to the first embodiment of the present invention.

[0043] A phase-change memory cell of the present invention, referenced Figure 4 From bottom to top, the structure includes a first electrode 103, a phase change unit 112, and a second electrode 114, each corresponding to the first electrode. The phase change unit 112 is a vertically oriented cylindrical structure; from the inside to the outside, the cylindrical structure includes a phase change material layer 111, a barrier layer 109, and a selection device layer 108 connected in sequence. The first electrode 103 is connected to the selection device layer 108, and the second electrode 114 is connected to the phase change material layer 111. The selection device layer 108 includes a vertically arranged two-dimensional crystal diode layer.

[0044] A phase-change memory cell can be fabricated on a substrate 101. One or more dielectric layers can be disposed on the substrate 101, for example, a first dielectric layer 102, a second dielectric layer 106, and a third dielectric layer 113; a fourth dielectric layer 104 can also be disposed between the first dielectric layer 102 and the second dielectric layer 106, and a fifth dielectric layer can be disposed on the third dielectric layer 113. The fourth dielectric layer 104 can be considered an extension of the first dielectric layer 102, and the fifth dielectric layer can be considered an extension of the third dielectric layer 113. The phase-change memory cell can be embedded within the aforementioned dielectric layers.

[0045] Substrate 101 may include semiconductor materials, such as silicon substrates, gallium arsenide substrates, germanium substrates, germanium-silicon substrates, or fully depleted silicon-on-insulator substrates. Substrate 101 may also be an integrated circuit, including integrated circuits with gates such as transistors or diodes.

[0046] In an optional embodiment, the first electrode 103 may include a bottom electrode 103a and a first heating electrode 103b; the top of the bottom electrode 103a and the bottom of the first heating electrode 103b are connected.

[0047] The bottom electrode 103a may be located in both the substrate 101 and the first dielectric layer 102. For example, the lower part of the bottom electrode 103a may be located in the substrate 101, while the upper part may be exposed on the surface of the substrate 101 and located in the first dielectric layer 102.

[0048] The bottom electrode 103a may have a through-hole structure; the material of the bottom electrode 103a may be a copper electrode, but is not limited to this.

[0049] The first heating electrode 103b can be located in the fourth dielectric layer 104, and can adopt a fan-shaped (three-dimensional fan-ring) structure, a cubic structure, or an L-shaped structure that is longitudinally disposed on the upper surface of the bottom electrode 103a. When an L-shaped structure is adopted, the horizontal bottom edge of the L-shaped structure is connected to the upper surface of the bottom electrode 103a, and the upper end of the vertical sidewall of the L-shaped structure is correspondingly connected to the lower end of the ring of the selection device layer 108.

[0050] In this embodiment, the first heating electrode 103b adopts an L-shaped structure with vertical sidewalls.

[0051] The phase change unit 112 may be located in the second dielectric layer 106, and from the inside out, it may include: a cylindrical phase change material layer 111, an annular barrier layer 109, and an annular selector layer 108. Preferably, the phase change unit 112 may include, from the inside out, a cylindrical phase change material layer 111, an annular barrier layer 109, and an annular selector layer 108.

[0052] The ring-shaped selector layer 108 is a two-dimensional crystal diode layer. The material of the selector layer 108 will not undergo a phase change during the operation of the phase-change memory device.

[0053] In an optional embodiment, the device layer 108 may be a two-dimensional crystal PN diode layer, comprising an interconnected two-dimensional crystal material layer 108b having N-type semiconductor properties and a two-dimensional crystal material layer 108a having P-type semiconductor properties. The material of the two-dimensional crystal material layer 108b having N-type semiconductor properties may be at least one of silylene, germanene, black phosphorus, tinene, triazine-based graphitic carbon nitride, or transition metal disulfides such as molybdenum disulfide, tungsten disulfide, and molybdenum diselenide. The material of the two-dimensional crystal material layer 108a having P-type semiconductor properties may be at least one of silylene, germanene, black phosphorus, tinene, or triazine-based graphitic carbon nitride, or at least one of the doped materials of silylene, germanene, black phosphorus, tinene, or triazine-based graphitic carbon nitride, wherein the doping element may be B, Al, In, etc.

[0054] In an optional embodiment, the device layer 108 may also be a two-dimensional crystal Schottky diode layer, which includes a two-dimensional crystal material layer 108b with semiconductor properties and a two-dimensional crystal material layer 108a with metallic properties connected together. The material of the two-dimensional crystal material layer 108b with semiconductor properties may be at least one of tungsten disulfide and molybdenum disulfide, molybdenum ditelluride, tantalum disulfide, tantalum ditelluride, niobium disulfide, and niobium ditelluride; the material of the two-dimensional crystal material layer 108a with metallic properties may be at least one of titanium disulfide, molybdenum disulfide, and tungsten ditelluride.

[0055] In the above embodiments, the upper end of the first heating electrode 103b is connected only to the lower end of the two-dimensional crystal material layer 108a with P-type semiconductor properties or the two-dimensional crystal material layer 108a with metallic properties.

[0056] The barrier layer 109 is made of a conductive material with high thermal and electrical conductivity and stable chemical properties. It will not chemically react with the materials of the selective device layer 108 or the phase change material layer 111, nor will element diffusion occur between them. Furthermore, it prevents mutual reactions and element diffusion between the selective device layer 108 and the phase change material layer 111, thus facilitating the growth of the two-dimensional crystal material. The barrier layer 109 can be made of graphene, a carbon-containing compound, a two-dimensional material, or at least one of the following: Ti, Pt, W, Ta, Cu, WCN, WN, and TaN.

[0057] The initial state of the phase change material layer 111 is crystalline. The material of the phase change material layer 111 can be at least one of the following: GeTe-Sb2Te3 system, GeTe-SnTe system, Sb2Te system, In3SbTe2 system, Sb-doped system, GeTe-Sb2Te3 system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements, GeTe-SnTe system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements, Sb2Te system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements, In3SbTe2 system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements, and Sb-doped system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements.

[0058] In an optional embodiment, the second electrode 114 may consist of a top electrode 114b and a second heating electrode 114a. The bottom of the second heating electrode 114a is connected only to the phase change material layer 111, and the top of the second heating electrode 114a is connected to the top electrode 114b.

[0059] The second heating electrode 114a can be a fan-shaped ring structure or a sidewall structure that is longitudinally arranged on the phase change unit 112 and located in the third dielectric layer 113.

[0060] In this way, a higher current density can be generated by using the first heating electrode 103b and the second heating electrode 114a, which have a smaller thickness, thereby significantly improving the heating efficiency and further reducing the power consumption of the device.

[0061] The top electrode 114b may be a metal layer structure disposed on the second heating electrode 114a and located in the fifth dielectric layer, such as a copper wire, but not limited thereto.

[0062] The following detailed embodiments and accompanying drawings illustrate one preparation method of the present invention. Figure 4 The method of phase-change memory cell in the process will be further explained.

[0063] like Figures 5-12 As shown, a method for fabricating a phase-change memory cell according to the present invention may include the following steps:

[0064] S11: As Figure 5 As shown, a first dielectric layer 102 is deposited on a substrate 101, and two bottom electrodes 103a are formed in the substrate 101 and the first dielectric layer 102. The lower half of the bottom electrode 103a is located in the substrate 101, and the upper half is located in the first dielectric layer 102.

[0065] In this embodiment, the bottom electrode 103a can be a copper wire with a diameter of 50-100 nm, preferably 60 nm.

[0066] like Figure 6 As shown, a fourth dielectric layer 104 is deposited on the first dielectric layer 102 and the bottom electrode 103a, and a groove structure is formed in the fourth dielectric layer 104 at the position corresponding to the bottom electrode 103a, penetrating the fourth dielectric layer 104.

[0067] Viewed from above, the groove can be circular, elliptical, rectangular, or polygonal. In this embodiment, a rectangular groove can be formed in the fourth dielectric layer 104. The side length of the groove is slightly smaller than the distance between the outer edges of the two bottom electrodes 103a. The groove is located above the outer edges of the two bottom electrodes 103a.

[0068] Then, a first heating electrode 103b is formed on the inner wall surface of the groove, and the first heating electrode 103b is connected to the bottom electrode 103a to form the first electrode 103.

[0069] The first heating electrode 103b can be at least one of a three-dimensional fan-shaped annular structure and a three-dimensional L-shaped sidewall structure. The thin film of the first heating electrode 103b can be deposited using atomic layer deposition, chemical vapor deposition, or high-density plasma chemical vapor deposition processes.

[0070] In this embodiment, a thin film of the first heating electrode 103b material is deposited on the inner wall surface of the rectangular groove, and the first heating electrode 103b material is patterned by photolithography and etching. Excess first heating electrode 103b material located on the side wall and bottom surface of the groove is removed. Then, the groove is filled with the fourth dielectric layer 104 material to fill the groove. The groove is then planarized by polishing to form two L-shaped first heating electrodes 103b located on a bottom electrode 103a respectively. Figure 6 The horizontal bottom edge of the first heating electrode 103b of the L-shaped structure is omitted in the top view.

[0071] The material of the first heating electrode 103b can be TiN. The thickness of the vertical sidewall of the L-shaped structure of the first heating electrode 103b can be 3 to 10 nm, preferably 6 nm.

[0072] S12: As Figure 7 As shown, a second dielectric layer 106 is deposited on the fourth dielectric layer 104 and the first heating electrode 103b. A first groove 107 structure penetrating the second dielectric layer 106 is formed in the second dielectric layer 106 at a position corresponding to each bottom electrode 103a. The first groove 107 can be one of an elliptical cylinder, a cylinder, a cuboid, or a prism. In this embodiment, the first groove 107 is a circular through-hole structure with a diameter of 40-120 nm, for example, 60 nm.

[0073] S13: As Figure 8 As shown, an annular selector layer 108 and a barrier layer 109 are sequentially formed on the sidewall surface of the first groove 107, and the top of the first heating electrode 103b is connected to the bottom of the annular selector layer 108. The selector layer 108 includes a two-dimensional crystal diode layer.

[0074] In step S11, the purpose of further fabricating a first heating electrode 103b on the bottom electrode 103a is to ensure the connectivity between the bottom electrode 103a and the selectable device layer 108. Since the selectable device layer 108 is relatively thin, typically 5-30 nm, while conventional bottom electrodes are generally 40-120 nm thick, directly connecting the bottom electrode 103a and the selectable device layer 108 in a conventional manner can easily lead to photolithographic alignment errors. This can result in the bottom electrode 103a not being connected to the selectable device layer 108, or the bottom electrode 103a being simultaneously connected to the selectable device layer 108, the barrier layer 109, and the phase change material layer 111, thus reducing process quality. This invention adds a first heating electrode 103b to the bottom electrode 103a. Utilizing the smaller thickness of the first heating electrode 103b compared to the selectable device layer 108, it effectively improves process stability and the process window (photolithographic alignment), thereby ensuring reliable connection performance between the selectable device layer 108 and the bottom electrode 103a.

[0075] In an optional embodiment, the selected device layer 108 may be a two-dimensional crystal PN diode layer, and may be composed of a two-dimensional crystal material layer 108b having N-type semiconductor properties and a two-dimensional crystal material layer 108a having P-type semiconductor properties. The two-dimensional crystal material layer 108b having N-type semiconductor properties may be at least one of silylene, germanene, black phosphorus, tinene, triazine-based graphitic carbon nitride, and transition metal disulfides such as molybdenum disulfide and tungsten disulfide; the two-dimensional crystal material layer 108a having P-type semiconductor properties may be at least one of silylene, germanene, black phosphorus, tinene, and triazine-based graphitic carbon nitride.

[0076] In an optional embodiment, the selected device layer 108 may also be a two-dimensional crystal Schottky diode layer, and may be composed of a two-dimensional crystal material layer 108b with semiconductor properties and a two-dimensional crystal material layer 108a with metallic properties. The two-dimensional crystal material layer 108b with semiconductor properties may be at least one of tungsten disulfide, molybdenum disulfide, molybdenum ditelluride, tantalum disulfide, tantalum ditelluride, niobium disulfide, and niobium ditelluride, and the two-dimensional crystal material layer 108a with metallic properties may be at least one of titanium disulfide, molybdenum disulfide, and tungsten ditelluride.

[0077] The barrier layer 109 can be a conductive material with high thermal and electrical conductivity and stable chemical properties at high temperatures. It will not chemically react with the materials of the selective device layer 108 or the phase change material layer 111, nor will element diffusion occur between them. Furthermore, it can prevent mutual reactions and element diffusion between the materials of the selective device layer 108 and the phase change material layer 111. The barrier layer 109 can be at least one of graphene, carbon-containing compounds, two-dimensional materials, or materials containing Ti, Pt, W, Ta, Cu, WCN, WN, or TaN.

[0078] The selective device layer 108 can be deposited using high-density plasma chemical vapor deposition (PDCVD) or atomic layer deposition (ALD), meaning that a three-dimensional annular film is deposited only on the sidewalls of the first groove 107. The barrier layer 109 can be deposited using PDCVD and can be deposited in the same equipment as the selective device layer 108.

[0079] In this embodiment, the selector layer 108 is a two-dimensional crystal Schottky diode layer, wherein the two-dimensional crystal material layer 108b with semiconductor properties is MoS2, and the two-dimensional crystal material layer 108a with metallic properties is WTe2. The selector layer 108, composed of the two-dimensional crystal material layer 108a with metallic properties and the two-dimensional crystal material layer 108b with semiconductor properties, will not change during phase transition unit operation. The barrier layer 109 is made of graphene, for example, and its thickness can be 3-15 nm, for example, 5 nm. The selector layer 108 and the barrier layer 109 are deposited in the same equipment using HDP CVD to form an annular selector layer 108 and barrier layer 109.

[0080] The high-density plasma chemical vapor deposition method is a deposition-etching-deposition-etching method, which ensures that the selectable device layer 108 and the barrier layer 109 are deposited only on the sidewalls of the first groove 107, while no thin film is deposited at the bottom of the first groove 107, making the selectable device layer 108 and the barrier layer 109 three-dimensional rings.

[0081] Graphene, as a barrier layer 109, has stable chemical properties and excellent electrical and thermal conductivity, which is beneficial for improving the performance of phase change memory devices.

[0082] The upper surface of the vertical sidewall of the first heating electrode 103b is entirely located within the region inside the lower surface of the two-dimensional crystalline material layer 108a, which has metallic properties.

[0083] Since the barrier layer 109 is formed only on the sidewall of the first groove 107, a second groove is formed in the first groove 107 within the barrier layer 109.

[0084] S14: As Figure 9 As shown, a phase change material layer 111 is deposited in the second groove within the barrier layer 109, and the second groove is filled.

[0085] The initial state of the phase change material layer 111 is crystalline. The material of the phase change material layer 111 is at least one of the following: GeTe-Sb2Te3 system, GeTe-SnTe system, Sb2Te system, In3SbTe2 system, Sb-doped system, GeTe-Sb2Te3 system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements, GeTe-SnTe system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements, Sb2Te system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements, In3SbTe2 system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements, and Sb-doped system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements.

[0086] The phase change material layer 111 can be produced using chemical vapor deposition or atomic layer deposition. The deposition process must ensure that the formed three-dimensional columnar phase change material layer 111 is free of gaps and pores. The deposition temperature can be between 200 and 500°C, and the deposited phase change material is crystalline.

[0087] In this embodiment, the phase change material layer 111 is made of, for example, C-doped GeSbTe, and the deposition temperature is 300°C. After deposition, the C-doped GeSbTe thin film is crystalline.

[0088] S15: As Figure 10 As shown, the excess phase change material layer 111, barrier layer 109 and selector layer 108 material outside the first groove 107 can be removed by chemical mechanical polishing, and a columnar phase change unit 112 is formed in the first groove 107.

[0089] The formed cylindrical phase change unit 112 comprises, from the inside out, a phase change material layer 111, a barrier layer 109, and a selector layer 108. The cylindrical phase change unit 112 can be one of an elliptical cylinder, a cylindrical shape, a cuboid, or a prism. The top end of the first heating electrode 103b is connected only to the outermost selector layer 108 of the cylindrical phase change unit 112, and the bottom end of the first heating electrode 103b is connected only to the bottom electrode 103a.

[0090] S16: As Figure 11 As shown, a third dielectric layer 113 is deposited on the second dielectric layer 106 and the phase change unit 112, and a second heating electrode 114a connecting the phase change material layer 111 is formed in the third dielectric layer 113.

[0091] The second heating electrode 114a is connected only to the innermost phase change material layer 111 of the cylindrical phase change unit 112.

[0092] In this embodiment, a circular groove is first formed in the third dielectric layer 113, with the bottom circumference of the groove intersecting the surface of the phase change material layer 111 in the two phase change units 112 shown in the figure. A thin film of the second heating electrode 114a is deposited in the groove, and two fan-shaped second heating electrodes 114a are formed respectively on one phase change material layer 111 through photolithography and etching, with the bottom of the fan-shaped second heating electrode 114a only in contact with the phase change material layer 111 in the phase change unit 112. Then, by depositing dielectric layer material in the groove and polishing, a three-dimensional fan-shaped second heating electrode 114a is finally formed. The material of the second heating electrode 114a is, for example, TiN, with a thickness of 3-60 nm, for example, 6 nm.

[0093] like Figure 12 As shown, a fifth dielectric layer is deposited on the third dielectric layer 113 and the second heating electrode 114a, and a top electrode 114b connecting the second heating electrode 114a is formed in the fifth dielectric layer. In this embodiment, the top electrode 114b is a copper wire metal layer with a width of 30-120 nm, for example, 45 nm.

[0094] In this embodiment, the second electrode 114 consists of a second heating electrode 114a and a top electrode 114b. The bottom of the second heating electrode 114a is connected to the phase change material layer 111, and the top of the second heating electrode 114a is connected to the top electrode 114b. The second heating electrode 114a is a fan-shaped annular structure or a sidewall structure arranged longitudinally on the phase change unit 112.

[0095] Figure 13 These are corresponding schematic diagrams of the cross-sectional view and top view of the phase-change memory cell structure according to the second embodiment of the present invention. To clearly illustrate the structure of the present invention, Figure 13 The diagram shows the corresponding cross-sectional and top views of the structure. Figure 13 The top image shows a cross-sectional view, and the bottom image shows a top view.

[0096] refer to Figure 13 As another optional embodiment, a phase-change memory cell of the present invention includes: a first electrode 203 disposed on a substrate 201 and a first dielectric layer 202, a phase-change unit 212 disposed in a second dielectric layer 206, and a second electrode 214 disposed on a third dielectric layer 213. The phase-change unit 212 is a vertical cylindrical structure, and the cylindrical structure includes a cylindrical phase-change material layer 211, an annular barrier layer 209, and an annular select device layer 208 connected sequentially from the inside to the outside.

[0097] The device selection layer 208 may include a conductor material layer 208a disposed on the outermost side of the cylindrical phase change unit 212 and a ring-shaped two-dimensional crystal diode layer 208b disposed inside the conductor material layer 208a. The two-dimensional crystal diode layer 208b may include a two-dimensional crystal material layer with P-type semiconductor properties and a two-dimensional crystal material layer with N-type semiconductor properties; or, the two-dimensional crystal diode layer 208b may also include a two-dimensional crystal material layer with semiconductor properties and a two-dimensional crystal material layer with metallic properties.

[0098] The conductor material layer 208a facilitates the growth of two-dimensional crystals and possesses high thermal and electrical conductivity, as well as chemical stability at high temperatures, further reducing the contact resistance with the first electrode 203. The conductor material layer 208a can be graphene, a carbon-containing compound, a two-dimensional material, or at least one of the following: Ti, Pt, W, Ta, Cu, WCN, WN, and TaN. In this embodiment, the conductor material layer 208a is graphene.

[0099] The first electrode 203 may include a bottom electrode 203a and a first heating electrode 203b. The first heating electrode 203b may be disposed in a fourth dielectric layer 204 on the first dielectric layer 202. The first heating electrode 203b is only connected to the conductor material layer 208a of the select device layer 208. The second electrode 214 may include a top electrode 214b and a second heating electrode 214a. The second heating electrode 214a is only connected to the phase change material layer 211.

[0100] Other aspects of the aforementioned phase-change memory unit and its fabrication method can be found in the above description. Figure 4 Structure and Figures 5-12 The preparation method is explained through examples and will not be repeated here.

[0101] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A phase change memory cell, comprising: From bottom to top, a first electrode, a phase change unit and a second electrode are correspondingly arranged, the phase change unit is configured as a longitudinal columnar structure, the columnar structure comprises, from inside to outside, a phase change material layer, a barrier layer and a selector device layer connected in sequence; wherein the first electrode is connected with the selector device layer, the second electrode is connected with the phase change material layer, the selector device layer comprises a two-dimensional crystal diode layer arranged longitudinally and a conductor material layer arranged outside the two-dimensional crystal diode layer in connection, and the first electrode is connected with the conductor material layer; the conductor material layer is a carbon-containing compound containing at least one of Ti, Pt, W, Ta, Cu, WN and TaN materials.

2. The phase change memory cell of claim 1, wherein, The two-dimensional crystal diode layer comprises a two-dimensional crystal PN diode layer configured as a two-dimensional crystal material layer with N-type semiconductor properties and a two-dimensional crystal material layer with P-type semiconductor properties connected in connection, and the first electrode is connected with the two-dimensional crystal material layer with P-type semiconductor properties.

3. The phase change memory cell of claim 1, wherein, The two-dimensional crystal diode layer comprises a two-dimensional crystal Schottky diode layer configured as a two-dimensional crystal material layer with semiconductor properties and a two-dimensional crystal material layer with metal properties connected in connection, and the first electrode is connected with the two-dimensional crystal material layer with metal properties.

4. The phase change memory cell of claim 1, wherein, The first electrode comprises a bottom electrode and a first heating electrode, the lower end of the first heating electrode is connected with the upper end of the bottom electrode, and the upper end of the first heating electrode is connected with the lower end of the selector device layer, and / or the second electrode comprises a top electrode and a second heating electrode, the upper end of the second heating electrode is connected with the lower end of the top electrode, and the lower end of the second heating electrode is connected with the upper end of the phase change material layer.

5. A method for manufacturing a phase change memory cell as claimed in any one of the claims 1 to 4, characterized in that The method comprises the following steps: S01: providing a substrate, depositing a first dielectric layer on the substrate, and forming a first electrode in the substrate and the first dielectric layer; S02: depositing a second dielectric layer on the first dielectric layer, forming a first recess structure penetrating through the second dielectric layer corresponding to the position of the first electrode; S03: sequentially forming a selector device layer and a barrier layer on the sidewall surface of the first recess, thereby forming a second recess in the first recess inside the barrier layer and connecting the selector device layer with the first electrode; wherein the formed selector device layer comprises a two-dimensional crystal diode layer; when forming the selector device layer, a conductor material layer is first formed on the sidewall surface of the first recess, then a two-dimensional crystal diode layer is formed inside the conductor material layer, and the conductor material layer is connected with the first electrode; S04: forming a phase change material layer in the second recess and filling the second recess; S05: removing the excess phase change material layer, barrier layer and selector device layer material outside the first recess to form a columnar structure phase change unit in the first recess; S06: depositing a third dielectric layer on the second dielectric layer and forming a second electrode connected with the phase change material layer in the third dielectric layer.

6. The method of claim 5, wherein the phase change memory cell is formed by: In the step S03, when the two-dimensional crystal diode layer is formed, the step includes sequentially forming a two-dimensional crystal material layer with P-type semiconductor property and a two-dimensional crystal material layer with N-type semiconductor property on the sidewall surface of the first recess, thereby forming a two-dimensional crystal PN diode layer, and connecting the two-dimensional crystal material layer with P-type semiconductor property with the first electrode.

7. The method of claim 5, wherein the phase change memory cell is formed by: In the step S03, when the two-dimensional crystal diode layer is formed, the step includes sequentially forming a two-dimensional crystal material layer with metal property and a two-dimensional crystal material layer with semiconductor property on the sidewall surface of the first recess, thereby forming a two-dimensional crystal Schottky diode layer, and connecting the two-dimensional crystal material layer with metal property with the first electrode.

8. The method of claim 5, wherein the phase change memory cell is formed by: In the step S01, the first electrode is formed in the substrate and the first dielectric layer, including: forming a bottom electrode in the substrate and the first dielectric layer, and then forming a first heating electrode connected with the bottom electrode on the bottom electrode; in the step S03, the formed selector device layer is connected with the first heating electrode; and / or in the step S06, the second electrode connected with the phase change material layer is formed in the third dielectric layer, including: forming a second heating electrode in the third dielectric layer, and connecting the second heating electrode with the phase change material layer, and then forming a top electrode connected with the second heating electrode on the second heating electrode.

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