A method, apparatus and medium for determining a hold current of a phase change memory array

Abstract

This application provides a method, apparatus, and medium for determining the holding current of a phase-change memory array. The method includes: obtaining the range of set currents for performing a set operation on the phase-change memory array; obtaining the threshold voltage distribution when multiple set currents within the set current range are applied to the phase-change memory array; obtaining the target voltage under each set current based on the standard deviation of a preset multiple of the threshold voltage distribution corresponding to each set current; calculating the voltage difference between the target voltages corresponding to two adjacent set currents within the set current range in the direction of sequential increase of the set current, obtaining multiple voltage differences; and determining the set current corresponding to the voltage difference that satisfies the voltage change condition among the multiple voltage differences as the holding current of the phase-change memory array, thereby achieving simple, fast, accurate, and efficient determination of the holding current of the phase-change memory array.

Description

[0001] This application claims priority to Chinese Patent Application No. 202411949686.9, filed on December 27, 2024, entitled "A Method, Apparatus and Medium for Determining Holding Current of a Phase Change Memory Array", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of semiconductors, and in particular to a method, apparatus and medium for determining the holding current of a phase-change memory array. Background Technology

[0003] Phase-change memory (PCM) bridges the performance gap between dynamic random access memory (DRAM) and flash memory, offering advantages such as high-speed read speed, high erase / write cycles, non-volatility, small component size, low power consumption, and resistance to strong shocks and radiation, leading to its widespread use.

[0004] Unlike DRAM and flash memory, which store data in the form of electrical charges, phase-change memory (PCM) utilizes the crystalline and amorphous states of phase-change materials to store data. For example, different electrical pulses can induce a rapid and reversible phase transition between an amorphous and crystalline state in the PCM. Heating the PCM with an electric current causes it to transform from an amorphous to a crystalline state; this process is called a SET operation. Alternatively, transforming the PCM from a crystalline to an amorphous state is called a RESET operation. This change in the state of the PCM can represent a bit of data, either "0" or "1".

[0005] Hold current is one of the necessary conditions for keeping phase-change memory (PCM) operational, and it has a significant impact on PCM operation, especially SET operation. There is currently a need to determine the hold current of PCM arrays so that it reflects the actual situation of the PCM array. Summary of the Invention

[0006] In view of this, the purpose of this application is to provide a method, apparatus and medium for determining the holding current of a phase change memory array, which can determine the holding current of the phase change memory array simply, quickly, accurately and efficiently.

[0007] This application provides a method for determining the holding current of a phase-change memory array, the method comprising:

[0008] Obtain the set current range for performing a set operation on a phase change memory array, wherein the phase change memory array includes multiple phase change memories;

[0009] The threshold voltage distribution is obtained when multiple set currents within the set current range are applied to the phase change memory array, and the threshold voltage distribution is the number of phase change memories corresponding to different read voltages under the same set current.

[0010] The target voltage under each set current is obtained according to the standard deviation of the threshold voltage distribution corresponding to each set current by a preset multiple;

[0011] Calculate the voltage difference between the target voltages corresponding to two adjacent set currents within the set current range, following the direction of sequential increase of the set current, to obtain multiple voltage difference values;

[0012] The set current corresponding to the voltage difference that satisfies the voltage change condition among the multiple voltage differences is determined as the holding current of the phase change memory array.

[0013] Optionally, obtaining the threshold voltage distribution when multiple set currents within the set current range are applied to the phase-change memory array includes:

[0014] Within the set current range, multiple set currents are traversed at preset current intervals.

[0015] Obtain the threshold voltage distribution when each of the set currents is applied to the phase change memory array.

[0016] Optionally, obtaining the threshold voltage distribution when each of the set currents is applied to the phase-change memory array includes:

[0017] Obtain the read voltage range of the phase-change memory array, wherein the read voltage range includes multiple read voltages;

[0018] The number of phase change memories corresponding to different read voltages when each set current is applied to the phase change memory array is obtained, and the threshold voltage distribution is obtained based on the multiple read voltages and the number of phase change memories corresponding to each read voltage.

[0019] Optionally, the preset multiple is 3.5.

[0020] Optionally, determining the set current corresponding to the voltage difference that satisfies the voltage change condition among the plurality of voltage differences as the holding current of the phase-change memory array includes:

[0021] The target current corresponding to the largest difference among the multiple voltage differences is determined as the holding current of the phase change memory array. The target current is the set current corresponding to the subtraction in the calculation of the largest difference.

[0022] Optionally, the phase change memory array is divided into multiple electrical regions based on electrical distance; the holding current of the phase change memory in different electrical regions is different.

[0023] Optionally, before obtaining the range of the set current for performing a set operation on the phase-change memory array, the method further includes:

[0024] Obtain the number of cycle operations of the phase-change memory array, wherein the cycle operations include write operations and erase operations;

[0025] The step of determining the set current corresponding to the voltage difference that satisfies the voltage change condition among the multiple voltage differences as the holding current of the phase-change memory array includes:

[0026] The set current corresponding to the voltage difference that satisfies the voltage change condition among the multiple voltage differences is determined as the holding current of the phase change memory array after the number of cycle operations.

[0027] Optionally, the setting operation includes multiple stages, and the multiple stages include a second stage;

[0028] The range of set currents for performing set operations on the phase-change memory array includes:

[0029] Obtain the set current range corresponding to the second stage of performing a set operation on the phase change memory array.

[0030] This application provides a holding current determination device for a phase-change memory array, the device comprising:

[0031] The first acquisition unit is used to acquire the set current range for performing a set operation on the phase change memory array, wherein the phase change memory array includes multiple phase change memories;

[0032] The second acquisition unit is used to acquire the threshold voltage distribution when multiple set currents within the set current range are applied to the phase change memory array, wherein the threshold voltage distribution is the number of phase change memories corresponding to different read voltages under the same set current.

[0033] The third acquisition unit is used to acquire the target voltage under each set current according to the standard deviation of a preset multiple of the threshold voltage distribution corresponding to each set current;

[0034] The calculation unit is used to calculate the voltage difference between the target voltages corresponding to two adjacent set currents within the set current range in the direction of sequential increase of the set current, and obtain multiple voltage difference values.

[0035] The determining unit is used to determine the set current corresponding to the voltage difference that satisfies the voltage change condition among the multiple voltage differences as the holding current of the phase change memory array.

[0036] This application provides a computer-readable medium including instructions that, when executed on a computer, cause the computer to perform the method as described in any of the foregoing descriptions.

[0037] This application provides a method for determining the holding current of a phase-change memory (PCM) array. The method includes: obtaining a set current range for performing a set operation on the PCM array, wherein the PCM array includes multiple PCMs; obtaining a threshold voltage distribution when multiple set currents within the set current range are applied to the PCM array, wherein the threshold voltage distribution represents the number of PCMs corresponding to different read voltages under the same set current, and the threshold voltage distribution of different set currents can reflect the difference between the set current and the holding current, thereby assisting in determining the value of the holding current using the value of the set current; obtaining a target voltage under each set current based on the standard deviation of a preset multiple of the threshold voltage distribution corresponding to each set current, and using the target voltage obtained by the preset multiple standard deviation to determine the holding current of the multiple PCMs in the PCM array. The holding current of the phase-change memory array is determined by calculating the voltage difference between the target voltages corresponding to two adjacent set currents within the set current range, following the direction of sequential increase of the set current. Multiple voltage differences are obtained. The set current corresponding to the voltage difference that satisfies the voltage change condition among the multiple voltage differences is determined as the holding current of the phase-change memory array. That is, when the target voltage difference corresponding to two adjacent set currents satisfies the voltage change condition, it means that the two adjacent set currents are the currents closest to the holding current, thus quickly determining the holding current. It can be seen that this application obtains the target voltage corresponding to the standard deviation of a preset multiple by using the threshold voltage distribution obtained by multiple set currents, and then uses whether the voltage difference between the target voltages satisfies the voltage change condition to achieve a simple, fast, accurate and efficient determination of the holding current of the phase-change memory array. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 A flowchart illustrating a method for determining the holding current of a phase-change memory array according to an embodiment of this application is shown.

[0040] Figure 2 A waveform diagram of a set current provided in an embodiment of this application is shown;

[0041] Figure 3This paper illustrates the threshold voltage distribution of a phase memory array under different set currents according to an embodiment of this application.

[0042] Figure 4 This application provides a schematic diagram of a current-voltage curve according to an embodiment.

[0043] Figure 5 This paper presents a schematic diagram of current-voltage curves for different electrical distances provided in an embodiment of this application.

[0044] Figure 6 This invention provides a schematic diagram of current-voltage curves for different number of cycle operations according to an embodiment of the present application.

[0045] Figure 7 A schematic diagram of a current-holding device for a phase-change memory array provided in an embodiment of this application is shown. Detailed Implementation

[0046] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0047] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0048] Phase-change memory (PCM) stores data based on the resistance change of the phase-change material in the memory cell (e.g., being in a high-resistance state or a low-resistance state). PCM has a transistorless cross-point architecture, which places the memory cell at the intersection of vertical conductors, including word lines (WL) and bit lines (BL) that intersect each other perpendicularly. WL and BL are typically composed of 20nm / 20nm constant linewidth (Line / Space, L / S) formed after a patterning process.

[0049] Unlike DRAM and flash memory, which store data in the form of electrical charges, phase-change memory (PCM) utilizes the crystalline and amorphous states of phase-change materials to store data. The storage cells of PCM are heated by an electric current, causing the PCM material to transform from an amorphous state to a crystalline state. This transformation from amorphous to crystalline is also called nucleation, or the change from a high-resistivity state to a low-resistivity state, a process called a SET (set) operation. Alternatively, the PCM material can be transformed from a crystalline state to an amorphous state, or from a low-resistivity state to a high-resistivity state, a process called a RESET (reset) operation. This change in the state of the phase-change material can represent a bit of data, "0" or "1".

[0050] The core component of a phase-change memory (PCM) cell is the phase-change material based on chalcogenides (such as GST materials, specifically Ge2Sb2Te5). PCMs require repeated read and write operations on their cells. Before performing regular read and write operations, the PCM is typically subjected to SET and RESET operations.

[0051] Hold current is one of the necessary conditions for keeping a phase-change memory (PCM) operational, and it has a significant impact on PCM operation, especially SET operation. There is a current need to determine the hold current of a PCM array so that it reflects the actual condition of the PCM array. Therefore, measuring the hold current in a PCM array is of great importance for PCM operation and monitoring changes in the PCM.

[0052] Currently, there is no method to test the hold current in a phase-change memory (PCM) array. Hold current can be measured by performing current-voltage (IV) tests on devices in a test simplified array (TSK), thus reflecting the hold current in the PCM array. However, since the TSK is a simplification of the PCM array, the hold current obtained by this method does not reflect the actual situation in the PCM array. Furthermore, because it is difficult to perform 100k read / write cycles on the devices in a TSK, it is difficult to know the hold current of the PCM after multiple cycles.

[0053] Therefore, there is a current need to determine the holding current of a phase-change memory array so that the holding current reflects the actual situation of the phase-change memory array.

[0054] Based on this, this application provides a method for determining the holding current of a phase-change memory (PCM) array. The method includes: obtaining a set current range for performing a set operation on the PCM array, wherein the PCM array includes multiple PCMs; obtaining a threshold voltage distribution when multiple set currents within the set current range are applied to the PCM array, wherein the threshold voltage distribution represents the number of PCMs corresponding to different read voltages under the same set current, and the threshold voltage distribution of different set currents reflects the difference between the set current and the holding current, thereby assisting in determining the holding current value using the set current value; obtaining a target voltage under each set current based on the standard deviation of a preset multiple of the threshold voltage distribution corresponding to each set current, and using the target voltage obtained from the preset multiple standard deviation to determine the holding current of the multiple PCMs in the PCM array. The holding current of the phase-change memory array is determined by calculating the voltage difference between the target voltages corresponding to two adjacent set currents within the set current range, following the direction of sequential increase of the set current. Multiple voltage differences are obtained. The set current corresponding to the voltage difference that satisfies the voltage change condition among the multiple voltage differences is determined as the holding current of the phase-change memory array. That is, when the target voltage difference corresponding to two adjacent set currents satisfies the voltage change condition, it means that the two adjacent set currents are the currents closest to the holding current, thus quickly determining the holding current. It can be seen that this application obtains the target voltage corresponding to the standard deviation of a preset multiple by using the threshold voltage distribution obtained by multiple set currents, and then uses whether the voltage difference between the target voltages satisfies the voltage change condition to achieve simple, fast, accurate and efficient determination of the holding current of the phase-change memory array.

[0055] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0056] See Figure 1 The figure is a flowchart illustrating a method for determining the holding current of a phase-change memory array according to an embodiment of this application.

[0057] The method for determining the holding current of a phase-change memory array provided in this embodiment includes the following steps:

[0058] S101, obtain the set current range for performing a set operation on the phase change memory array, the phase change memory array including multiple phase change memories.

[0059] In the embodiments of this application, heating the storage cells of the phase change memory with current can cause the phase change material to change from an amorphous state to a crystalline state, i.e., a SET (set) operation. Therefore, if a SET operation is performed on the phase change memory, the set current for the SET operation needs to be obtained first.

[0060] Specifically, the set operation can include multiple phases, including phase 1, phase 2, phase 3, phase 4, and phase 5. The set current may differ for each phase; refer to [reference needed]. Figure 2 As shown, Figure 2 The diagram shows a waveform of a set current provided in an embodiment of this application.

[0061] The second stage, also known as the nucleation stage, plays a crucial role in the SET operation. Specifically, the set current in the second stage primarily serves as the nucleation current. Therefore, when the set current in the second stage is lower than the hold current, the phase-change memory (PCM) is in an oscillating state with a large peak current. When the set current in the second stage is equal to or higher than the hold current, the PCM is in the ON state and can perform effective nucleation.

[0062] Considering that this application determines the holding current of a phase change memory array including multiple phase change memories, and based on the high-low relationship between the holding current and the set current, the holding current can be determined by the set current. Therefore, the range of set currents for performing set operations on the phase change memory array can be obtained. The range of set currents includes multiple set currents, thereby enabling the determination of the holding current of the phase change memory array using multiple set currents.

[0063] Specifically, the set current range corresponding to the second stage of performing a set operation on the phase change memory array can be obtained. The set current range corresponding to the second stage includes multiple set currents corresponding to the second stage.

[0064] As an example, the waveform reference for the set current when performing a set operation on a phase-change memory array. Figure 2 As shown, the set currents for the first stage, second stage, third stage, and fifth stage are different.

[0065] S102, obtain the threshold voltage distribution when multiple set currents within the set current range are applied to the phase change memory array respectively, the threshold voltage distribution is the number of phase change memories corresponding to different read voltages under the same set current.

[0066] In the embodiments of this application, a set current is applied to the phase-change memory (PCM) to perform a set operation, which enables the PCM. At this time, the PCM can be read using a read voltage to obtain the number of PCMs already enabled under the current read voltage. This yields the number of PCMs corresponding to different read voltages under the same set current. The different read voltages and the corresponding number of PCMs constitute a threshold voltage distribution. Therefore, the threshold voltage distribution when multiple set currents within the set current range are applied to the PCM array can be obtained, and the threshold voltage distribution of different set currents can be used to assist in determining the holding current of the subsequent PCM array.

[0067] As one possible implementation, the multiple set currents included in the set current range are obtained based on a preset current interval. The multiple set currents can be iterated over within the set current range at preset current intervals; that is, multiple set currents are applied to the phase-change memory array to perform a set operation, thereby obtaining the threshold voltage distribution when each set current is applied to the phase-change memory array.

[0068] refer to Figure 3 The figure shown is a threshold voltage distribution diagram of a phase memory array under different set currents provided in an embodiment of this application. Figure 3 The horizontal axis represents the threshold voltage (Vt), and the vertical axis represents the number of phase-change memories. Figure 3 The table shows the threshold voltage distribution when the set current is different. Figure 3 In the threshold voltage distribution curve, the set current increases sequentially from blue, red, light green, purple, brown, to dark green. When the set current reaches certain values, the threshold voltage distribution of the phase-change memory array exhibits a noticeable set tail phenomenon. Figure 3 The elliptical indicator section is due to the set current being less than the holding current. When the set current is at certain values, the threshold voltage distribution of the phase change memory array does not show obvious tailing, because the phase change memory is in the on state and can perform good nucleation.

[0069] When any set current is applied to the phase-change memory array, the read voltage range of the phase-change memory array can be obtained. The read voltage range includes multiple read voltages, which can be divided based on a preset voltage interval to obtain multiple read voltages. The number of phase-change memories corresponding to different read voltages when each set current is applied to the phase-change memory array is obtained. Based on the multiple read voltages and the number of phase-change memories corresponding to each read voltage, the threshold voltage distribution is obtained.

[0070] S103: Obtain the target voltage under each set current based on the standard deviation of the threshold voltage distribution corresponding to each set current by a preset multiple.

[0071] In the embodiments of this application, after obtaining the threshold voltage distribution corresponding to each set current, the target voltage under each set current can be obtained according to the standard deviation of the threshold voltage distribution corresponding to each set current by a preset multiple, so as to accurately determine the holding current of multiple phase change memories in the phase change memory array using the target voltage obtained by the preset multiple standard deviation.

[0072] As one possible implementation, the preset multiplier is 3, meaning the target voltage at each set current is obtained using three times the standard deviation of the threshold voltage distribution. Three times the standard deviation is 3σ, and the 3σ principle can be used to ensure that the target voltage at each set current covers most of the phase-change memory components in the phase-change memory array.

[0073] As another possible implementation, the preset multiplier is 3.5, which means that the target voltage at each set current is obtained by using 3.5 times the standard deviation of the threshold voltage distribution. 3.5 times the standard deviation is 3.5σ. Compared with 3σ, 3.5σ can further ensure that the target voltage at each set current can cover most of the phase change memory included in the phase change memory array.

[0074] S104, following the direction of sequential increase of the set current, calculate the voltage difference between the target voltages corresponding to two adjacent set currents within the set current range, and obtain multiple voltage difference values.

[0075] In the embodiments of this application, after obtaining the target voltage under each set current according to the standard deviation of the threshold voltage distribution corresponding to each set current by a preset multiple, a current-voltage (IV) correspondence between the set current and the target voltage can be constructed, and the voltage difference between the target voltages corresponding to two adjacent set currents within the set current range can be calculated in the direction of sequential increase of the set current to obtain multiple voltage differences.

[0076] refer to Figure 4 As shown, Figure 4 This is a schematic diagram of a current-voltage curve provided in an embodiment of this application. Figure 4 The multiple curves in the image represent the current-voltage curves of different phase-change memory arrays. Figure 4 The set current has multiple values, and each set current has a corresponding target voltage. Following the direction of increasing set current, the voltage difference between the target voltages corresponding to adjacent set currents within the set current range is calculated, resulting in multiple voltage difference values. Figure 4 The horizontal axis represents the set current (Iset2) of the second stage, and the vertical axis represents 3.5 times the standard deviation of the threshold voltage (Vt_3.5sigma).

[0077] S105, the set current corresponding to the voltage difference that satisfies the voltage change condition among multiple voltage differences is determined as the holding current of the phase change memory array.

[0078] In the embodiments of this application, after obtaining the voltage difference between the target voltages corresponding to two adjacent set currents within the set current range, the set current corresponding to the voltage difference that satisfies the voltage change condition among multiple voltage differences can be determined as the holding current of the phase change memory array. The voltage change condition can indicate the state change of the phase change memory. That is, when the voltage difference between the target voltages corresponding to two adjacent set currents satisfies the voltage change condition, it means that the two adjacent set currents are the currents closest to the holding current, thereby quickly determining the holding current.

[0079] As one possible implementation, the voltage change condition can be that the largest difference among multiple voltage differences represents a sudden change in the target voltage. Therefore, the target current corresponding to the largest difference among multiple voltage differences can be determined as the holding current of the phase-change memory array, and the target current is the set current corresponding to the subtraction in the calculation of the largest difference. In other words, the latter of the two set currents corresponding to the largest difference is determined as the holding current.

[0080] In practical applications, considering that the voltage difference may be positive or negative, this application specifies that when comparing voltage differences, the absolute values ​​of the voltage differences are compared to determine the maximum difference. Since different set voltages correspond to different target voltages, and the current-voltage curve has an inflection point, the voltage difference after the target voltage rises can be disregarded; that is, the voltage difference with the largest drop in target voltage can be taken as the maximum difference.

[0081] refer to Figure 4 As shown, the voltage difference between the target voltages corresponding to the set currents A and B is the maximum difference within the set current range. Therefore, B can be determined as the holding current of the phase change memory array.

[0082] As another possible implementation, the voltage change condition can be the voltage difference with the largest multiple among multiple voltage differences and the first voltage difference. In this case, the voltage difference with the largest multiple represents the sudden change in the target voltage. Therefore, the target current corresponding to the voltage difference with the largest multiple among multiple voltage differences and the first voltage difference can be determined as the holding current of the phase-change memory array, and the target current is the set current corresponding to the subtraction in the calculation process. That is, the latter of the two set currents corresponding to the voltage difference with the largest multiple among the first voltage differences is determined as the holding current.

[0083] Therefore, this application obtains the target voltage corresponding to the standard deviation of a preset multiple by using the threshold voltage distribution obtained by multiple set currents, and then uses whether the voltage difference between the target voltages meets the voltage change condition to achieve simple, fast, accurate and efficient determination of the holding current of the phase change memory array.

[0084] In the embodiments of this application, the phase-change memory array is divided into multiple electrical regions based on electrical distance, where electrical distance (ED) refers to the distance between the applied unit and the unit to which the set current is applied. The multiple electrical regions may include a near end (NN), a middle end (MM), and a far end (FF). The holding current of the phase-change memory differs in different electrical regions; that is, the holding current of the phase-change memory is affected by the electrical distance.

[0085] As one possible implementation, the holding current of the phase-change memory gradually decreases as the electrical distance increases.

[0086] refer to Figure 5 As shown, Figure 5 This is a schematic diagram of current-voltage curves for different electrical distances provided in an embodiment of this application. Figure 5 The multiple curves represent the current-voltage curves of different phase-change memory arrays, namely chip 1 (D01), chip 2 (D02), chip 3 (D03), chip 4 (D04), and chip 5 (D05). Figure 5 It can be seen that the holding current at the near end is greater than that at the middle end, and the holding current at the middle end is greater than that at the far end. Figure 5 The horizontal axis represents the set current (Iset2) of the second stage, and the vertical axis represents 3.5 times the standard deviation of the threshold voltage (Vt_3.5sigma).

[0087] In the embodiments of this application, before obtaining the set current range for performing a set operation on the phase-change memory array, i.e., before performing the set operation, the number of cycle operations of the phase-change memory array can also be obtained to test the holding current of the phase-change memory array after the number of cycle operations. The cycle operation includes write operations and erase operations; one write operation and one erase operation constitute one cycle operation. In other words, the number of cycle operations for writing and erasing operations performed by the phase-change memory array can be obtained.

[0088] After obtaining the number of loop operations, steps S101-S105 are executed, and the holding current of the phase change memory array is determined as the holding current of the phase change memory array after the number of loop operations.

[0089] As one possible implementation, the holding current of the phase-change memory gradually increases or remains constant as the number of cycle operations increases.

[0090] refer to Figure 6 As shown, Figure 6 A schematic diagram of current-voltage curves for different number of cycle operations provided in an embodiment of this application is shown. Figure 6 The multiple curves represent current-voltage curves for different number of cycle operations, namely 0, 100,000 (100k), 300,000 (300k), 600,000 (600k), and 1,000,000 (1M). Figure 6 It can be seen that when the number of cycles is 0, the holding current is less than when the number of cycles is 100k; when the number of cycles is 100k, the holding current is less than when the number of cycles is 300k; and the holding currents when the number of cycles is 300k, 600k, and 1M are the same. Figure 6 The horizontal axis represents the set current (Iset2) of the second stage, and the vertical axis represents 3.5 times the standard deviation of the threshold voltage (Vt_3.5sigma).

[0091] Therefore, the cyclic operation of the phase-change memory array in this embodiment is simpler and faster than that of TSK. The cyclic performance of the phase-change memory included in the phase-change memory array is also better, enabling more accurate measurement of the hold current after cycling. The method for determining the hold current of the phase-change memory array provided in this embodiment has a short testing time, requires less data, and is simple to process. Regardless of the quality of the phase-change memory, it can accurately measure the hold current in the phase-change memory array.

[0092] Based on the holding current determination method for a phase change memory array provided in the above embodiments, this application also provides a holding current determination device for a phase change memory array, which will be described in detail below with reference to the accompanying drawings.

[0093] See Figure 7 The figure is a schematic diagram of the holding current determination device for a phase change memory array provided in an embodiment of this application.

[0094] The holding current determination device 200 for the phase change memory array provided in this embodiment includes:

[0095] The first acquisition unit 210 is used to acquire the set current range for performing a set operation on the phase change memory array, wherein the phase change memory array includes multiple phase change memories.

[0096] The second acquisition unit 220 is used to acquire the threshold voltage distribution when multiple set currents within the set current range are applied to the phase change memory array, wherein the threshold voltage distribution is the number of phase change memories corresponding to different read voltages under the same set current.

[0097] The third acquisition unit 230 is used to acquire the target voltage under each set current according to the standard deviation of a preset multiple of the threshold voltage distribution corresponding to each set current;

[0098] The calculation unit 240 is used to calculate the voltage difference between the target voltages corresponding to two adjacent set currents within the set current range in the direction of sequential increase of the set current, and obtain multiple voltage difference values.

[0099] The determining unit 250 is used to determine the set current corresponding to the voltage difference that satisfies the voltage change condition among the multiple voltage differences as the holding current of the phase change memory array.

[0100] In some embodiments, the second acquisition unit 220 is configured to:

[0101] Within the set current range, multiple set currents are traversed at preset current intervals.

[0102] Obtain the threshold voltage distribution when each of the set currents is applied to the phase change memory array.

[0103] In some embodiments, the second acquisition unit 220 is configured to:

[0104] Obtain the read voltage range of the phase-change memory array, wherein the read voltage range includes multiple read voltages;

[0105] The number of phase change memories corresponding to different read voltages when each set current is applied to the phase change memory array is obtained, and the threshold voltage distribution is obtained based on the multiple read voltages and the number of phase change memories corresponding to each read voltage.

[0106] In some embodiments, the preset multiple is 3.5.

[0107] In some embodiments, the determining unit 250 is configured to:

[0108] The target current corresponding to the largest difference among the multiple voltage differences is determined as the holding current of the phase change memory array. The target current is the set current corresponding to the subtraction in the calculation of the largest difference.

[0109] In some embodiments, the phase change memory array is divided into multiple electrical regions based on electrical distance; the holding current of the phase change memory in different electrical regions is different.

[0110] In some embodiments, before the first acquisition unit 210 acquires the set current range for performing a set operation on the phase change memory array, the apparatus further includes: a fourth acquisition unit;

[0111] The fourth acquisition unit is used for:

[0112] Obtain the number of cycle operations of the phase-change memory array, wherein the cycle operations include write operations and erase operations;

[0113] Determine unit 250, used for:

[0114] The set current corresponding to the voltage difference that satisfies the voltage change condition among the multiple voltage differences is determined as the holding current of the phase change memory array after the number of cycle operations.

[0115] In some embodiments, the setting operation includes multiple stages, and the multiple stages include a second stage;

[0116] The first acquisition unit 210 is used for:

[0117] Obtain the set current range corresponding to the second stage of performing a set operation on the phase change memory array.

[0118] Based on the holding current determination method for a phase-change memory array provided in the above embodiments, this application also provides a holding current determination device for a phase-change memory array, the holding current determination device for a phase-change memory array comprising:

[0119] The processor and memory may be present, and the number of processors may be one or more. In some embodiments of this application, the processor and memory may be connected via a bus or other means.

[0120] Memory may include read-only memory and random access memory, and provides instructions and data to the processor. A portion of the memory may also include NVRAM. Memory stores the operating system and operating instructions, executable modules, or data structures, or subsets thereof, or extended sets thereof. The operating instructions may include a variety of operation instructions for implementing various operations. The operating system may include various system programs for implementing various basic business functions and handling hardware-based tasks.

[0121] The processor controls the operation of the terminal device; the processor can also be called the CPU.

[0122] The methods disclosed in the embodiments of this application can be applied to a processor or implemented by a processor. A processor can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied as execution by a hardware decoding processor, or as a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0123] This application also provides a computer-readable medium for storing program code that is used to perform any of the methods described in the foregoing embodiments.

[0124] It should be noted that the computer-readable medium described above in this application can be a computer-readable signal medium, a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0125] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0126] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for determining a hold current for a phase change memory array, the method comprising: The method comprises: obtaining a set current range for performing a set operation on a phase change memory array, the phase change memory array comprising a plurality of phase change memories; obtaining a threshold voltage distribution when a plurality of set currents in the set current range are respectively applied to the phase change memory array, the threshold voltage distribution being a number of phase change memories corresponding to different read voltages under a same set current; obtaining a target voltage under each set current according to a preset multiple of a standard deviation of the threshold voltage distribution corresponding to the set current; calculating a voltage difference between target voltages corresponding to two adjacent set currents in the set current range in a direction of sequentially increasing set currents to obtain a plurality of voltage differences; determining a set current corresponding to a voltage difference satisfying a voltage mutation condition in the plurality of voltage differences as a holding current of the phase change memory array. The set operation comprises a plurality of stages, and the plurality of stages comprise a nucleation stage. The obtaining of the set current range for performing the set operation on the phase change memory array comprises: obtaining a set current range corresponding to a nucleation stage of the set operation on the phase change memory array.

2. The method of claim 1, wherein, The obtaining of the threshold voltage distribution when the plurality of set currents in the set current range are respectively applied to the phase change memory array comprises: performing a traversal operation on the plurality of set currents at a preset current interval in the set current range; obtaining the threshold voltage distribution when each set current is applied to the phase change memory array.

3. The method of claim 2, wherein, The obtaining of the threshold voltage distribution when each set current is applied to the phase change memory array comprises: obtaining a read voltage range of the phase change memory array, the read voltage range comprising a plurality of read voltages; obtaining a number of phase change memories corresponding to different read voltages when each set current is applied to the phase change memory array, and obtaining the threshold voltage distribution according to the plurality of read voltages and the number of phase change memories corresponding to each read voltage.

4. The method of claim 1, wherein, The preset multiple is 3.

5.

5. The method of claim 1, wherein, The determination of the set current corresponding to the voltage difference satisfying the voltage mutation condition in the plurality of voltage differences as the holding current of the phase change memory array comprises: determining a target current corresponding to a maximum difference in the plurality of voltage differences as the holding current of the phase change memory array, the target current being a set current corresponding to a subtraction in the calculation of the maximum difference.

6. The method of claim 1, wherein, The phase change memory array is divided into a plurality of electrical regions according to electrical distances; the holding currents of phase change memories in different electrical regions are different.

7. The method according to any one of claims 1 to 6, characterized in that, Before the obtaining of the set current range for performing the set operation on the phase change memory array, the method further comprises: obtaining a number of cycle operations of the phase change memory array, the cycle operation comprising a write operation and an erase operation; The determination of the set current corresponding to the voltage difference satisfying the voltage mutation condition in the plurality of voltage differences as the holding current of the phase change memory array comprises: determining the set current corresponding to the voltage difference satisfying the voltage mutation condition in the plurality of voltage differences as the holding current of the phase change memory array after the number of cycle operations.

8. A hold current determination apparatus for a phase change memory array, comprising: The device comprises: The first acquisition unit is configured to acquire a set current range for performing a set operation on a phase change memory array, the phase change memory array comprising a plurality of phase change memories; the set operation comprises a plurality of stages, and the plurality of stages comprise a nucleation stage; the first acquisition unit is configured to acquire a set current range corresponding to the nucleation stage for performing the set operation on the phase change memory array; The second acquisition unit is configured to acquire a threshold voltage distribution when a plurality of set currents in the set current range are respectively applied to the phase change memory array, the threshold voltage distribution being a number of phase change memories corresponding to different read voltages under the same set current; The third acquisition unit is configured to acquire a target voltage under each set current according to a preset multiple of a standard deviation of the threshold voltage distribution corresponding to each set current. The calculation unit is configured to calculate a voltage difference between target voltages corresponding to two adjacent set currents in the set current range in a direction in which the set currents are sequentially increased, to obtain a plurality of voltage differences. The determination unit is configured to determine a set current corresponding to a voltage difference satisfying a voltage jump condition in the plurality of voltage differences as a holding current of the phase change memory array.

9. A computer readable medium characterized by The computer program product comprises instructions which, when executed on a computer, cause the computer to perform the method of any one of claims 1-7.

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