Phase change memory and control method thereof

Abstract

The application discloses a phase change memory and a control method thereof, and belongs to the technical field of memories. The phase change memory comprises a plurality of local word lines and a plurality of local bit lines; a storage unit array comprising a plurality of array-arranged storage units, each storage unit being coupled between a local word line and a local bit line; a plurality of storage units comprising a target storage unit; a first current mirror structure coupled to the target storage unit through a local bit line; and a second current mirror structure coupled to the target storage unit through a local bit line. The first current mirror structure is configured to apply a first current signal to the target storage unit in a first time period; the first current signal is greater than a holding current of the target storage unit. The second current mirror structure is configured to apply a second current signal to the target storage unit in a second time period; the second current signal is greater than the first current signal. The above scheme can reduce the inrush current during the RESET operation.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a phase-change memory and its control method. Background Technology

[0002] Phase change memory (PCM) is a storage device designed based on the phase change characteristics of chalcogenide materials. PCM relies on the resistance change (phase state change) of the phase change material to store different binary data. Phase change materials possess two phase states: crystalline and amorphous. When the PCM is in its crystalline state, its resistivity is low and its conductivity is good, making it suitable for the SET state of data storage. When the PCM is in its amorphous state, its resistivity is high and its conductivity is poor, making it suitable for the RESET state of data storage. The RESET operation of a PCM can transform the SET state into the RESET state. The specific steps are as follows: a short, high-intensity current pulse is applied. Under Joule heating, the temperature of the PCM exceeds its melting point, causing it to melt. Then, through a rapid heat release quenching process, the PCM changes from a crystalline state to an amorphous state. After the RESET operation, the PCM exhibits a high-resistivity state.

[0003] In related technologies, two voltage signals, low voltage and high voltage, and a large current signal are used to complete the RESET operation. This method has a large inrush current, which can easily damage the storage cells in the phase change memory. Summary of the Invention

[0004] A phase-change memory and its control method are provided to solve the above-mentioned technical problems.

[0005] In a first aspect, a phase-change memory is provided, comprising: Multiple local word lines and multiple local bit lines; A memory cell array includes multiple memory cells arranged in an array, each memory cell being coupled between a local word line and a local bit line; the multiple memory cells include a target memory cell; The first current mirror structure is coupled to the target memory cell through the local bit line; The second current mirror structure is coupled to the target memory cell through the local bit line; The first current mirror structure is configured to: apply a first current signal to the target memory cell during a first time period; the first current signal is greater than the holding current of the target memory cell; The second current mirror structure is configured to: apply a second current signal to the target memory cell during a second time period; the second current signal is greater than the first current signal; and the second time period is after the first time period.

[0006] In some embodiments, the current range of the first current signal Ireset1 includes: 110%×Ih≤Ireset1≤120%×Ih, where Ih represents the holding current of the target memory cell.

[0007] In some embodiments, the plurality of local word lines include target word lines; The phase-change memory further includes: a first switch, the first switch being coupled to the target memory cell via the target word line; The target word line is configured to be subjected to a first voltage signal during the first time period; The first switch is configured to be turned on during the first time period so that a first voltage signal is transmitted to the target memory cell through the target word line.

[0008] In some embodiments, the phase-change memory further includes: a second switch, the second switch being coupled to the target memory cell via the target word line; The target word line is configured to: apply a second voltage signal during the second time period; the second voltage signal is greater than the first voltage signal; The second switch is configured to be turned on during the second time period so that the second voltage signal is transmitted to the target memory cell through the target word line.

[0009] In some embodiments, the plurality of local bit lines include target bit lines, and the target memory cell is coupled between the target word line and the target bit line; The target bit line is configured to have a third voltage signal applied during the first time period and the second time period.

[0010] In some embodiments, the first current mirror structure includes a coupled first reference branch and a first mirror branch; the first mirror branch is coupled to the target memory cell; the first reference branch is used to receive a third current signal. The first current mirror structure is configured to receive a first enable signal during the first time period and operate based on the first enable signal to copy the third current signal to obtain the first current signal.

[0011] In some embodiments, the second current mirror structure includes a coupled second reference branch and a second mirror branch; the second mirror branch is coupled to the target memory cell; the second reference branch is used to receive a fourth current signal; The second current mirror structure is configured to receive a second enable signal during the second time period and operate based on the second enable signal to copy the fourth current signal to obtain the second current signal.

[0012] Secondly, embodiments of this application also provide a control method for a phase-change memory, applied to the phase-change memory described in any of the preceding claims, the method comprising: The target storage unit is determined from multiple storage units; During a first time period, a first current signal is applied to the target memory cell; the first current signal is greater than the holding current of the target memory cell. During a second time period, a second current signal is applied to the target storage unit; the second current signal is greater than the first current signal; the second time period is after the first time period.

[0013] In some embodiments, applying a first current signal to the target memory cell includes: Obtain the third current signal; Based on the first enable signal, the third current signal is copied to obtain a first current signal, and the first current signal is applied to the target storage unit.

[0014] In some embodiments, applying a second current signal to the target memory cell includes: Obtain the fourth current signal; Based on the second enable signal, the fourth current signal is copied to obtain a second current signal, and the second current signal is applied to the target storage unit.

[0015] This application offers the following advantages: The phase-change memory provided in this application divides current control into two stages. A relatively small first current signal is applied through a first current mirror structure in the first time period, and a relatively large second current signal is applied through a second current mirror structure in the second time period, effectively suppressing inrush current during the second time period. Since the first current signal is relatively small, current limiting in the first time period can be avoided. Even when there are multiple target memory cells in different locations, the actual current of each target memory cell remains consistent in the first time period, resulting in better consistency in the RESET effect of the entire memory cell array and contributing to improved lifespan and durability of the phase-change memory. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0018] Figure 1 This is a timing diagram for a phase-change memory. Figure 2 This is a schematic diagram of the structure of a phase-change memory provided in an exemplary embodiment of this disclosure; Figure 3 A schematic diagram of the structure of a phase-change memory provided as an exemplary embodiment of this disclosure; Figure 4 This is a schematic diagram of another phase-change memory provided as an exemplary embodiment of the present disclosure; Figure 5 A schematic diagram of the structure of another phase-change memory provided as an exemplary embodiment of this disclosure; Figure 6 Timing diagram of a phase-change memory provided as an exemplary embodiment of this disclosure; Figure 7 A flowchart of a control method for a phase-change memory provided as an exemplary embodiment of this disclosure.

[0019] Explanation of reference numerals in the attached figures: 11-Local word line; 12-Target word line; 13-Local bit line; 14-Target bit line; 15-Global word line; 16-Intermediate word line; 17-Global bit line; 18-Intermediate bit line; 21-Memory cell; 22-Target memory cell; 31-First current mirror structure; 32-First reference branch; 33-First mirror branch; 34-Second current mirror structure; 35-Second reference branch; 36-Second mirror branch; 41-First switch; 42-Second switch; 43-Third switch; 44-Fourth switch; 45-Fifth switch; 46-Sixth switch. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0021] In the embodiments of this application, "at least one" refers to one or more; "multiple" refers to two or more. In the description of this application, the terms "first," "second," "third," etc., are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance, nor should they be construed as indicating or implying order.

[0022] References such as “one embodiment” or “some embodiments” as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the terms “comprising,” “including,” “having,” and variations thereof, as used in this specification, mean “including, but not limited to,” unless otherwise specifically emphasized.

[0023] In related technologies, phase-change memory (PCM) includes peripheral circuitry, word lines (WL), bit lines (BL), and arrayed memory cells. The peripheral circuitry is coupled to both the word lines and bit lines. Each memory cell is coupled between one word line and one bit line. The peripheral circuitry applies voltage and / or current signals to the memory cells via the word lines and bit lines to complete the RESET operation. The memory cells contain phase-change material. Memory cells closer to the peripheral circuitry are denoted as NN, and the sum of the word line resistance and bit line resistance of NN is relatively small. Memory cells farther from the peripheral circuitry are denoted as FF, and the sum of the word line resistance and bit line resistance of FF is relatively large.

[0024] The timing diagram of the RESET operation in related technologies is as follows: Figure 1As shown, the RESET operation includes a first time period and a second time period. In the first time period, a first voltage signal Vb is applied to the memory cell via the word line; in the second time period, a second voltage signal Vh is applied to the memory cell via the word line. Both the first and second voltage signals Vb and Vh are positive voltage signals, and the second voltage signal Vh is greater than the first voltage signal Vb. In both the first and second time periods, a third voltage signal VN is applied to the memory cell via the bit line. The third voltage signal VN is a negative voltage signal. The total voltage applied to the memory cell is equal to the combined effect of the first voltage signal Vb, the second voltage signal Vh, and the third voltage signal VN. In both the first and second time periods, a current enable signal is provided. When the current enable signal is present, a relatively large and constant fifth current signal Ireset5 is applied to the memory cell. In the first time period, the first voltage signal Vb and the third voltage signal VN work together to form a low-voltage signal, which is used to open memory cells with lower voltage thresholds. In the second time period, the second voltage signal Vh and the third voltage signal VN work together to form a high-voltage signal, which is used to open memory cells with higher voltage thresholds. No operations are performed on the memory cells during the third time period. At this time, the word line voltage is low (VSS, e.g., 0V), the bit line voltage is low (VSS), the current enable signal is low (VSS), and the actual current flowing through the memory cell is 0μA. The solid red line represents the actual current value NN Ireset6 of memory cell NN during the first time period, the solid purple line represents the actual current value FF Ireset6 of memory cell FF during the first time period, the dashed red line represents the actual current value NN Ireset7 of memory cell NN during the second time period, the dashed purple line represents the actual current value FF Ireset7 of memory cell FF during the second time period, and the dashed blue line represents the fifth current signal Ireset5 applied to the memory cell, i.e., the theoretical current value.

[0025] Figure 1 The RESET operation shown has the following technical problems: (1) There is a voltage difference between the first voltage signal Vb and the second voltage signal Vh. Therefore, the voltage switching process from the first voltage signal Vb to the second voltage signal Vh generates an inrush current. The magnitude of the inrush current deviates from Ireset5 and is uncontrollable. (2) Because the fifth current signal Ireset5 is relatively large, while the first voltage signal Vb is relatively low in the first time period, current limiting occurs in the first time period. The actual current passing through the storage unit in the first time period... Determined by the following formula: ,in, Indicates the voltage of the word line. Indicates the voltage of the bit line. This indicates the holding voltage of the memory cell (the minimum voltage that keeps the memory cell open). Represents the resistance of the memory cell. This indicates the resistance on the word line corresponding to the memory cell. This indicates the resistance on the bit line corresponding to the memory cell. The magnitude is affected by the total resistance along the path ( + Due to the influence of ), the storage units in different locations correspond to They are different. The closer a memory cell is to the external circuitry, the smaller the total resistance along its path. The greater the resistance, the higher the total resistance along the path of the memory cell; the farther the memory cell is from the external circuitry, the greater the total resistance along its path. The smaller it is; (3) The magnitude of surge current is affected by voltage difference. The combined effects of RC parasitics and other factors result in varying surge current magnitudes at different locations. Specifically, the actual voltage on the word line at the end of the first time period... Calculated using the following formula: Total resistance along the path ( + The location of the storage unit is closely related to the location of the storage unit, therefore This is closely related to the location of the storage cells. Furthermore, from the first time period to the second time period, the voltage difference... Represented as ,therefore It is also closely related to the location of the storage unit; storage units in different locations have different properties. The differences are significant, and due to the inconsistent RC parasitics at different locations, the surge current varies considerably. The closer the memory cell is to the external circuitry, the larger its surge current; conversely, the farther the memory cell is from the external circuitry, the smaller its surge current, exhibiting a "larger near-end, smaller far-end" characteristic. Figure 1 This manifests as NN Ireset6 being greater than FF Ireset6. Therefore, the near-end memory cell NN is more susceptible to damage from inrush current, and achieving the same reset effect requires more complex compensation at various locations. Furthermore, for the near-end memory cell NN, excessive inrush current can cause write disturbance, and more seriously, may gradually damage the ovonic threshold switch (OTS) and PCM storage material inside the memory cell, affecting the lifespan of the memory cell.

[0026] In view of the technical problems existing in the related technology, such as uncontrollable surge current during RESET operation, inconsistent surge current at different locations, and current limiting in the first time period leading to inconsistent current magnitude at different locations in the first time period, this application provides a phase change memory and its control method to at least partially solve the above-mentioned technical problems.

[0027] See Figure 2 As shown, this application provides a phase-change memory, including: Multiple local word lines 11 and multiple local bit lines 13; The array of storage cells 21 includes a plurality of storage cells 21 arranged in an array, each storage cell 21 being coupled between a local word line 11 and a local bit line 13; the plurality of storage cells 21 include a target storage cell 22; The first current mirror structure 31 is coupled to the target memory cell 22 through the local bit line 13; The second current mirror structure 34 is coupled to the target memory cell 22 through the local bit line 13; The first current mirror structure 31 is configured to: apply a first current signal to the target memory cell 22 during a first time period; the first current signal is greater than the holding current of the target memory cell 22. The second current mirror structure 34 is configured to: apply a second current signal to the target storage cell 22 during a second time period; the second current signal is greater than the first current signal; the second time period is after the first time period.

[0028] It should be noted that, Figure 1 Only one local word line 11, one local bit line 13, and one memory cell 21 are shown; not all of the local word line 11, local bit line 13, and memory cell 21 are shown.

[0029] In some embodiments, the holding current of the target memory cell 22 is the minimum current that keeps the target memory cell 22 in the on state.

[0030] In some embodiments, the current range of the first current signal Ireset1 includes: 110%×Ih≤Ireset1≤120%×Ih, where Ih represents the holding current of the target memory cell 22.

[0031] Through the above embodiments, current control is divided into two stages. A relatively small first current signal is applied through the first current mirror structure 31 in the first time period, and a relatively large second current signal is applied through the second current mirror structure 34 in the second time period, effectively suppressing inrush current during the second time period. Since the first current signal is relatively small, current limiting in the first time period can be avoided. Even when there are multiple target storage units 22, and their positions are different, the actual current of each target storage unit 22 in the first time period can still be guaranteed. There is no difference; the RESET effect of the entire 21-cell array is more consistent, which helps to improve the lifespan and durability of the phase-change memory.

[0032] The phase-change memory and its control method will be explained in detail below with reference to the accompanying drawings.

[0033] In some embodiments, see Figure 3 As shown, the memory cell array 21 includes multiple memory cells 21 arranged in an array, each memory cell 21 being coupled between a local word line 11 (WL) and a local bit line 13 (BL). From the multiple memory cells 21, the memory cell 21 requiring a RESET operation is selected as the target memory cell 22. It should be noted that... Figure 3 The first current mirror structure 31 and the second current mirror structure 34 are not shown. The number of target memory cells 22 can be one or more.

[0034] In some embodiments, see Figure 4 As shown, multiple local word lines 11 include a target word line 12; the phase-change memory further includes a first switch 41, which is coupled to a target memory cell 22 via the target word line 12; the target word line 12 is configured to be applied with a first voltage signal Vb during a first time period; the first switch 41 is configured to be turned on during the first time period so that the first voltage signal Vb is transmitted to the target memory cell 22 via the target word line 12. The first voltage signal Vb is a positive voltage signal.

[0035] In some embodiments, see Figure 4 As shown, the phase-change memory further includes a second switch 42, which is coupled to the target memory cell 22 via a target word line 12. The target word line 12 is configured to have a second voltage signal Vh applied to it during a second time period. The second voltage signal Vh is greater than a first voltage signal Vb. The second switch 42 is configured to be turned on during the second time period, so that the second voltage signal Vh is transmitted to the target memory cell 22 via the target word line 12. The second voltage signal Vh is a positive voltage signal.

[0036] In some embodiments, see Figure 4 As shown, multiple local bit lines 13 include a target bit line 14, and a target memory cell 22 is coupled between the target word line 12 and the target bit line 14; the target bit line 14 is configured to be subjected to a third voltage signal VN during a first time period and a second time period. The third voltage signal VN is a negative voltage signal.

[0037] In some embodiments, the first switch 41 includes a transistor, the second switch 42 includes a transistor, and the third switch 43 includes a transistor.

[0038] In some embodiments, during a first time period, the theoretical voltage value applied to the target memory cell 22 is equal to the first voltage signal Vb minus the third voltage signal VN. During a second time period, the theoretical voltage value applied to the target memory cell 22 is equal to the second voltage signal Vh minus the third voltage signal VN.

[0039] Based on the above embodiments, the first voltage signal Vb is controlled by the first switch 41 and the second voltage signal Vh is controlled by the second switch 42. Only the switch corresponding to the selected target storage cell 22 will be turned on, which can prevent the voltage signal from leaking to other areas and causing leakage current. It can also prevent the unselected storage cell 21 from dividing the voltage and causing RESET failure.

[0040] In some embodiments, see Figure 5 As shown, the first current mirror structure 31 includes a first reference branch 32 and a first mirror branch 33 coupled together; the first mirror branch 33 is coupled to the target storage unit 22; the first reference branch 32 is used to receive a third current signal; the first current mirror structure 31 is configured to: receive a first enable signal in a first time period, and operate based on the first enable signal, copying the third current signal to obtain the first current signal. The first current signal is a mirror signal of the third current signal. The first enable signal is a high-level signal.

[0041] In some embodiments, see Figure 5 As shown, the second current mirror structure 34 includes a coupled second reference branch 35 and a second mirror branch 36; the second mirror branch 36 is coupled to the target storage unit 22; the second reference branch 35 is used to receive a fourth current signal; the second current mirror structure 34 is configured to receive a second enable signal in a second time period, and operate based on the second enable signal to copy the fourth current signal to obtain a second current signal. The second current signal is a mirror signal of the fourth current signal. The second enable signal is a high-level signal.

[0042] In some embodiments, the first reference branch 32 includes a first NMOS (n-metal-oxide-semiconductor) transistor, and the first mirror branch 33 includes a second NMOS transistor. In the first NMOS transistor, the gate and drain are shorted, and the source is grounded. The gate of the first NMOS transistor and the gate of the second NMOS transistor are coupled together. The source of the second NMOS transistor is grounded. The drain of the second NMOS transistor outputs a first current signal. The drain of the first NMOS transistor receives a third current signal.

[0043] In some embodiments, the second reference branch 35 includes a third NMOS (n-metal-oxide-semiconductor) transistor, and the second mirror branch 36 includes a fourth NMOS transistor. The connection method of the third NMOS transistor and the fourth NMOS transistor can be referred to the connection method of the first NMOS transistor and the second NMOS transistor described above, and will not be repeated here.

[0044] Based on the above embodiments, only a third current signal is needed. By inputting this third current signal to multiple first current mirror structures 31 for replication, the replicated first current signal can be used to synchronously control the target memory cell 22 in the array of multiple memory cells 21 to achieve a RESET operation. Similarly, only a fourth current signal is needed. By inputting this fourth current signal to multiple second current mirror structures 34 for replication, the replicated second current signal can be used to synchronously control the target memory cell 22 in the array of multiple memory cells 21 to achieve a RESET operation, effectively simplifying the circuit structure and control difficulty.

[0045] In some embodiments, the current range of the second current signal Ireset2 is 80 microamps to 100 microamps.

[0046] In some embodiments, see Figure 5As shown, the phase-change memory also includes a global word line 15 (gwl), a mid word line 16 (mwl), a global bit line 17, and a mid bit line 18. A first switch 41 is coupled to the global word line 15, a second switch 42 is coupled to the global word line 15, the global word line 15 is coupled to the mid word line 16, the mid word line 16 is coupled to the local word line 11 (specifically, the mid word line 16 is coupled to the target word line 12 within the local word line 11), the local word line 11 is coupled to the target memory cell 22, the target memory cell 22 is coupled to the local bit line 13 (specifically, the target memory cell 22 is coupled to the target bit line 14 within the local bit line 13), the local bit line 13 is coupled to the mid bit line 18, the mid bit line 18 is coupled to the global bit line 17, and the global bit line 17 is coupled to the first current mirror structure 31 and the second current mirror structure 34, respectively. The intermediate bit line 18 serves a dual function as both a "local data line (ldl)" and a "bit line." During write operations (RESET and SET operations), the intermediate bit line 18 functions as a bit line, transmitting voltage signals. For example, during a RESET operation, the intermediate bit line 18 transmits the third voltage signal VN to the target memory cell 22. During read operations, the intermediate bit line 18 functions as a local data line, transmitting the binary data read from the target memory cell 22 to the external control module via the intermediate bit line 18. The global bit line 17 also serves a dual function as a "global data line (dl)" and a "bit line." During a RESET operation, both the global bit line 17 and the intermediate bit line 18 transmit the third voltage signal VN to the target memory cell 22. During read operations, the binary data read from the target memory cell 22 is transmitted to the external control module via the intermediate bit line 18 and the global bit line 17.

[0047] In some embodiments, without considering the voltage division of wires and switches along the path, the voltage of global word line 15 = the voltage of intermediate word line 16 = the voltage of local word line 11. Without considering the voltage division of wires and switches along the path, the voltage of global bit line 17 = the voltage of intermediate bit line 18 = the voltage of local bit line 13.

[0048] In some embodiments, see Figure 5As shown, the phase-change memory also includes a third switch 43 and a fourth switch 44. The third switch 43 is coupled between the global word line 15 and the intermediate word line 16. The fourth switch 44 is coupled between the intermediate word line 16 and the local word line 11. The third switch 43 includes a transistor, and the fourth switch 44 includes a transistor. During the first time period and the second time period, both the third switch 43 and the fourth switch 44 are turned on, so that the first voltage signal Vb is transmitted sequentially through the global word line 15, the intermediate word line 16, and the local word line 11 to the target memory cell 22, and the second voltage signal Vh is transmitted sequentially through the global word line 15, the intermediate word line 16, and the local word line 11 to the target memory cell 22.

[0049] In some embodiments, see Figure 5 As shown, the phase-change memory also includes a sixth switch 46 and a fifth switch 45. The sixth switch 46 is coupled between the local bit line 13 and the intermediate bit line 18. The fifth switch 45 is coupled between the intermediate bit line 18 and the global bit line 17. The fifth switch 45 includes a transistor, and the sixth switch 46 includes a transistor. During the first time period and the second time period, both the fifth switch 45 and the sixth switch 46 are turned on, so that the third voltage signal VN is transmitted sequentially through the global bit line 17, the intermediate bit line 18, and the local bit line 13 to the target memory cell 22.

[0050] In some embodiments, a controllable direct current (DC) is used to perform the RESET operation, making the RESET current more controllable.

[0051] In some embodiments, Figure 6 This is a timing diagram illustrating the control method for the phase-change memory provided in this application.

[0052] See Figure 6 As shown, during the first time period, a first voltage signal Vb is applied to the target word line 12, and a third voltage signal VN is applied to the local target bit line 14. The first current mirror structure 31 receives a first enable signal. Upon receiving the first enable signal, the first current mirror structure 31 operates and copies the third current signal to obtain the first current signal.

[0053] Continue reading Figure 6 As shown, during the second time period, a second voltage signal Vh is applied to the target word line 12, and a third voltage signal VN is applied to the target bit line 14. The second current mirror structure 34 receives a second enable signal. Upon receiving the second enable signal, the second current mirror structure 34 operates and replicates the fourth current signal to obtain the second current signal.

[0054] Continue reading Figure 6As shown, during the third time period, no operation is performed on the target memory cell 22, the voltage of the target word line 12 is low level VSS (e.g., 0V), the voltage of the target bit line 14 is low level VSS, the first enable signal is low level VSS, and the second enable signal is low level VSS.

[0055] Continue reading Figure 6 As shown, the first current value Ireset1 connected in the first time period is slightly greater than the holding current Ih, so there will be no current limiting in the first time period. The actual current of the target storage unit 22 at different locations is... They are all equal, that is, in the later part of the first time period, the actual currents of NN and FF are equal. Since both Ireset1 and Ih are equal, the RESET effect across the entire array of memory cells 21 is more consistent. In the second time period, the current value passing through the target memory cell 22 is equal to Ireset2, eliminating inrush current. Furthermore, because Ireset1 is a relatively small current value, It is also a relatively small current value.

[0056] When switching from the first time period to the second time period, the presence or absence of surge current is affected by the voltage switching of the word line direction. The smaller the voltage difference between Vh and Vb, the smaller the surge current.

[0057] Specifically, due to It is a relatively small current value, thus improving the voltage division from global word line 15 to target word line 12, resulting in a smaller voltage change. The voltage value on target word line 12 at the end of the first time period is expressed as: R represents the resistance along the transmission path of the first voltage signal Vb. Since... The voltage difference between the first and second time periods is relatively high, thus reducing inrush current. Then, a controllable second current signal is applied during the second time period, utilizing the heat generated by this signal to complete the reset operation. Because inrush current and write interference are effectively suppressed, the lifespan of the phase-change memory is extended.

[0058] In some embodiments, see Figure 7 As shown, this application provides a control method for a phase-change memory, applied to the phase-change memory as described in any of the above embodiments, the method comprising: S101: Determine the target storage cell 22 from the plurality of storage cells 21; S102: In the first time period, a first current signal is applied to the target memory cell 22; the first current signal is greater than the holding current of the target memory cell 22; S103: In the second time period, a second current signal is applied to the target storage unit 22; the second current signal is greater than the first current signal; the second time period is after the first time period.

[0059] In some embodiments, applying a first current signal to the target storage unit 22 specifically includes: acquiring a third current signal; copying the third current signal based on a first enable signal to obtain a first current signal, and applying the first current signal to the target storage unit 22.

[0060] Specifically, the third current signal can be copied using the first current mirror structure 31.

[0061] In some embodiments, applying a second current signal to the target storage unit 22 specifically includes: acquiring a fourth current signal; copying the fourth current signal based on a second enable signal to obtain a second current signal, and applying the second current signal to the target storage unit 22.

[0062] Specifically, the fourth current signal can be replicated using the second current mirror structure 34.

[0063] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0064] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A phase-change memory, characterized in that, include: Multiple local word lines (11) and multiple local bit lines (13); The storage cell (21) array includes a plurality of storage cells (21) arranged in an array, each of the storage cells (21) being coupled between a local word line (11) and a local bit line (13); the plurality of storage cells (21) include a target storage cell (22); The first current mirror structure (31) is coupled to the target memory cell (22) through the local bit line (13); The second current mirror structure (34) is coupled to the target memory cell (22) through the local bit line (13); The first current mirror structure (31) is configured to apply a first current signal to the target memory cell (22) during a first time period; The first current signal is greater than the holding current of the target memory cell (22); The second current mirror structure (34) is configured to apply a second current signal to the target storage cell (22) during a second time period; the second current signal is greater than the first current signal; and the second time period is after the first time period.

2. The phase-change memory according to claim 1, characterized in that, The current range of the first current signal Ireset1 includes: 110%×Ih≤Ireset1≤120%×Ih, where Ih represents the holding current of the target memory cell (22).

3. The phase-change memory according to claim 1, characterized in that, The multiple local character lines (11) include the target character line (12); The phase-change memory further includes a first switch (41), which is coupled to the target memory cell (22) via the target word line (12); The target word line (12) is configured to be subjected to a first voltage signal during the first time period; The first switch (41) is configured to be turned on during the first time period so that a first voltage signal is transmitted to the target memory cell (22) through the target word line (12).

4. The phase-change memory according to claim 3, characterized in that, Also includes: The second switch (42) is coupled to the target memory cell (22) via the target word line (12); The target word line (12) is configured to: be subjected to a second voltage signal during the second time period; the second voltage signal is greater than the first voltage signal; The second switch (42) is configured to be turned on during the second time period so that the second voltage signal is transmitted to the target memory cell (22) through the target word line (12).

5. The phase-change memory according to claim 3, characterized in that, The plurality of local bit lines (13) include a target bit line (14), and the target memory cell (22) is coupled between the target word line (12) and the target bit line (14); The target bit line (14) is configured to be subjected to a third voltage signal during the first time period and the second time period.

6. The phase-change memory according to any one of claims 1 to 5, characterized in that, The first current mirror structure (31) includes a first reference branch (32) and a first mirror branch (33) coupled together; the first mirror branch (33) is coupled to the target storage unit (22); the first reference branch (32) is used to access a third current signal; The first current mirror structure (31) is configured to receive a first enable signal during the first time period and operate based on the first enable signal to copy the third current signal to obtain the first current signal.

7. The phase-change memory according to any one of claims 1 to 5, characterized in that, The second current mirror structure (34) includes a coupled second reference branch (35) and a second mirror branch (36); the second mirror branch (36) is coupled to the target storage unit (22); the second reference branch (35) is used to receive a fourth current signal; The second current mirror structure (34) is configured to receive a second enable signal during the second time period and operate based on the second enable signal to copy the fourth current signal to obtain the second current signal.

8. A control method for a phase-change memory, applied to the phase-change memory as described in any one of claims 1 to 7, characterized in that, The method includes: The target storage cell (22) is determined from multiple storage cells (21); During a first time period, a first current signal is applied to the target memory cell (22); the first current signal is greater than the holding current of the target memory cell (22); During the second time period, a second current signal is applied to the target storage unit (22); the second current signal is greater than the first current signal; the second time period is after the first time period.

9. The control method for the phase-change memory according to claim 8, characterized in that, Applying a first current signal to the target storage cell (22) includes: Obtain the third current signal; Based on the first enable signal, the third current signal is copied to obtain the first current signal, and the first current signal is applied to the target storage unit (22).

10. The control method for the phase-change memory according to claim 8, characterized in that, Applying a second current signal to the target storage cell (22) includes: Obtain the fourth current signal; Based on the second enable signal, the fourth current signal is copied to obtain a second current signal, and the second current signal is applied to the target storage unit (22).

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