Resistive random access memory with low set and reset transient power and method of making the same

Abstract

The application relates to a low SET and RESET transient power resistive change memory and a preparation method thereof, which comprises a substrate layer (Si / SiO2), an adhesion layer (Ti), a bottom electrode layer (Pt), a current-limiting layer (SiO2), a resistive change layer (TaON) and an upper electrode layer (TiN) which are sequentially stacked. The application provides a low SET and RESET transient power resistive change memory with a TiN / TaON / SiO2 / Pt structure. The SiO2 prepared by PECVD is used as the current-limiting layer to prevent the resistive change layer from forming thick conductive wires and to prevent large current from being generated. The SiO2 prepared by PECVD contains more defects, and the electrons can be injected into the SiO2 film; the defects in the SiO2 film can be used as traps to capture the electrons; and with the gradual enhancement of the applied electric field, the electrons captured by the traps jump to participate in conduction.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor microelectronic devices. It relates to a resistive switching memory with low SET and RESET instantaneous power and its fabrication method. Specifically, it proposes a resistive switching memory with a structure of TiN / TaON / SiO2 / Pt and relates to its fabrication method. Background Technology

[0002] In the 1960s, Simmons et al. discovered a phenomenon of abrupt resistance changes in SiOx materials. In 2000, Liu et al. reported that a device fabricated from a thin-film metal material exhibited excellent resistance switching characteristics under pulse stimulation. Subsequently, more and more people began to study resistive random access memory (IRRAM), including many large semiconductor electronics design companies such as Samsung, IBM, and Toshiba. IRRAM utilizes the switching between different resistance states of the thin-film material—high resistance state (HRS) and low resistance state (LRS)—under an applied voltage to achieve data storage. Since different high and low configurations externally represent logic "1" and logic "0," thus realizing data storage, the high resistance state (HRS) and low resistance state (LRS) of IRRAM can be maintained for a long time after the power is cut off. This is one of the important properties that makes IRRAM a non-volatile memory.

[0003] The process of a resistive random access memory (IRRAM) transitioning from a high-resistivity state (HRS) to a low-resistivity state (LRS) is called the SET process, also known as the set process. The transition from a low-resistivity state to a high-resistivity state is called the RESET process, also known as the reset process. After fabrication, the IRRAM exhibits relatively high resistance, requiring an initial voltage to return it to the LRS state; this process is called the Forming process. A common IRRAM structure is a "sandwich" structure (MIM)—where the top and bottom electrodes are metal, and the middle layer, also called the resistive switching layer, is an insulator.

[0004] Resistive random access memory (RRAM) has advantages such as small cell size, fast read / write speed, low programming voltage, low power consumption, compatibility with CMOS fabrication process, and simple device structure, making it one of the most promising new types of memory for the future. Summary of the Invention

[0005] To address the aforementioned technical issues, a resistive switching memory with low SET and RESET instantaneous power and its fabrication method are provided.

[0006] The solution of the present invention is:

[0007] A resistive switching memory with low SET and RESET instantaneous power includes a substrate layer (Si / SiO2), an adhesion layer (Ti), a bottom electrode layer (Pt), a current-limiting layer (SiO2), a resistive switching layer (TaON), and a top electrode layer (TiN) stacked sequentially.

[0008] Preferably, the thickness of the adhesive layer is The thickness of the bottom electrode layer (Pt) is The thickness of the flow-limiting layer is The thickness of the resistive switching layer (TaON) is The thickness of the upper electrode layer (TiN) is

[0009] Preferably, the substrate is a Si / SiO2 conductor substrate, the adhesion layer is Ti, the bottom electrode layer is Pt, the current limiting layer is SiO2, the resistive switching layer is TaON, and the top electrode layer is TiN.

[0010] The method for fabricating the low SET and RESET instantaneous power resistive switching memory includes the following steps:

[0011] S1. Wafer preparation: Prepare silicon wafers and clean them to remove dust.

[0012] S2. Preparation of SiO2 semiconductor substrate after sulfuric acid cleaning: The substrate layer is grown by thermal oxidation process on the silicon wafer surface;

[0013] S3. Preparation of adhesion layer: Magnetron sputtering of metallic Ti as an adhesion layer to connect the SiO2 semiconductor substrate and the bottom electrode Pt;

[0014] S4. Fabrication of the bottom electrode: Magnetron sputtering of metal Pt as the bottom electrode of the SiO2 / TaON double-layer resistive switching memory;

[0015] S5, PECVD preparation of the current-limiting layer;

[0016] S6. Fabrication of resistive switching layer: TaON is sputtered using magnetron-RF sputtering;

[0017] S7, magnetron sputtering of TiN, with Ar and N2 gases introduced;

[0018] S8 and AME etching, with Cl2 as the etching gas, form a connection hole for the bottom electrode lead-out;

[0019] S9. Photolithographic stripping to form discrete resistive switching memory devices.

[0020] Preferably, the conditions for step S3, magnetron-RF sputtering, are: the background vacuum is not greater than 3.2 × 10⁻⁶. -4 Pa, working pressure not exceeding 0.5Pa, sputtering power 50W~100W;

[0021] The conditions for step S4, magnetron-RF sputtering, are: background vacuum not greater than 3.2 × 10⁻⁶. -4 Pa, working pressure not exceeding 2.4 Pa.

[0022] Preferably, the conditions for magnetron-RF sputtering in step S6 are as follows: inert gases Ar, O2, and N2 are introduced, with a volume ratio of Ar:(1.5-10):20, 3 mTorr to 10 mTorr, sputtering power of 50 W to 100 W, and the target material is Ta2O5.

[0023] Preferably, the conditions for magnetron-RF sputtering in step S7 are: the ratio of Ar to N2 in the introduced gas is (16-20):2, and the background vacuum is no greater than 3.2 × 10⁻⁶. -4 Pa, working pressure not exceeding 2.4 Pa, N2 flow rate of reaction gas 20 sccm~25 sccm, target material is Ti.

[0024] Beneficial effects of this invention:

[0025] 1. A resistive switching memory with low SET and RESET instantaneous power of TiN / TaON / SiO2 / Pt structure was proposed. 2. PECVD-prepared SiO2 was used as a current-limiting layer to prevent the formation of thick conductive filaments in the resistive switching layer, thus preventing the generation of large currents. PECVD-prepared SiO2 contains many defects, allowing electrons to be injected into the SiO2 film. These defects act as traps, capturing electrons. As the applied electric field gradually increases, these trapped electrons undergo transitions and participate in conduction.

[0026] 3. The TiN / TaON / SiO2 / Pt resistive switching device exhibits good line overlap after 100 DC scans, indicating good uniformity and a smooth resistive switching process without degradation. Furthermore, the device demonstrates bipolar resistive switching characteristics and stable switching capabilities without undergoing a forming process. Attached Figure Description

[0027] Figure 1 Schematic diagram of the resistive random access memory structure of this invention;

[0028] Figure 2 Flowchart of the fabrication process of the TiN / TaON / SiO2 / Pt resistive switching memory of the present invention;

[0029] Figure 3 DC test results of the TiN / TaON / SiO2 / Pt resistive switching memory prepared in Example 1;

[0030] Figure 4 The DC test results are for the resistive random access memory prepared in Example 2;

[0031] Figure 5 The DC test results are for the resistive random access memory prepared in Example 3;

[0032] Figure 6 The LRS statistical distribution of the resistive switching memory prepared in Example 3;

[0033] Figure 7 The HRS statistical distribution of the resistive switching memory prepared in Example 3. Detailed Implementation

[0034] The present invention will be further illustrated below with reference to the embodiments, but the scope of protection of the present invention is not limited to the scope described in the embodiments.

[0035] Example 1

[0036] like Figure 1 A resistive switching memory with low SET and RESET instantaneous power includes a substrate layer (SiO2), an adhesion layer (Ti), a bottom electrode layer (Pt), a current-limiting layer (SiO2), a resistive switching layer (TaON), and a top electrode layer (TiN) stacked sequentially.

[0037] The method for fabricating a resistive switching memory with low SET and RESET instantaneous power is described above.

[0038] 1. Wafer preparation: Prepare n(100) crystal orientation 4-inch silicon wafers and clean the silicon wafers to remove dust;

[0039] 2. Preparation of SiO2 semiconductor substrate after sulfuric acid cleaning at room temperature: Growth of 4-inch silicon wafers using thermal oxidation process.

[0040] 3. Preparation of the adhesion layer: magnetron sputtering Metallic Ti is used as an adhesion layer to connect the SiO2 semiconductor substrate and the bottom electrode Pt, with a base vacuum of 3.2 × 10⁻⁶. -4 Pa, working pressure 0.5 Pa, sputtering power 100 W;

[0041] 4. Fabrication of the bottom electrode: magnetron sputtering Metallic Pt is used as the bottom electrode (BE) of a SiO2 / TaON double-layer resistive switching memory, with a base vacuum of 3.2 × 10⁻⁶. -4 Pa, working pressure 2.4 Pa;

[0042] 5. Preparation of SiO2 using SiH4 and N2O via PECVD process

[0043] 6. Fabrication of resistive switching layer: TaON is fabricated using physical vapor deposition and radio frequency sputtering. Inert gases Ar, O2, and N2 are introduced at 6 mTorr. The volume ratio of Ar, O2, and N2 is 40:6:20, the oxygen partial pressure ratio is 18%, the sputtering power is 100W, and the target material is a φ60×3mm ceramic target Ta2O5.

[0044] 7. Magnetron sputtering The ratio of Ar to N2 gas was 18:2, the target material was Ti, and the base vacuum was 3.2 × 10⁻⁶. -4 Pa, working pressure 2.4 Pa, reaction gas N2 flow rate 20 sccm;

[0045] 8. AME etching, with Cl2 (chlorine) as the etching gas, to form the bottom electrode lead-out hole;

[0046] 9. Photolithography stripping is used to form discrete resistive switching memory devices.

[0047] The TiN / TaON / SiO2 / Pt resistive switching device prepared in this embodiment, under 100 DC scans, as... Figure 3 As shown in the figure, the good overlap of the curves indicates good uniformity of the resistive switching device, demonstrating a smooth resistive switching process without degradation. Furthermore, the resistive switching device exhibits bipolar resistive switching characteristics and can stably switch without undergoing a forming process. The VSET of the resistive switching device is 5.7V, VRESET is -5.4V, the instantaneous power during SET is 28.5μW, and the instantaneous power during RESET is 5.4μW. This indicates that the TiN / TaON / SiO2 / Pt resistive switching device has lower power consumption than the TiN / TaON / Pt resistive switching device.

[0048] Example 2

[0049] Unlike Example 1, this example does not use SiO2 as a current-limiting layer; otherwise, it is the same as Example 1. The resistive switching device was obtained after 50 DC scans, as shown... Figure 4 As shown.

[0050] like Figure 4 As shown, without SiO2 as a current-limiting layer, the resistive switching device does not exhibit resistive switching characteristics under small current-limiting conditions; it can only exhibit resistive switching characteristics under a current-limiting condition of 1mA.

[0051] Example 3

[0052] The difference from Example 1 is that the volume ratio of Ar, O2, and N2 in the resistive switching layer prepared in step 6 is changed. The volume ratios of Ar, O2, and N2 are 40:1.5:20 for sample 1#, 40:3:20 for sample 2#, and 40:3:20 for sample 3#, while other parameters remain the same as in Example 1. The resistive switching device was then tested under 100 DC scans. Figure 6-7 As shown.

[0053] like Figure 6-7 As shown, sample #1 has relatively higher homogeneity compared to samples #2 and #3 due to the change in gas volume ratio.

Claims

1. A resistive switching memory with low SET and RESET instantaneous power, characterized in that: It includes a substrate layer, an adhesion layer, a bottom electrode layer, a current-limiting layer, a resistive switching layer, and an upper electrode layer stacked sequentially. The substrate is a Si / SiO2 conductor substrate, the adhesion layer is Ti, the bottom electrode layer is Pt, the current limiting layer is a 60Å SiO2 layer prepared by PECVD using SiH4 and N2O, the resistive switching layer is TaON, and the top electrode layer is TiN.

2. The resistive switching memory with low SET and RESET instantaneous power according to claim 1, characterized in that: The thickness of the adhesion layer is 100 Å to 300 Å, the thickness of the bottom electrode layer is 800 Å to 1000 Å, the thickness of the current-limiting layer is 60 Å to 100 Å, the thickness of the resistive switching layer is 100 Å to 200 Å, and the thickness of the top electrode layer is 500 Å to 700 Å.

3. The method for fabricating the resistive switching memory with low SET and RESET instantaneous power according to any one of claims 1-2, characterized in that: S1. Wafer preparation: Prepare silicon wafers and clean them to remove dust. S2. Preparation of SiO2 semiconductor substrate after sulfuric acid cleaning: The substrate layer is grown by thermal oxidation process on the silicon wafer surface; S3. Preparation of adhesion layer: Magnetron sputtering of metallic Ti as an adhesion layer to connect the SiO2 semiconductor substrate and the bottom electrode Pt; S4. Fabrication of the bottom electrode: Magnetron sputtering of metal Pt as the bottom electrode of the SiO2 / TaON double-layer resistive switching memory; S5, PECVD preparation of the current-limiting layer; S6. Fabrication of resistive switching layer: TaON is sputtered by magnetron-RF sputtering; S7, magnetron sputtering of TiN, with Ar and N2 gases introduced; S8 and AME etching, with Cl2 as the etching gas, form a connection hole for the bottom electrode lead-out; S9. Photolithographic stripping to form discrete resistive switching memory devices.

4. The method for fabricating a resistive switching memory with low SET and RESET instantaneous power according to claim 3, characterized in that: The conditions for step S3, magnetron-RF sputtering, are: the background vacuum is no greater than 3.2 × 10⁻⁶. -4 Pa, working pressure not exceeding 0.5Pa, sputtering power 50W~100W; The conditions for step S4, magnetron-RF sputtering, are: background vacuum not greater than 3.2 × 10⁻⁶. -4 Pa, working pressure not exceeding 2.4 Pa.

5. The method for fabricating a resistive switching memory with low SET and RESET instantaneous power according to claim 3, characterized in that: The conditions for magnetron-RF sputtering in step S6 are as follows: inert gases Ar, O2, and N2 are introduced, with a volume ratio of Ar:(1.5-10):20, 3 mTorr~10 mTorr, sputtering power of 50 W~100 W, and the target material is Ta2O5.

6. The method for fabricating a resistive switching memory with low SET and RESET instantaneous power according to claim 3, characterized in that: The conditions for magnetron-RF sputtering in step S7 are as follows: the ratio of Ar to N2 in the introduced gas is (16-20):2, and the background vacuum is no greater than 3.2 × 10⁻⁶. -4 Pa, working pressure not exceeding 2.4 Pa, N2 flow rate of reaction gas 20 sccm~25 sccm, target material is Ti.

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