A low-resource FPGA multi-axis current loop

Abstract

The present invention relates to a low-resource FPGA multi-axis current loop, comprising a current loop operation module, a data access scheduling module, a parameter access module and a variable access module; the current loop operation module is used for feedback input quantity conditioning and current loop operation; the data access scheduling module is used for selecting the feedback input quantity of the output current loop operation module and receiving the calculation results of each axis output by the current loop operation module; it is used to control the access timing and access action of the parameter access module and the variable access module; the parameter access module is used for accessing the parameters required for the current loop operation of each axis; the variable access module is used for accessing the variables in the current loop operation process of each axis; wherein the parameter access module and the variable access module both use the RAM resources inside the FPGA to store data and use two-level buffer registers for access caching, and data access and current loop operation are performed in parallel. The present invention further reduces the resources required for FPGA to realize multi-axis synchronous current loop without increasing the control time.

Description

Technical Field

[0001] The present invention relates to the field of motors, and in particular to a low-resource FPGA multi-axis current loop. Background Art

[0002] The inherent hysteresis control characteristics, slow processing speed and insufficient on-chip resources of traditional processor (MCU / ARM / DSP) software-based motor control systems are increasingly restricting the improvement of motor drive control performance. FPGA has developed rapidly in the field of industrial control in recent years due to its inherent speed and resource advantages. Generally speaking, the current loop control of AC motors is fixed, repeatable and reproducible, so the use of FPGA to implement the current loop has become popular in servo control systems. On the one hand, it improves the performance of the current loop, and on the other hand, it releases processor (MCU / ARM / DSP) resources, so that the speed loop and position loop can achieve higher performance.

[0003] In the multi-axis servo control scheme, there are many ways to use FPGA to realize multi-axis synchronous current loop. The amount of FPGA resources consumed and the length of time required for implementation are two main factors in evaluating its performance.

[0004] The prior art only considers reusing the operation part of the current loop control algorithm, which is a generally conceivable method. However, in the traditional FPGA to implement multi-axis current loop reuse design, register storage is used to store the parameters required for the current loop operation of each axis and the variables in the operation process of each axis, which is specifically reflected in the following two aspects: (1) The parameters corresponding to the current loop operation of each axis (such as adjustment parameters, motor parameters), current instructions, control signals, etc. cannot be reused, and this information is stored in the register of the FPGA. It is well known that the register resources of the FPGA are precious and relatively scarce; (2) Since a single current loop operation module is repeatedly called and applied to multiple axes, the variables in the operation process of each axis also need to add additional registers for caching.

[0005] Although using registers to store data can be updated immediately and used at any time, due to the special architecture of FPGA's combination of registers and lookup tables (LUTs), a disproportionate increase in registers will also cause unused lookup table (LUT) resources to be occupied, and this phenomenon will become more serious as the number of axes increases, which can easily lead to FPGA resource shortages. Figure 1 Taking traditional parameter reading as an example, the required register resources increase in direct proportion to the number of axes. That is, the above (1) and (2) contents will still increase the resources consumed by the FPGA as the number of controlled axes increases. Summary of the invention

[0006] The purpose of the present invention is to provide a low-resource FPGA multi-axis current loop, which further reduces the resources required for FPGA to implement a multi-axis synchronous current loop without increasing the control time, so that the FPGA resource consumption does not increase with the increase in the number of axes.

[0007] In order to solve the above technical problems, the technical solution of the present invention is: a low-resource FPGA multi-axis current loop, comprising:

[0008] Current loop operation module: used for conditioning of feedback input quantity and current loop operation;

[0009] Data access scheduling module: used to select the feedback input quantity of the output current loop operation module and receive the calculation results of each axis output by the current loop operation module; used to control the access timing and access action of the parameter access module and the variable access module;

[0010] Parameter access module: used to access the parameters required for the current loop calculation of each axis;

[0011] Variable access module: used to access the variables in the current loop operation process of each axis;

[0012] Among them, the parameter access module and the variable access module both use the RAM resources inside the FPGA to store data; the parameter access module and the variable access module both use two-level buffer registers to access the data cache, and data access and current loop operations are performed in parallel.

[0013] Furthermore, the current loop operation module is time-division multiplexed. When the current loop operation start signal of this cycle arrives, the current loop operation of the first axis is performed. When the current loop operation of the current axis is completed, the current loop operation of the next axis is immediately started until all axis operations are completed.

[0014] Furthermore, the current loop operation module is suitable for a pipeline structure, and the current loop operation module is divided into several steps. When the current loop operation start signal of this cycle arrives, the first step operation of the first axis is performed. When the first step operation of the first axis is completed, the second step operation of the first axis is started immediately, and the first step operation of the second axis is started immediately, and so on, until all steps of all axes are completed.

[0015] Furthermore, the two-level buffer register is divided into a primary buffer register and a secondary buffer register according to the signal flow direction; the data access scheduling module selects the output RAM read address according to the current loop multiplexing order, and caches the read data to the primary buffer register; the data access scheduling module controls the primary buffer register to output the current cached data to the secondary buffer register before caching the next axis data.

[0016] Further, the parameter access module includes a parameter RAM, a parameter primary buffer register group and a parameter secondary buffer register group;

[0017] The parameter RAM is used to store the parameters required for the current loop operation of all axes. The parameter RAM is a dual-port RAM, one end of which is used for the processor to write parameters, and the other end is used for the FPGA current loop operation module to read parameters;

[0018] The parameter level 1 buffer register group is used to store the parameters read by the parameter RAM in real time;

[0019] The parameter secondary buffer register group is used to cache the current axis parameters;

[0020] The reading time of the parameter RAM and the updating time of the parameter primary buffer register group and the parameter secondary buffer register group are controlled by the control signal output by the data access scheduling module, specifically:

[0021] Parameter writing process: The microprocessor completes the update of each axis parameter before the current loop enable signal arrives in each control cycle, and the parameter RAM partition stores the parameters of each axis;

[0022] Parameter reading process: The data access scheduling module reads the parameters of the next current loop operation axis in advance at the start of the current loop operation of the current axis according to the order of the current loop multiplexing axes, and puts the read data into the parameter first-level buffer register group; when the current loop operation of the current axis ends, that is, when the current loop operation of the next axis starts, the data of the parameter first-level buffer register group is updated to the parameter second-level buffer register group for use by the next axis current loop operation.

[0023] Further, the variable access module includes a variable RAM, a write variable primary buffer register group, a write variable secondary buffer register group, a read variable primary buffer register group, and a read variable secondary buffer register group;

[0024] The variable RAM is used to store the variables of all axis current loop operation processes. The variable RAM is a dual-port RAM, one end of which is used for the current loop operation module to write variables, and the other end is used for the current loop operation module to read variables;

[0025] The first-level buffer register group of write variables is used to store the real-time variables of the current axis, and the second-level buffer register group of write variables is used to cache the variables of the previous axis;

[0026] The read variable primary buffer register group is used to store the variables read by the variable RAM in real time, and the read variable secondary buffer register group is used to cache the variables of the current axis;

[0027] The access time of the variable RAM and the update time of the buffer are controlled by the control signal output by the data access scheduling module, specifically:

[0028] Variable writing process: The current loop operation module stores the variables in the primary buffer register group of the write variables in real time during the current loop operation of the current axis; at the end of the current loop operation of the current axis, the data in the primary buffer register group of the write variables is updated to the secondary buffer register group of the write variables, and then the data access scheduling module controls the data in the secondary buffer register group of the write variables to be written into the corresponding axis area of ​​the variable RAM for reading in the next cycle;

[0029] Variable reading process: The data access scheduling module reads the variables of the next current loop operation axis at the start of the current loop operation of the current axis according to the order of the current loop multiplexing axes, and puts the read data into the variable first-level buffer register group; when the current axis current loop operation ends, the data of the variable first-level buffer register group is updated to the variable second-level buffer register group for use by the next axis current loop operation.

[0030] The present invention has the following beneficial effects:

[0031] The present invention proposes a control method for further reducing the resources required for FPGA to realize multi-axis synchronous current loop without increasing the control time, so that the FPGA resource consumption does not increase with the increase of the number of axes. Taking full advantage of the characteristic that the rich RAM resources inside the FPGA are rarely used when the FPGA is applied to servo control, the present invention adopts the rich RAM resource access method inside the FPGA to store the parameters required for the current loop operation of each axis, as well as the variables in the operation process of each axis, without occupying the register resources of the FPGA. However, the further introduced problem is that the parameters or variables are stored in the RAM, and access requires extra time. In order not to affect the original control time, the present invention proposes a method for caching data access and current loop operation in parallel, and using a two-level buffer register to access the data, avoiding data competition caused by real-time reading, ensuring the reliability and real-time performance of multi-axis control, and realizing the access of multi-axis information. Theoretically, it can be extended to unlimited axes, and according to the multi-axis timing, the access timing is reasonably allocated to realize pipeline operation, so there is no need to increase the control time. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of multi-axis current loop parameter reading for traditional FPGA;

[0033] Figure 2 This is a schematic diagram of the FPGA implementation of multi-axis current loop parameter reading in the present invention;

[0034] Figure 3 This is a structural block diagram of a low-resource FPGA multi-axis current loop of the present invention;

[0035] Figure 4 This is a block diagram of the parameter access module in the present invention;

[0036] Figure 5 It is a block diagram of the variable access module in the present invention;

[0037] Figure 6 A schematic diagram of the RAM and double buffer structure in the present invention;

[0038] Figure 7 This is a timing diagram for accessing current loop parameters in the present invention;

[0039] Figure 8 This is a timing diagram for accessing current loop variables in the present invention. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] Please refer to Figure 3 The present invention is a low-resource FPGA multi-axis current loop, which includes: a current loop operation module, a data access scheduling module, a parameter access module and a variable access module.

[0042] In the present invention, both the parameter access module and the variable access module are RAM+double buffer structure, the double buffer structure is a two-level buffer register, the two-level buffer register is divided into a primary buffer register and a secondary buffer register according to the signal flow direction; both the parameter access module and the variable access module use the RAM resources inside the FPGA to store data, and both use the two-level buffer register to access the data cache, and the data access and current loop operation are performed in parallel. The double buffer structure is applied to the read and write process of the RAM, such as Figure 6 , take parameter reading as an example. The RAM partition stores the parameters required for the current loop of each axis. The data access scheduling module selects the output RAM read address according to the current loop reuse order and caches the read data to the first-level buffer register. The data access scheduling module controls the first-level buffer register to output the current cache data to the second-level buffer register before caching the next axis data, avoiding data competition caused by real-time reading, ensuring the correctness of the current loop operation, and ensuring the reliability and real-time performance of multi-axis control. Figure 2 , taking parameter reading as an example.

[0043] Current loop operation module: used for conditioning and transformation of feedback input quantity (current feedback, position feedback), current loop adjustment operation, etc. The calculation result is used to generate the PWM of the current axis and control the motor of the current axis. The current loop operation module is reused. In this embodiment, the current loop operation module adopts time division multiplexing. When the current loop operation start signal of this cycle arrives, the current loop operation of the first axis is performed. When the current loop operation of the current axis is completed, the current loop operation of the next axis is immediately started until all axis operations are completed. In other embodiments, the current loop operation module reuse is not limited to time division multiplexing, and pipeline multiplexing can also be adopted. The current loop operation module is suitable for the pipeline structure. The current loop operation module is divided into several steps. When the current loop operation start signal of this cycle arrives, the first step of the operation of the first axis is performed. When the first step of the operation of the first axis is completed, the second step of the operation of the first axis is immediately started, and the first step of the operation of the second axis is immediately started at the same time, and so on, until all steps of all axes are completed.

[0044] Data access scheduling module: used to select the feedback input of the output current loop operation module and the calculation results of each axis output by the receiving current loop operation module; used to control the access timing and access actions of the parameter access module and the variable access module. Among them, the current loops of multiple axes are controlled by the data access scheduling module to execute sequentially, so the data access scheduling module can select the feedback input of the output current loop operation module and the calculation results of each axis output by the receiving current loop operation module according to the current axis number.

[0045] Parameter access module: used to access the parameters required for the current loop operation of each axis; see Figure 4 ,The parameter access module includes a parameter RAM, a parameter primary buffer register group and a parameter secondary buffer register group;

[0046] The parameter RAM is used to store the parameters required for the current loop operation of all axes (hereinafter referred to as parameters), such as current setting, motor parameters, adjustment parameters, etc. The current loop parameters are provided by the microprocessor, which is the MCU or other chips or devices such as the host computer that provide the current loop parameters. The parameter RAM is a dual-port RAM, one end of which is used for the processor (MCU / ARM / DSP) to write parameters, and the other end is used for the FPGA current loop operation module to read parameters; the parameter first-level buffer register group is used to store the parameters read in real time by the parameter RAM; the parameter second-level buffer register group is used to cache the current axis parameters;

[0047] The reading time of the parameter RAM and the updating time of the parameter primary buffer register group and the parameter secondary buffer register group are controlled by the control signal output by the data access scheduling module to ensure the correctness of the multiplexed current loop operation. Figure 4 "SEL" refers to the select output, that is, the corresponding data is output according to the read address output by the data access scheduling module. Figure 7, the parameter access timing is as follows:

[0048] Parameter writing process: The microprocessor completes the update of each axis parameter before the current loop enable signal arrives in each control cycle, and the parameter RAM partition stores the parameters of each axis;

[0049] Parameter reading process: The data access scheduling module reads the parameters of the next current loop operation axis in advance at the start of the current loop operation of the current axis according to the order of the current loop multiplexing axes, and puts the read data into the parameter first-level buffer register group; when the current axis current loop operation ends (that is, the start time of the next axis current loop operation), the data of the parameter first-level buffer register group is updated to the parameter second-level buffer register group for use by the next axis current loop operation.

[0050] Variable access module: used to access the variables in the current loop operation process of each axis; see Figure 5 , the variable access module includes a variable RAM, a write variable primary buffer register group, a write variable secondary buffer register group, a read variable primary buffer register group and a read variable secondary buffer register group;

[0051] The variable RAM is used to store the intermediate variables (hereinafter referred to as variables) of all axis current loop operation processes. The variable RAM is a dual-port RAM, one end of which is used for the current loop operation module to write variables, and the other end is used for the current loop operation module to read variables;

[0052] The first-level buffer register group of write variables is used to store the real-time variables of the current axis, and the second-level buffer register group of write variables is used to cache the variables of the previous axis;

[0053] The read variable primary buffer register group is used to store the variables read by the variable RAM in real time, and the read variable secondary buffer register group is used to cache the variables of the current axis;

[0054] The access time of the variable RAM and the update time of the buffer are controlled by the control signal output by the data access scheduling module to ensure the correctness of the multiplexed current loop operation. Figure 8 , the variable access timing is as follows:

[0055] Variable writing process: The current loop operation module stores the variables in the primary buffer register group of the write variables in real time during the current loop operation of the current axis; at the end of the current loop operation of the current axis, the data in the primary buffer register group of the write variables is updated to the secondary buffer register group of the write variables, and then the data access scheduling module controls the data in the secondary buffer register group of the write variables to be written into the corresponding axis area of ​​the variable RAM for reading in the next cycle;

[0056] Variable reading process: The data access scheduling module reads the variables of the next current loop operation axis at the start of the current loop operation of the current axis according to the order of the current loop multiplexing axes, and puts the read data into the variable first-level buffer register group; when the current axis current loop operation ends, the data of the variable first-level buffer register group is updated to the variable second-level buffer register group for use by the next axis current loop operation.

[0057] The advantages of the present invention are:

[0058] 1) The microprocessor, current loop operation module, and data access scheduling module in the present invention all operate independently, so the access of parameter RAM and variable RAM will not increase the operation time of the current loop operation module.

[0059] 2) The present invention uses RAM+double buffer structure to access current loop parameters and variables, so the LUT resources consumed by the FPGA will not increase with the increase in the number of control axes. The present invention uses the abundant RAM resources in the FPGA to replace some parameter and variable register resources in the multi-axis current loop, thereby reducing the use of FPGA resources. This replacement process is not just a simple "container" replacement, but also needs to cooperate with the timing control and cache control of reading and writing RAM, so as to reduce FPGA resources without increasing control time. The present invention further reduces FPGA resources on the basis of the existing current loop multiplexing technology (multiplexing is also to reduce resources).

[0060] The parts not involved in the present invention are the same as the prior art or are implemented by using the prior art.

[0061] The above contents are further detailed descriptions of the present invention in combination with specific implementation methods, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A low-resource FPGA multi-axis current loop control system, characterized by: include Current loop operation module: used for conditioning of feedback input quantity and current loop operation; Data access scheduling module: used to select the feedback input quantity of the output current loop operation module and receive the calculation results of each axis output by the current loop operation module; used to control the access timing and access action of the parameter access module and the variable access module; Parameter access module: used to access the parameters required for the current loop calculation of each axis; Variable access module: used to access the variables in the current loop operation process of each axis; Among them, the parameter access module and the variable access module both use the RAM resources inside the FPGA to store data; the parameter access module and the variable access module both use two-level buffer registers to access the data, and the data access and current loop operation are performed in parallel; The parameter access module includes a parameter RAM, a parameter primary buffer register group and a parameter secondary buffer register group; The parameter RAM is used to store the parameters required for the current loop operation of all axes. The parameter RAM is a dual-port RAM, one end of which is used for the processor to write parameters, and the other end is used for the FPGA current loop operation module to read parameters; The parameter level 1 buffer register group is used to store the parameters read by the parameter RAM in real time; The parameter secondary buffer register group is used to cache the current axis parameters; The reading time of the parameter RAM and the updating time of the parameter primary buffer register group and the parameter secondary buffer register group are controlled by the control signal output by the data access scheduling module, specifically: Parameter writing process: The microprocessor completes the update of each axis parameter before the current loop enable signal arrives in each control cycle, and the parameter RAM partition stores the parameters of each axis; Parameter reading process: The data access scheduling module reads the parameters of the next current loop operation axis in advance at the start time of the current loop operation of the current axis according to the order of the current loop multiplexing axis, and puts the read data into the parameter first-level buffer register group; when the current loop operation of the current axis ends, that is, when the current loop operation of the next axis starts, the data of the parameter first-level buffer register group is updated to the parameter second-level buffer register group for use in the current loop operation of the next axis; The variable access module includes a variable RAM, a write variable primary buffer register group, a write variable secondary buffer register group, a read variable primary buffer register group and a read variable secondary buffer register group; The variable RAM is used to store the variables of all axis current loop operation processes. The variable RAM is a dual-port RAM, one end of which is used for the current loop operation module to write variables, and the other end is used for the current loop operation module to read variables; The first-level buffer register group of write variables is used to store the real-time variables of the current axis, and the second-level buffer register group of write variables is used to cache the variables of the previous axis; The read variable primary buffer register group is used to store the variables read by the variable RAM in real time, and the read variable secondary buffer register group is used to cache the variables of the current axis; The access time of the variable RAM and the update time of the buffer are controlled by the control signal output by the data access scheduling module, specifically: Variable writing process: The current loop operation module stores the variables in the primary buffer register group of the write variables in real time during the current loop operation of the current axis; at the end of the current loop operation of the current axis, the data in the primary buffer register group of the write variables is updated to the secondary buffer register group of the write variables, and then the data access scheduling module controls the data in the secondary buffer register group of the write variables to be written into the corresponding axis area of ​​the variable RAM for reading in the next cycle; Variable reading process: The data access scheduling module reads the variables of the next current loop operation axis at the start of the current loop operation of the current axis according to the order of the current loop multiplexing axes, and puts the read data into the variable first-level buffer register group; when the current loop operation of the current axis ends, the data of the variable first-level buffer register group is updated to the variable second-level buffer register group for use by the next axis current loop operation.

2. The low-resource FPGA multi-axis current loop control system according to claim 1, characterized in that: The current loop operation module is time-division multiplexed. When the current loop operation start signal of this cycle arrives, the current loop operation of the first axis is performed. When the current loop operation of the current axis is completed, the current loop operation of the next axis is started immediately until all axis operations are completed.

3. The low-resource FPGA multi-axis current loop control system according to claim 1, characterized in that: The current loop operation module is suitable for the pipeline structure. The current loop operation module is divided into several steps. When the current loop operation start signal of this cycle arrives, the first step of the operation of the first axis is performed. When the first step of the operation of the first axis is completed, the second step of the operation of the first axis is started immediately, and the first step of the operation of the second axis is started immediately, and so on, until all steps of all axes are completed.

4. The low-resource FPGA multi-axis current loop control system according to claim 1, characterized in that: The two-level buffer register is divided into a primary buffer register and a secondary buffer register according to the signal flow direction; The data access scheduling module selects the output RAM read address according to the current loop multiplexing order and caches the read data to the first-level buffer register; the data access scheduling module controls the first-level buffer register to output the current cached data to the second-level buffer register before caching the next axis data.

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