A programmable decimation filter circuit

Abstract

The present invention discloses a programmable decimation filter circuit, which belongs to the field of large-scale digital integrated circuit design, and includes a coefficient remapping module, a data remapping module, a gated clock module and a convolution module; the convolution module includes a delay module, an addition module, a multiplication module, a summation module and an overflow protection module connected in sequence; the input ports of the programmable decimation filter circuit are filter coefficients, filter length, decimation multiples, input data, clock 1 and clock 2, respectively, and the output port is output data; the filter coefficient is input to the coefficient remapping module, the filter length is input to the addition module and the summation module, the decimation multiple is input to the data remapping module and the delay module, the input data is input to the data remapping module, the clock 1 is input to the data remapping module, and the clock 2 is input to the data remapping module and the gated clock. The present invention provides a flexible and configurable digital filtering solution for a high-speed transceiver receiving link.

Description

Technical Field

[0001] The invention relates to the technical field of large-scale digital integrated circuit design, and in particular to a programmable decimation filter circuit. Background Art

[0002] The large-scale commercial application of 5G has brought about a huge demand for data processing. Under the demand for high speed, high integration, and ultra-wideband, high-performance transceivers have emerged. High-performance transceivers integrate digital signal processing functions in the receiving link. As the main signal processing unit, the performance, area, and power consumption of the digital filter determine the overall performance of the entire digital circuit. How to minimize the area and power consumption of the digital filter while meeting different application scenarios has become a key design difficulty. Summary of the invention

[0003] The object of the present invention is to provide a programmable decimation filter circuit to solve the problem that the area and power consumption of a traditional digital filter are difficult to meet high performance requirements.

[0004] To solve the above technical problems, the present invention provides a programmable decimation filter circuit, a coefficient remapping module, a data remapping module, a gated clock module and a convolution module;

[0005] The convolution module includes a delay module, an addition module, a multiplication module, a summation module and an overflow protection module which are connected in sequence; the delay module delays the input data, the addition module performs addition operation on the delayed input data, the multiplication module realizes the multiplication function of the filter coefficient and the addition output, the summation module realizes the summation of the multiplication module output, and the overflow protection module performs overflow protection on the convolution result of the summation output;

[0006] The input ports of the programmable decimation filter circuit are filter coefficient, filter length, decimation multiple, input data, clock 1 and clock 2, respectively, and the output port is output data; the filter coefficient is input to the coefficient remapping module, the filter length is input to the coefficient remapping module, the gated clock module, the addition module and the summation module, the decimation multiple is input to the data remapping module and the delay module, the input data is input to the data remapping module, the clock 1 is input to the data remapping module, and the clock 2 is input to the data remapping module and the gated clock gating;

[0007] The coefficient remapping module is connected to the multiplication module,

[0008] The data remapping module is connected to the delay module,

[0009] The gated clock module is simultaneously connected to the delay module, the addition module, the multiplication module, and the summation module.

[0010] In one implementation, the decimation multiple can be configured as 1, 2, 4, corresponding to 1, 2, 4 times decimation; clock 1 and input data have the same frequency, clock 2 and output data have the same frequency; the filter length can be configured as 24, 48, 72, corresponding to 12, 24, 36 filter coefficients; the filter coefficients are coeff_in_01, coeff_in_02, ..., coeff_in_35, coeff_in_36; the filter coefficients have three configurations, namely:

[0011] Configuration A1: When the filter length is configured to 24, only coeff_in_01, coeff_in_02, …, coeff_in_11, coeff_in_12 need to be configured;

[0012] Configuration A2: When the filter length is configured to 48, only coeff_in_01, coeff_in_02, …, coeff_in_23, coeff_in_24 need to be configured;

[0013] Configuration A3: When the filter length is configured to 72, all coefficients coeff_in_01, coeff_in_02, …, coeff_in_35, coeff_in_36 need to be configured.

[0014] In one implementation, the coefficient remapping module remaps the filter coefficients according to the filter length, and its input signal is the filter length and the filter coefficients coeff_in_01, coeff_in_02, ..., coeff_in_35, coeff_in_36, and the output signal is coeff01, coeff02, ..., coeff35, coeff36. The coefficient remapping module has three working modes, namely:

[0015] Mode B1: When the filter length is configured as 24, coeff_in_01, coeff_in_02, ..., coeff_in_11, coeff_in_12 are placed in coeff25, coeff26, ..., coeff35, coeff36 in sequence, and coeff01, coeff02, ..., coeff22, coeff23 all output 0;

[0016] Mode B2: When the filter length is configured to 48, coeff_in_01, coeff_in_02, ..., coeff_in_23, coeff_in_24 are sequentially placed in coeff13, coeff14, ..., coeff35, coeff36, and coeff01, coeff02, ..., coeff11, coeff12 are all 0;

[0017] Mode B3: When the filter length is configured to 72, coeff_in_01, coeff_in_02, …, coeff_in_35, coeff_in_36 are sequentially placed into coeff01, coeff02, …, coeff35, coeff36.

[0018] In one implementation, the input signals of the gated clock module are filter length and clock 2, and the output signals are clk_72, clk_48_72, and clk_24_48_72; the gated clock module includes a decision maker 1, a decision maker 2, and a decision maker 3; each decision maker is connected to the filter length and clock 2, the decision maker 1 outputs clk_24_48_72, the decision maker 2 outputs clk_48_72, and the decision maker 3 outputs clk_72;

[0019] The function of the decision 1 is that when the filter length is configured to be 24, 48 or 72, the output signal clk_24_48_72 = clock 2, otherwise it is 0;

[0020] The function of decision 2 is that when the filter length is configured to be 48 or 72, the output signal clk_48_72 = clock 2, and 0 in other cases;

[0021] The function of the decision device 3 is to output the signal clk_72 = clock 2 when the filter length is configured as 72, and to output the signal clk_72 = clock 2 in other cases.

[0022] In one embodiment, the data remapping module includes a counter, a data distributor and a data remapping delay unit; the input signals of the data remapping module are clock 1, input data, extraction multiple and clock 2, and the output signals are data d_1, data d_2, data d_3, and data d_4; wherein clock 1 is input into the counter, input data is input into the data distributor, extraction multiple is input into the data distributor, and clock 2 is input into the data remapping delay unit; the counter is connected to the data distributor, and the data distributor outputs signals d_1_tmp, d_2_tmp, d_3_tmp, and d_4_tmp to the data remapping delay unit; the data remapping module has three modes, namely:

[0023] Mode C1: The decimation multiple is 1, clock 1 and clock 2 have the same frequency and phase, the output data has the same frequency as the input data, the output data d_1 is obtained by delaying the input data, the output data d_2 is obtained by delaying the output data d_1, the output data d_3 is obtained by delaying the output data d_2, and the output data d_4 is obtained by delaying the output data d_3;

[0024] Mode C2: The decimation factor is 2, clock 2 is the frequency divided by two of clock 1, the output data d_1 and d_2 are half of the input data respectively, the output data d_3 is the delay of the output data d_1, and the output data d_4 is the delay of the output data d_2;

[0025] Mode C3: The decimation factor is 4, clock 2 is divided by four of clock 1, and the output data d_1, d_2, d_3, and d_4 are all one quarter of the input data.

[0026] In one embodiment, the delay module includes three delay units: delay unit 1, delay unit 2 and delay unit 3; the working clock of delay unit 1 is clk_24_48_72, the input is d_1~d_4, d01~d19, and the corresponding output is d01~d23; the working clock of delay unit 2 is clk_48_72, the input is d20~d43, and the corresponding output is d24~d47; the working clock of delay unit 3 is clk_72, the input is d44~d67, and the corresponding output is d48~d71.

[0027] In one embodiment, the addition module includes three addition units: addition unit 1, addition unit 2 and addition unit 3;

[0028] The working clock of the adding unit 1 is clk_24_48_72, and the output data is add_25_47, add_26_46, ..., add_35_37, add_36_36; when the filter length is configured to 24, the corresponding input data is d01+d23, d02+d22, ..., d11+d13, d12 in sequence; when the filter length is configured to 48, the corresponding input data is d13+d35, d14+d34, ..., d22+d25, d24 in sequence; when the filter length is configured to 72, the corresponding input data is d25+d47, d26+d46, ..., d35+d37, d36 in sequence;

[0029] The working clock of adder 2 is clk_48_72, and the output data is add_13_59, add_14_58, ..., add_23_49, add_24_48; when the filter length is configured to 24, there is no clock input, and the adder 2 does not work; when the filter length is configured to 48, the corresponding inputs are d01+d47, d02+d46, ..., d11+d17, d12+d36 in sequence; when the filter length is configured to 72, the corresponding inputs are d13+d59, d14+d58, ..., d23+d49, d24+d48 in sequence;

[0030] The working clock of the adding unit 3 is clk_72, and the output data is add_01_71, add_02_70, …, add_11_61, add_12_60; when the filter length is configured to 24 or 48, there is no clock input, and the adding unit 3 does not work; when the filter length is configured to 72, the corresponding inputs are d01+d71, d02+d70, …, d11+d61, d12+d60 in sequence.

[0031] In one embodiment, the multiplication module includes three multiplication units: multiplication unit 1, multiplication unit 2 and multiplication unit 3;

[0032] The working clock of multiplication unit 1 is clk_24_48_72, and the input coefficients coeff25, coeff26, ..., coeff35, coeff36 are multiplied by the outputs add_25_47, add_26_46, ..., add_35_37, add_36_36 of the addition module respectively to obtain the output data mult_25_47, mult_26_46, ..., mult_35_37, mult_36_36;

[0033] The working clock of multiplication unit 2 is clk_48_72, and the input coefficients coeff13, coeff14, ..., coeff23, coeff24 are multiplied by the output results add_13_59, add_14_58, ..., add_23_49, add_24_48 of the addition module respectively to obtain the output data mult_13_59, mult_14_58, ..., mult_23_49, mult_24_48;

[0034] The working clock of the multiplication unit 3 is clk_72, and the input coefficients coeff01, coeff02, ..., coeff11, coeff12 are multiplied by the output results add_01_71, add_02_70, ..., add_11_61, add_12_60 of the addition module respectively to obtain the output data mult_01_71, mult_02_70, ..., mult_11_61, mult_12_60.

[0035] In one embodiment, the summing module includes four summing units: summing unit 1, summing unit 2, summing unit 3 and summing unit 4;

[0036] The working clock of summing unit 1 is clk_24_48_72, which is used to sum mult_25_47, mult_26_46, ..., mult_35_37, mult_36_36;

[0037] The working clock of summing unit 2 is clk_48_72, which is used to sum mult_13_59, mult_14_58, ..., mult_23_49, mult_24_48;

[0038] The working clock of summing unit 3 is clk_72, which is used to sum mult_01_71, mult_02_70, ..., mult_11_61, mult_12_60;

[0039] The function of summing unit 4 is to sum the results of summing unit 1, summing unit 2, and summing unit 3 again according to the configuration of the filter length and output them through the data selector mux:

[0040] When the filter length is configured to 24, summation unit 4 directly outputs the output of summation unit 1; when the filter length is configured to 48, the output result of summation unit 4 is the sum of the output of summation unit 1 and the output of summation unit 2; when the filter length is configured to 72, the output result of summation unit 4 is the sum of the output of summation unit 1, the output of summation unit 2 and the output of summation unit 3.

[0041] In the programmable decimation filter circuit provided by the present invention, accurate control of the circuit module can be achieved for different decimation ratios and filter coefficient lengths, low power consumption can be achieved through clock gating, and a large number of module multiplexing can reduce hardware overhead while ensuring high-speed operation of the circuit, thereby providing a flexible and configurable digital filtering solution for the high-speed transceiver receiving link. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of the overall structure of a programmable decimation filter circuit provided by the present invention;

[0043] Figure 2 This is a schematic diagram of the coefficient remapping module structure;

[0044] Figure 3 This is a schematic diagram of the gated clock module structure;

[0045] Figure 4 This is a schematic diagram of the data remapping module structure;

[0046] Figure 5 This is a schematic diagram of the timing relationship between clock 1, input data, decimation multiple, and clock 2 when the decimation multiple is 1;

[0047] Figure 6 This is a schematic diagram of the timing relationship between clock 1, input data, decimation multiple, and clock 2 when the decimation multiple is 2;

[0048] Figure 7 This is a schematic diagram of the timing relationship between clock 1, input data, decimation multiple, and clock 2 when the decimation multiple is 4;

[0049] Figure 8 It is a schematic diagram of the delay module structure;

[0050] Fig. 9 It is a schematic diagram of the structure of the addition module;

[0051] Fig.10 It is a schematic diagram of the structure of the multiplication module;

[0052] Fig.11 This is a schematic diagram of the summation module structure. DETAILED DESCRIPTION

[0053] The following is a further detailed description of a programmable decimation filter circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the accompanying drawings are in a very simplified form and are not in exact proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0054] The present invention provides a programmable decimation filter circuit, the overall structure of which is as follows: Figure 1As shown, it includes a coefficient remapping module, a data remapping module, a gated clock module and a convolution module; wherein the convolution module includes a delay module, an addition module, a multiplication module, a summation module and an overflow protection module. The input ports of the programmable decimation filter circuit are filter coefficient, filter length, decimation multiple, input data, clock 1, and clock 2, respectively, and the output port is output data; the filter coefficient is input to the coefficient remapping module, the filter length is input to the coefficient remapping module, the gated clock module, the addition module inside the convolution module, and the summation module inside the convolution module, the decimation multiple is input to the data remapping module and the delay module, the input data is input to the data remapping module, clock 1 is input to the data remapping module, and clock 2 is input to the data remapping module and the gated clock gating.

[0055] The decimation multiple can be configured as 1, 2, 4, corresponding to 1, 2, 4 times decimation. Clock 1 has the same frequency as the input data. Clock 2 has the same frequency as the output data. The filter length can be configured as 24, 48, 72, corresponding to 12, 24, 36 filter coefficients. The filter coefficients are coeff_in_01, coeff_in_02, ..., coeff_in_35, coeff_in_36; there are three configurations for the filter coefficients, namely:

[0056] Configuration A1: When the filter length is configured to 24, only coeff_in_01, coeff_in_02, ..., coeff_in_11, coeff_in_12 need to be configured, and other coefficients (coeff_in_13, coeff_in_14, ..., coeff_in_35, coeff_in_36) are not configured;

[0057] Configuration A2: When the filter length is configured to 48, only coeff_in_01, coeff_in_02, ..., coeff_in_23, coeff_in_24 need to be configured, and other coefficients (coeff_in_25, coeff_in_26, ..., coeff_in_35, coeff_in_36) are not configured;

[0058] Configuration A3: When the filter length is configured to 72, all coefficients coeff_in_01, coeff_in_02, …, coeff_in_35, coeff_in_36 need to be configured.

[0059] The structure of the coefficient remapping module is as follows Figure 2As shown, the input signal of the module is the filter length and the filter coefficients coeff_in_01, coeff_in_02, ..., coeff_in_35, coeff_in_36, and the output signal is coeff01, coeff02, ..., coeff35, coeff36. The function of the coefficient remapping module is to remap the filter coefficients according to the filter length. The coefficient remapping module has three working modes, namely:

[0060] Mode B1: When the filter length is configured to 24, coeff_in_01, coeff_in_02, ..., coeff_in_11, coeff_in_12 are placed in coeff25, coeff26, ..., coeff35, coeff36 in sequence, and coeff01, coeff02, ..., coeff22, coeff23 all output 0;

[0061] Mode B2: When the filter length is configured to 48, coeff_in_01, coeff_in_02, ..., coeff_in_23, coeff_in_24 are sequentially placed in coeff13, coeff14, ..., coeff35, coeff36, and coeff01, coeff02, ..., coeff11, coeff12 are all 0;

[0062] Mode B3: When the filter length is configured to 72, coeff_in_01, coeff_in_02, …, coeff_in_35, coeff_in_36 are sequentially placed into coeff01, coeff02, …, coeff35, coeff36.

[0063] The structure of the gated clock module is as follows Figure 3 As shown, the input signals of the module are filter length and clock 2, and the output signals are clk_72, clk_48_72, and clk_24_48_72. The gated clock module includes three decision devices: decision device 1, decision device 2, and decision device 3. Each decision device is connected to the filter length and clock 2, decision device 1 outputs clk_24_48_72, decision device 2 outputs clk_48_72, and decision device 3 outputs clk_72. The function of decision device 1 is that when the filter length is configured to 24, 48, or 72, the output signal clk_24_48_72 = clock 2, and the other cases are 0; the function of decision device 2 is that when the filter length is configured to 48 or 72, the output signal clk_48_72 = clock 2, and the other cases are 0; the function of decision device 3 is that when the filter length is configured to 72, the output signal clk_72 = clock 2, and the other cases are 0.

[0064] The data remapping module structure is as follows Figure 4 As shown, it includes a counter, a data distributor and a data remapping delay unit. The input signals of the data remapping module are clock 1, input data, extraction multiple and clock 2, and the output signals are data d_1, data d_2, data d_3, and data d_4. Clock 1 is input into the counter, input data is input into the data distributor, extraction multiple is input into the data distributor, and clock 2 is input into the data remapping delay unit; the counter is connected to the data distributor, and the data distributor outputs signals d_1_tmp, d_2_tmp, d_3_tmp, and d_4_tmp to the data remapping delay unit. The data remapping module has three modes, namely:

[0065] Mode C1, its timing relationship is as follows Figure 5 In this mode, the decimation multiple is 1, clock 1 and clock 2 have the same frequency and phase, the output data has the same frequency as the input data, the output data d_1 is obtained by delaying the input data, the output data d_2 is obtained by delaying the output data d_1, the output data d_3 is obtained by delaying the output data d_2, and the output data d_4 is obtained by delaying the output data d_3;

[0066] Mode C2, its timing relationship is as follows Figure 6 As shown. In this mode, the extraction multiple is 2, clock 2 is the frequency divided by two of clock 1, and the output data d_1 and d_2 are half of the input data respectively. Output data d_3 is the delay of output data d_1, and output data d_4 is the delay of output data d_2;

[0067] Mode C3, its timing relationship is as follows Figure 7 In this mode, the decimation multiple is 4, clock 2 is four times the frequency of clock 1, and the output data d_1, d_2, d_3, and d_4 are all one quarter of the input data.

[0068] The convolution module includes five submodules, namely a delay module, an addition module, a multiplication module, a summation module and an overflow protection module; the delay module is used to delay the input data, the addition module is used to perform addition operations on the delayed input data, the multiplication module is used to realize the multiplication function of the filter coefficient and the addition output, the summation module is used to realize the summation of the multiplication module output, and the overflow protection module is used to perform overflow protection on the convolution result of the summation output.

[0069] The structure of the delay module is as follows Figure 8As shown, it includes three delay units (i.e., delay unit 1, delay unit 2 and delay unit 3). The working clock of delay unit 1 is clk_24_48_72, the input is d_1~d_4, d01~d19, and the corresponding output is d01~d23; the working clock of delay unit 2 is clk_48_72, the input is d20~d43, and the corresponding output is d24~d47; the working clock of delay unit 3 is clk_72, the input is d44~d67, and the corresponding output is d48~d71.

[0070] The structure of the addition module is as follows Fig. 9 As shown, it includes three adding units (i.e., adding unit 1, adding unit 2, and adding unit 3). The working clock of adding unit 1 is clk_24_48_72, and the output data is add_25_47, add_26_46, ..., add_35_37, add_36_36; when the filter length is configured to 24, the corresponding input data is d01+d23, d02+d22, ..., d11+d13, d12 in sequence; when the filter length is configured to 48, the corresponding input data is d13+d35, d14+d34, ..., d22+d25, d24 in sequence; when the filter length is configured to 72, the corresponding input data is d25+d47, d26+d46, ..., d35+d37, d36; the working clock of the adding unit 2 is clk_48_72, and the output data is add_13_59, add_14_58, …, add_23_49, add_24_48; when the filter length is configured to 24, there is no clock input, and the adding unit 2 does not work; when the filter length is configured to 48, the corresponding inputs are d01+d47, d02+d46, …, d11+d17, d12+d36 in sequence; when the filter length is configured to 72, the corresponding inputs are d13+d59, d14+d58, …, d23+d49, d24+d48 in sequence. The working clock of the adding unit 3 is clk_72, and the output data is add_01_71, add_02_70, …, add_11_61, add_12_60; when the filter length is configured to 24 or 48, there is no clock input, and the adding unit 3 does not work; when the filter length is configured to 72, the corresponding inputs are d01+d71, d02+d70, …, d11+d61, d12+d60 in sequence.

[0071] The structure of the multiplication module is as follows: Fig.10As shown, it includes three multiplication units (i.e., multiplication unit 1, multiplication unit 2, and multiplication unit 3). The working clock of multiplication unit 1 is clk_24_48_72, and the input coefficients coeff25, coeff26, ..., coeff35, coeff36 are multiplied by the outputs add_25_47, add_26_46, ..., add_35_37, add_36_36 of the addition module respectively to obtain the output data mult_25_47, mult_26_46, ..., mult_35_37, mult_36_36. The working clock of multiplication unit 2 is clk_48_72, and the input coefficients coeff13, coeff14, ..., coeff23, coeff24 are multiplied with the output results of the addition module add_13_59, add_14_58, ..., add_23_49, add_24_48 respectively to obtain the output data mult_13_59, mult_14_58, ..., mult_23_49, mult_24_48. The working clock of multiplication unit 3 is clk_72, and the input coefficients coeff01, coeff02, ..., coeff11, coeff12 are multiplied with the output results of the addition module add_01_71, add_02_70, ..., add_11_61, add_12_60 respectively to obtain the output data mult_01_71, mult_02_70, ..., mult_11_61, mult_12_60.

[0072] The structure of the summation module is as follows Fig.11As shown, it includes four summing units (i.e., summing unit 1, summing unit 2, summing unit 3, and summing unit 4) and combinational logic. The working clock of summing unit 1 is clk_24_48_72, which is used to sum mult_25_47, mult_26_46, ..., mult_35_37, mult_36_36. The working clock of summing unit 2 is clk_48_72, which is used to sum mult_13_59, mult_14_58, ..., mult_23_49, mult_24_48. The working clock of summing unit 3 is clk_72, which is used to sum mult_01_71, mult_02_70, ..., mult_11_61, mult_12_60. The function of summing unit 4 is to sum the results of summing unit 1, summing unit 2, and summing unit 3 again according to the configuration of the filter length and output them through the data selector mux. When the filter length is configured to 24, summing unit 4 directly outputs the output of summing unit 1; when the filter length is configured to 48, the output result of summing unit 4 is the output of summing unit 1 + the output of summing unit 2 (that is, the sum of the output of summing unit 1 and the output of summing unit 2); when the filter length is configured to 72, the output result of summing unit 4 is the output of summing unit 1 + the output of summing unit 2 + the output of summing unit 3 (that is, the sum of the output of summing unit 1, the output of summing unit 2, and the output of summing unit 3).

[0073] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A programmable decimation filter circuit, characterized in that: It includes coefficient remapping module, data remapping module, gated clock module and convolution module; The convolution module includes a delay module, an addition module, a multiplication module, a summation module and an overflow protection module which are connected in sequence; the delay module delays the input data, the addition module performs addition operation on the delayed input data, the multiplication module realizes the multiplication function of the filter coefficient and the addition output, the summation module realizes the summation of the multiplication module output, and the overflow protection module performs overflow protection on the convolution result of the summation output; The input ports of the programmable decimation filter circuit are filter coefficient, filter length, decimation multiple, input data, clock 1 and clock 2, respectively, and the output port is output data; the filter coefficient is input to the coefficient remapping module, the filter length is input to the coefficient remapping module, the gated clock module, the addition module and the summation module, the decimation multiple is input to the data remapping module and the delay module, the input data is input to the data remapping module, the clock 1 is input to the data remapping module, and the clock 2 is input to the data remapping module and the gated clock gating; The coefficient remapping module is connected to the multiplication module, The data remapping module is connected to the delay module, The gated clock module is simultaneously connected to the delay module, the addition module, the multiplication module, and the summation module; The decimation multiple can be configured as 1, 2, 4, corresponding to 1, 2, 4 times decimation; clock 1 and input data have the same frequency, clock 2 and output data have the same frequency; the filter length can be configured as 24, 48, 72, corresponding to 12, 24, 36 filter coefficients; the filter coefficients are coeff_in_01, coeff_in_02, ..., coeff_in_35, coeff_in_36; the filter coefficients have three configurations, namely: Configuration A1: When the filter length is configured to 24, only coeff_in_01, coeff_in_02, ..., coeff_in_11, coeff_in_12 need to be configured; Configuration A2: When the filter length is configured to 48, only coeff_in_01, coeff_in_02, …, coeff_in_23, coeff_in_24 need to be configured; Configuration A3: When the filter length is configured to 72, all coefficients coeff_in_01, coeff_in_02, …, coeff_in_35, coeff_in_36 need to be configured; The coefficient remapping module remaps the filter coefficients according to the filter length. Its input signal is the filter length and the filter coefficients coeff_in_01, coeff_in_02, ..., coeff_in_35, coeff_in_36, and its output signal is coeff01, coeff02, ..., coeff35, coeff36. The coefficient remapping module has three working modes, namely: Mode B1: When the filter length is configured as 24, coeff_in_01, coeff_in_02, ..., coeff_in_11, coeff_in_12 are placed in coeff25, coeff26, ..., coeff35, coeff36 in sequence, and coeff01, coeff02, ..., coeff22, coeff23 all output 0; Mode B2: When the filter length is configured to 48, coeff_in_01, coeff_in_02, ..., coeff_in_23, coeff_in_24 are sequentially placed in coeff13, coeff14, ..., coeff35, coeff36, and coeff01, coeff02, ..., coeff11, coeff12 are all 0; Mode B3: When the filter length is configured as 72, coeff_in_01, coeff_in_02, ..., coeff_in_35, coeff_in_36 are sequentially placed into coeff01, coeff02, ..., coeff35, coeff36; The input signals of the gated clock module are filter length and clock 2, and the output signals are clk_72, clk_48_72, and clk_24_48_72; the gated clock module includes decision 1, decision 2, and decision 3; each decision maker is connected to the filter length and clock 2, decision maker 1 outputs clk_24_48_72, decision maker 2 outputs clk_48_72, and decision maker 3 outputs clk_72; The function of the decision 1 is that when the filter length is configured to be 24, 48 or 72, the output signal clk_24_48_72 = clock 2, otherwise it is 0; The function of decision 2 is that when the filter length is configured to be 48 or 72, the output signal clk_48_72 = clock 2, and 0 in other cases; The function of the decision device 3 is that when the filter length is configured as 72, the output signal clk_72 = clock 2, and 0 in other cases; The data remapping module includes a counter, a data distributor and a data remapping delay unit; the input signals of the data remapping module are clock 1, input data, extraction multiple and clock 2, and the output signals are data d_1, data d_2, data d_3 and data d_4; wherein clock 1 is input into the counter, input data is input into the data distributor, extraction multiple is input into the data distributor, and clock 2 is input into the data remapping delay unit; the counter is connected to the data distributor, and the data distributor outputs signals d_1_tmp, d_2_tmp, d_3_tmp and d_4_tmp to the data remapping delay unit; the data remapping module has three modes, namely: Mode C1: The decimation multiple is 1, clock 1 and clock 2 have the same frequency and phase, the output data has the same frequency as the input data, the output data d_1 is obtained by delaying the input data, the output data d_2 is obtained by delaying the output data d_1, the output data d_3 is obtained by delaying the output data d_2, and the output data d_4 is obtained by delaying the output data d_3; Mode C2: The decimation factor is 2, clock 2 is the frequency divided by two of clock 1, the output data d_1 and d_2 are half of the input data respectively, the output data d_3 is the delay of the output data d_1, and the output data d_4 is the delay of the output data d_2; Mode C3: The decimation factor is 4, clock 2 is divided by four of clock 1, and the output data d_1, d_2, d_3, and d_4 are all one-fourth of the input data.

2. The programmable decimation filter circuit according to claim 1, wherein: The delay module includes three delay units: delay unit 1, delay unit 2 and delay unit 3; the working clock of delay unit 1 is clk_24_48_72, the input is d_1~d_4, d01~d19, and the corresponding output is d01~d23; the working clock of delay unit 2 is clk_48_72, the input is d20~d43, and the corresponding output is d24~d47; the working clock of delay unit 3 is clk_72, the input is d44~d67, and the corresponding output is d48~d71.

3. The programmable decimation filter circuit according to claim 2, wherein: The addition module includes three addition units: addition unit 1, addition unit 2 and addition unit 3; The working clock of the adding unit 1 is clk_24_48_72, and the output data is add_25_47, add_26_46, ..., add_35_37, add_36_36; when the filter length is configured to 24, the corresponding input data is d01+d23, d02+d22, ..., d11+d13, d12 in sequence; when the filter length is configured to 48, the corresponding input data is d13+d35, d14+d34, ..., d22+d25, d24 in sequence; when the filter length is configured to 72, the corresponding input data is d25+d47, d26+d46, ..., d35+d37, d36 in sequence; The working clock of adder 2 is clk_48_72, and the output data is add_13_59, add_14_58, ..., add_23_49, add_24_48; when the filter length is configured to 24, there is no clock input, and the adder 2 does not work; when the filter length is configured to 48, the corresponding inputs are d01+d47, d02+d46, ..., d11+d17, d12+d36 in sequence; when the filter length is configured to 72, the corresponding inputs are d13+d59, d14+d58, ..., d23+d49, d24+d48 in sequence; The working clock of the adding unit 3 is clk_72, and the output data is add_01_71, add_02_70, …, add_11_61, add_12_60; when the filter length is configured to 24 or 48, there is no clock input, and the adding unit 3 does not work; when the filter length is configured to 72, the corresponding inputs are d01+d71, d02+d70, …, d11+d61, d12+d60 in sequence.

4. The programmable decimation filter circuit according to claim 3, wherein: The multiplication module includes three multiplication units: multiplication unit 1, multiplication unit 2 and multiplication unit 3; The working clock of multiplication unit 1 is clk_24_48_72, and the input coefficients coeff25, coeff26, ..., coeff35, coeff36 are multiplied by the outputs add_25_47, add_26_46, ..., add_35_37, add_36_36 of the addition module respectively to obtain the output data mult_25_47, mult_26_46, ..., mult_35_37, mult_36_36; The working clock of multiplication unit 2 is clk_48_72, and the input coefficients coeff13, coeff14, ..., coeff23, coeff24 are multiplied by the output results add_13_59, add_14_58, ..., add_23_49, add_24_48 of the addition module respectively to obtain the output data mult_13_59, mult_14_58, ..., mult_23_49, mult_24_48; The working clock of the multiplication unit 3 is clk_72, and the input coefficients coeff01, coeff02, ..., coeff11, coeff12 are multiplied by the output results add_01_71, add_02_70, ..., add_11_61, add_12_60 of the addition module respectively to obtain the output data mult_01_71, mult_02_70, ..., mult_11_61, mult_12_60.

5. The programmable decimation filter circuit according to claim 4, wherein: The summing module includes four summing units: summing unit 1, summing unit 2, summing unit 3 and summing unit 4; The working clock of summing unit 1 is clk_24_48_72, which is used to sum mult_25_47, mult_26_46, ..., mult_35_37, mult_36_36; The working clock of summing unit 2 is clk_48_72, which is used to sum mult_13_59, mult_14_58, ..., mult_23_49, mult_24_48; The working clock of summing unit 3 is clk_72, which is used to sum mult_01_71, mult_02_70, ..., mult_11_61, mult_12_60; The function of summing unit 4 is to sum the results of summing unit 1, summing unit 2, and summing unit 3 again according to the configuration of the filter length and output them through the data selector mux: When the filter length is configured as 24, summing unit 4 directly outputs the output of summing unit 1; when the filter length is configured as 48, the output result of summing unit 4 is the sum of the output of summing unit 1 and the output of summing unit 2; When the filter length is configured as 72, the output result of summing unit 4 is the sum of the output of summing unit 1, the output of summing unit 2 and the output of summing unit 3.

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