Misregulated voltage cancellation circuit, method, sense circuit, device and apparatus

Abstract

The application relates to a mismatch voltage elimination circuit, method, readout circuit, device and equipment. A preliminary correction is performed on a mismatch voltage in a reference voltage of a target quantizer by a correction circuit, so that the corrected mismatch voltage is stabilized in a preset mismatch magnitude, and then a fine adjustment calibration is performed on the corrected mismatch voltage by a calibration circuit, so that the mismatch voltage is eliminated, and an accurate reference voltage of the target quantizer is obtained. In this way, through the mismatch calibration of the two processes, on the one hand, the condition of a larger mismatch amplitude is quickly corrected to a smaller mismatch magnitude, and on the other hand, the remaining mismatch is fine adjusted and calibrated, so that the reference voltage of the quantizer can be subjected to the mismatch voltage elimination, and the reference voltage source of the quantizer is more accurate.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to an offset voltage elimination circuit, method, readout circuit, apparatus, and device. Background Technology

[0002] The readout circuit can preprocess and convert the analog signals acquired by the signal acquisition device to generate current signals.

[0003] The device that performs signal conversion in the readout circuit is the quantizer, and the noise level of the quantizer is crucial, as it determines the overall noise level of the readout circuit system. For example, the offset voltage of the quantizer can make the reference voltage of the quantizer inaccurate. Therefore, in order to achieve the low noise requirements of the readout circuit system, offset voltage elimination is needed for the reference voltage of the quantizer.

[0004] Therefore, how to eliminate the offset voltage of the quantizer's reference voltage has become an urgent technical problem to be solved. Summary of the Invention

[0005] This application provides an offset voltage elimination circuit, method, readout circuit, apparatus, and device that can eliminate offset voltage of the reference voltage of a quantizer.

[0006] In a first aspect, embodiments of this application provide an offset voltage elimination circuit, which includes: a correction circuit and a calibration circuit;

[0007] The correction circuit is used to initially correct the offset voltage in the reference voltage of the target quantizer so that the corrected offset voltage is stabilized within a preset offset range.

[0008] The calibration circuit is used to fine-tune the corrected offset voltage to eliminate the offset voltage and obtain the accurate reference voltage of the target quantizer.

[0009] In one embodiment, the correction circuit includes: a comparator, an analog-to-digital converter, and a current compensator;

[0010] A comparator is used to obtain a potential signal from a voltage signal converted from an offset voltage.

[0011] An analog-to-digital converter is used to generate a control signal based on a potential signal. The control signal is used to control a current compensator to provide compensation current. The compensation current is used to stabilize the offset voltage within the offset range.

[0012] In one embodiment, the correction circuit further includes a bidirectional offset control circuit;

[0013] The compensation current provided by the current compensator is input to the offset generating device through the bidirectional offset control circuit to stabilize the offset voltage within the offset range; the offset generating device is a component that causes the reference voltage to generate an offset voltage.

[0014] In one embodiment, the offset generating device includes a buffer and an amplifier; wherein the phase of the compensation current input to the buffer is different from the phase of the compensation current input to the amplifier.

[0015] In one embodiment, the calibration circuit includes a first phase calibration circuit and a second phase calibration circuit; the first phase calibration circuit and the second phase calibration circuit respectively fine-tune and calibrate the offset voltage at different phases.

[0016] In one embodiment, the first phase calibration circuit includes a first voltage-to-current converter, and the second phase calibration circuit includes a second voltage-to-current converter.

[0017] An amplifier is used to convert the offset voltage generated by the buffer into a first offset current in the first phase; or, in the second phase, the input is short-circuited and the offset voltage generated by itself is converted into a second offset current.

[0018] The target quantizer is used to integrate the first offset current to obtain the corresponding first voltage signal; or, to integrate the second offset current to obtain the corresponding second voltage signal.

[0019] A first voltage-to-current converter is used to generate a first fine-tuning compensation current based on a first voltage signal, and to compensate the buffer with the first fine-tuning compensation current;

[0020] The second voltage-to-current converter is used to generate a second fine-tuning compensation current based on the second voltage signal and to compensate the amplifier with the second fine-tuning compensation current.

[0021] Secondly, embodiments of this application provide a readout circuit, which includes: a coarse quantizer, a sample-and-hold circuit, a fine quantizer, and an offset voltage elimination circuit;

[0022] The coarse quantizer is used to coarsely quantize the analog signal of the target device to obtain the first quantized signal. The reference voltage of the coarse quantizer is the voltage after offset voltage elimination processing by the offset voltage elimination circuit. The elimination processing includes preliminary correction of the offset voltage in the reference voltage of the coarse quantizer so that the corrected offset voltage is stabilized within the preset offset level, and fine adjustment and calibration of the corrected offset voltage.

[0023] A sample-and-hold circuit is used to perform sample-and-hold processing on the first quantized signal;

[0024] The fine quantizer is used to fine quantize the first quantized signal after sample-and-hold processing to obtain the quantized value corresponding to the analog signal.

[0025] In one embodiment, the coarse quantizer is an integrator and the fine quantizer is an analog-to-digital converter.

[0026] In one embodiment, multiple coarse quantizers correspond to one fine quantizer.

[0027] Thirdly, embodiments of this application provide a processor that includes the readout circuit provided in any of the embodiments of the second aspect.

[0028] Fourthly, embodiments of this application provide a method for eliminating offset voltage, the method comprising:

[0029] The offset voltage in the reference voltage of the target quantizer is initially corrected so that the corrected offset voltage is stabilized within the preset offset range.

[0030] The corrected offset voltage is fine-tuned and calibrated to eliminate the offset voltage and obtain the accurate reference voltage of the target quantizer.

[0031] Fifthly, embodiments of this application provide an offset voltage elimination device, the device comprising:

[0032] The coarse adjustment module is used to perform preliminary correction on the offset voltage in the reference voltage of the target quantizer so that the corrected offset voltage is stabilized within a preset offset range.

[0033] The fine-tuning module is used to fine-tune and calibrate the corrected offset voltage to eliminate the offset voltage and obtain the accurate reference voltage of the target quantizer.

[0034] In a sixth aspect, embodiments of this application provide a computer device, including a memory and a processor. The memory stores a computer program, and when the computer program is executed by the processor, the processor performs the steps provided in the fourth aspect embodiment.

[0035] In a seventh aspect, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps provided in the fourth aspect embodiment.

[0036] This application provides an offset voltage elimination circuit, method, readout circuit, apparatus, and device. A correction circuit initially corrects the offset voltage in the reference voltage of the target quantizer to stabilize it within a preset offset range. Then, a calibration circuit fine-tunes the corrected offset voltage to eliminate it, resulting in a precise reference voltage for the target quantizer. Thus, through two offset calibration processes, large offset amplitudes are quickly corrected to a smaller offset range, while remaining offset is fine-tuned, thereby eliminating the offset voltage in the quantizer's reference voltage and ensuring a more accurate reference voltage source. Furthermore, the offset voltage elimination circuit only requires sampling the two calibration steps, simplifying the circuit design, saving chip area, and reducing power consumption. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or in the conventional technology, the drawings used in the description of the embodiments or in the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the readout circuit framework in one embodiment;

[0039] Figure 2 This is a schematic diagram of the offset voltage cancellation circuit in one embodiment;

[0040] Figure 3 This is a schematic diagram of the offset voltage cancellation circuit in another embodiment;

[0041] Figure 4 This is a schematic diagram of the offset voltage cancellation circuit in another embodiment;

[0042] Figure 5 This is a schematic diagram of the offset voltage cancellation circuit in another embodiment;

[0043] Figure 6 This is a schematic diagram of the offset voltage cancellation circuit in another embodiment;

[0044] Figure 7 This is a schematic diagram of the offset voltage cancellation circuit in another embodiment;

[0045] Figure 8 This is a schematic diagram of the offset voltage cancellation circuit in another embodiment;

[0046] Figure 9This is a schematic diagram of the offset voltage cancellation circuit in another embodiment;

[0047] Figure 10 This is a schematic diagram of the offset voltage cancellation circuit in another embodiment;

[0048] Figure 11 This is a schematic diagram of the offset voltage cancellation circuit in another embodiment;

[0049] Figure 12 This is a schematic diagram of the readout circuit framework in one embodiment;

[0050] Figure 13 This is a schematic diagram of the offset voltage elimination method in one embodiment;

[0051] Figure 14 This is a schematic diagram of the frame of an offset voltage elimination device in one embodiment.

[0052] Explanation of reference numerals in the attached figures:

[0053] 10: Offset voltage cancellation circuit; 20: Readout circuit;

[0054] 101: Correction circuit; 102: Calibration circuit;

[0055] 103: Target quantizer; 104: Offset generator;

[0056] 1011: Comparator; 1012: Analog-to-digital converter;

[0057] 1013: Current compensator; 1014: Bidirectional offset control circuit;

[0058] 1021: First phase calibration circuit; 1022: Second phase calibration circuit;

[0059] 10211: First voltage-to-current converter; 10221: Second voltage-to-current converter;

[0060] 1041: Buffer; 1042: Amplifier;

[0061] 201: Coarse quantizer; 202: Sample and hold circuit;

[0062] 203: Quantizer; 30: Offset voltage elimination device;

[0063] 301: Coarse adjustment module; 302: Fine adjustment module. Detailed Implementation

[0064] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this application belong. The terminology used herein in the description of embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of this application.

[0066] It is understood that the terms "first," "second," etc., used in the embodiments of this application may be used to describe various elements herein, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the embodiments of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor. It is also understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., transmit electrical signals or data to each other.

[0067] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, integrals, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integrals, steps, operations, components, parts, or combinations thereof. It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this specification and claims, the singular forms of “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term “and / or” as used in this specification and claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0068] like Figure 1The diagram illustrates a system structure of a readout circuit. Specifically, the readout circuit is used for CT detectors, PET detectors, or other detectors, or for other applications. Taking a dedicated integrated readout circuit for CT detectors as an example, in practical applications, to improve the quantization accuracy of analog signals in a short time, dedicated integrated readout circuits for CT detectors mostly employ a coarse quantizer to first coarsely quantize the photoelectric analog signal collected by the photodiode, and then send the remaining signal to a fine quantizer for fine quantization. In the readout circuit, the front-end integrator is equivalent to the coarse quantizer, and the back-end analog-to-digital converter is equivalent to the fine quantizer. In application, both the coarse and fine quantizers require a reference voltage source. However, in practical applications, the reference voltage sources of both the coarse and fine quantizers have certain noise. For example, the coarse quantizer has offset and flicker noise. The noise of the coarse quantizer determines the noise level of the entire system, so it is necessary to denoise the coarse quantizer so that the readout circuit can achieve photocurrent readout with low noise and high accuracy. The noise of the fine quantizer is not the dominant factor in the overall system. Its reference voltage source can tolerate a certain amount of noise, so no additional noise reduction is needed. It can be eliminated directly through the system-level consistency gain calibration algorithm.

[0069] In related technologies, the techniques and methods for precise reference voltage sources for low-noise, high-precision photocurrent readout circuits mainly include the following two types:

[0070] (1) Taking 20-bit precision as an example, for a 20-bit low-noise high-precision photocurrent readout circuit, in order to achieve a precision requirement of more than 20 bits in the shortest time, many high-precision photocurrent readout circuits use current integration, then coarse quantization in the charge domain, and then fine quantization of the remaining part. To achieve high precision, low noise, and low mismatch in both the coarse and fine quantization reference voltage sources, it is necessary to design very high power consumption and very complex circuits.

[0071] (2) To achieve the aforementioned high precision, in some scenarios, high precision can be achieved without circuitry, but rather through manual calibration (trimming). However, in practical applications, computed tomography (CT) modules contain a large number of chips. If the coarse adjustment reference voltage of each chip requires trimming, it will significantly increase the testing time of the automatic test equipment (ATE), thereby increasing chip costs. Moreover, trimming is a one-time calibration, making it difficult to suppress deviations caused by process-voltage-temperature (PVT) factors such as manufacturing process and temperature. Therefore, manual calibration leads to long testing times, increased chip costs, and inherently poor calibration accuracy.

[0072] Therefore, the design of the reference voltage source for the quantizer in the above two situations in related technologies has some defects. For example, the designs listed above have defects such as high power consumption, complex design, high manual calibration cost, and inability to effectively suppress deviations caused by factors such as process temperature. Based on this, embodiments of this application provide an offset voltage elimination circuit, method, readout circuit, device, and apparatus, which can eliminate the offset voltage of the quantizer's reference voltage, ensuring a more accurate reference voltage source for the quantizer. It should be noted that the offset voltage elimination circuit, method, readout circuit, device, and apparatus provided in embodiments of this application are not limited to achieving the above-mentioned technical effects, but can also achieve other technical effects. For example, the offset voltage elimination circuit, method, readout circuit, device, and apparatus provided in embodiments of this application only require a two-step calibration process circuit, making the circuit design simpler, saving chip area, and reducing power consumption.

[0073] Please see Figure 2 As shown, this application embodiment provides an offset voltage elimination circuit 10, which includes a correction circuit 101 and a calibration circuit 102. The correction circuit 101 is used to initially correct the offset voltage in the reference voltage of the target quantizer 103 so that the corrected offset voltage is stabilized within a preset offset level. The calibration circuit 102 is used to fine-tune and calibrate the corrected offset voltage to eliminate the offset voltage and obtain the accurate reference voltage of the target quantizer 103.

[0074] In practical applications, the target quantizer can be a coarse quantizer in the readout circuit. For example, the coarse quantizer can be an integrator or an analog-to-digital converter at the front end of the readout circuit.

[0075] Generally, the offset voltage in the reference voltage of the coarse quantizer is caused by large manufacturing process deviations in some components connected to the reference voltage terminal of the target quantizer, and it is one of the inherent noises of semiconductors. Therefore, the offset voltage in the reference voltage of the coarse quantizer can be eliminated by the offset voltage cancellation circuit 10 provided in this embodiment.

[0076] Please see Figure 3 The diagram shows a connection schematic of an offset generating device (a component connected to the reference voltage terminal of the target quantizer) in an offset voltage cancellation circuit 10. The input terminal of the offset generating device 104 is the reference voltage terminal Vref of the target quantizer 103, while the output terminal of the offset generating device 104 is connected to the input terminal of the target quantizer 103. The output terminal of the target quantizer 103 is connected to the correction circuit 101 and the calibration circuit 102.

[0077] exist Figure 2In this circuit, the reference voltage of the target quantizer 103 is output from the reference voltage terminal Vref. After passing through the offset generation device 104 to the target quantizer 103, the offset voltage generated by the offset generation device 104 carries the reference voltage of the target quantizer 103 into the correction circuit 101 and the calibration circuit 102. The correction circuit 101 performs preliminary correction on the offset voltage, stabilizing it within a preset offset range. This preliminary correction is essentially a rapid correction process, quickly correcting large offsets to a smaller offset range. Then, the calibration circuit 102 performs fine-tuning and calibration on the corrected offset voltage, thereby eliminating the offset voltage from the offset generation device and obtaining the accurate reference voltage of the target quantizer 103. For example, the reference voltage after eliminating the offset voltage can achieve 20-bit accuracy.

[0078] The offset voltage elimination circuit provided in this embodiment performs preliminary correction on the offset voltage in the reference voltage of the target quantizer through a correction circuit, stabilizing the corrected offset voltage within a preset offset range. Then, a calibration circuit performs fine-tuning on the corrected offset voltage to eliminate the offset voltage, resulting in a precise reference voltage for the target quantizer. Thus, through two offset calibration processes, it quickly corrects large offset amplitudes to a smaller offset range, while fine-tuning the remaining offset, thereby eliminating the offset voltage in the quantizer's reference voltage and ensuring a more accurate reference voltage source. Furthermore, requiring only two steps of the calibration process simplifies the circuit design, saves chip area, and reduces power consumption.

[0079] Based on the above embodiments, the correction circuit 101 and calibration circuit 102 in the offset voltage elimination circuit 10 will be described below.

[0080] Based on any of the above embodiments, such as Figure 4 As shown, this application provides an offset voltage elimination circuit 10. In this offset voltage elimination circuit 10, the correction circuit 101 includes: a comparator 1011, an analog-to-digital converter 1012, and a current compensator 1013. The comparator 1011 is used to obtain a potential signal based on the voltage signal converted from the offset voltage. The analog-to-digital converter 1012 is used to generate a control signal based on the potential signal, and control the current compensator 1013 to provide a compensation current through the control signal. The compensation current is used to stabilize the offset voltage within the offset range.

[0081] In this embodiment, the input terminal of comparator 1011 is connected to the output terminal of target quantizer 103, the output terminal of comparator 1011 is connected to the input terminal of analog-to-digital converter 1012, and the output terminal of analog-to-digital converter 1012 is connected to the input terminal of current compensator 1013. Thus, after the offset voltage enters comparator 1011, comparator 1011 can obtain a potential signal based on the voltage signal converted from the offset voltage and output this potential signal to analog-to-digital converter 1012. Analog-to-digital converter 1012 can generate a control signal based on the potential signal. This control signal enters the current compensator and controls the current compensator to output a corresponding compensation current. This compensation current ultimately compensates the component (offset generating device) that generates the aforementioned offset voltage. The current compensation has a calibrating effect on the offset and suppresses it, thereby stabilizing the offset voltage within the offset range.

[0082] like Figure 5 As shown, in one embodiment, the correction circuit 101 further includes: a bidirectional offset control circuit 1014; the compensation current provided by the current compensator 1013 is input to the offset generating device 104 through the bidirectional offset control circuit 1014 to stabilize the offset voltage within the offset range; the offset generating device 104 is a component that causes the reference voltage to generate an offset voltage.

[0083] Specifically, the input terminal of the bidirectional offset control circuit 1014 is connected to the output terminal of the current compensator 1013, and the output terminal of the bidirectional offset control circuit 1014 is connected to the offset generating device 104. Figure 5 In the process, the compensation current of the current compensator 1013 is compensated to the offset generating device 104 through the bidirectional offset control circuit 1014. The current compensation has a calibration effect on the offset, which suppresses the offset and stabilizes the offset voltage within the offset range, thereby eliminating the offset voltage in the reference voltage and making the reference voltage source of the quantizer more accurate.

[0084] In one embodiment, the offset generating device 104 includes a buffer 1041 and / or an amplifier 1042.

[0085] like Figure 6 As shown, the input terminal of buffer 1041 is the reference voltage terminal Vref of target quantizer 103, and the output terminal of buffer 1041 is connected to the input terminal of amplifier 1042; the output terminal of amplifier 1042 is connected to the input terminal of target quantizer 103. The compensation current provided by the aforementioned current compensator 1013 is input to buffer 1041 and / or amplifier 1042 respectively through bidirectional offset control circuit 1014.

[0086] In practical applications, the phase of the compensation current input to the buffer 1041 is different from the phase of the compensation current input to the amplifier 1042. For example, the phase of the compensation current input to the buffer 1041 is the first phase ph1, and the phase of the compensation current input to the amplifier 1042 is ph2. The first phase ph1 and the second phase ph2 are different, and the compensation current is not applied simultaneously with the first phase ph1 and the second phase ph2.

[0087] When the reference voltage output from the reference voltage terminal Vref passes through the buffer and amplifier, the buffer and amplifier will generate an offset voltage carried in the reference voltage, so that the final reference voltage of the target quantizer 103 carries an offset voltage.

[0088] In practical applications, buffers can be used to ensure the synchronous transmission of data or clocks, and amplifiers can amplify signals. This application does not limit the implementation structure of buffers and amplifiers, and the design can be based on actual needs.

[0089] Based on the above embodiments, a schematic diagram of the implementation structure of the correction circuit is provided for the buffer 1041 and amplifier 1042 under different phases.

[0090] In one embodiment, such as Figure 7 As shown, Figure 7 In the diagram, buffer represents a buffer, AZ1 represents an amplifier, INT represents a target quantizer, CMP represents a comparator, 5-bit SAR represents an analog-to-digital converter, IDAC represents a current compensator, A represents a bidirectional offset control circuit, and ph1 and ph2 are switches for the two phases, respectively.

[0091] in, Figure 7 The 5-bit SAR analog-to-digital converter, the IDAC current compensator, and the bidirectional offset control circuit A each include two, representing the first phase ph1 and the second phase ph2, respectively.

[0092] against Figure 7The buffer in the circuit has an offset voltage of Vos1, and for amplifier AZ1, the offset voltage is Vos2. For Vos1, the reference voltage output from the reference voltage terminal Vref at the first phase ph1 is generated by the buffer and enters the target quantizer INT. Then, it enters the comparator CMP. The comparator CMP can obtain a potential signal based on the voltage signal converted from the offset voltage and output this potential signal to the 5-bit analog-to-digital converter SAR on the side corresponding to the first phase ph1. The 5-bit analog-to-digital converter SAR on the side corresponding to the first phase ph1 can generate a control signal based on the potential signal. This control signal enters the current compensator IDAC on the side corresponding to the first phase ph1, thereby controlling the current compensator IDAC to output the corresponding compensation current. This compensation current ultimately compensates the buffer, suppressing and calibrating the Vos1 generated by the buffer, stabilizing Vos1 within the offset range, and achieving the initial correction of Vos1.

[0093] Similarly, for Vos2, the reference voltage output from the reference voltage terminal Vref under the second phase ph2 is amplified by amplifier AZ1 to generate Vos2, which then enters the target quantizer INT and then the comparator CMP. The comparator CMP can obtain a potential signal based on the voltage signal converted from the offset voltage and output the potential signal to the 5-bit SAR analog-to-digital converter on the corresponding side of the second phase ph2. The 5-bit SAR analog-to-digital converter on the corresponding side of the second phase ph2 can generate a control signal based on the potential signal. This control signal enters the current compensator IDAC on the corresponding side of the second phase ph2, thereby controlling the current compensator IDAC to output the corresponding compensation current. This compensation current can finally compensate the amplifier AZ1 to suppress and calibrate the Vos2 generated by the amplifier AZ1, stabilizing Vos2 within the offset range and achieving the initial correction of Vos2.

[0094] The above describes the implementation structure of the correction circuit 101. Based on the above embodiment, the implementation structure of the calibration circuit 102 in the offset voltage elimination circuit 10 will be described below.

[0095] Based on any of the above embodiments, such as Figure 8 As shown, in one embodiment, an offset voltage cancellation circuit 10 is provided. The calibration circuit 102 in the offset voltage cancellation circuit 10 includes: a first phase calibration circuit 1021 and a second phase calibration circuit 1022; the first phase calibration circuit 1021 and the second phase calibration circuit 1022 respectively perform fine-tuning calibration of the offset voltage at different phases.

[0096] In this embodiment, the input terminals of the first phase calibration circuit 1021 and the second phase calibration circuit 1022 are both connected to the output terminal of the target quantizer 103, and the output terminals of the first phase calibration circuit 1021 and the second phase calibration circuit 1022 are both connected to the offset generating device 104.

[0097] The first phase calibration circuit 1021 and the second phase calibration circuit 1022 are used to fine-tune the offset voltages of different phases. For example, in the first phase ph1, the offset voltage generated by the buffer is fine-tuned, and in the second phase ph2, the offset voltage generated by the amplifier is fine-tuned.

[0098] In one embodiment, such as Figure 9 As shown, the first phase calibration circuit 1021 includes a first voltage-to-current converter 10211, and the second phase calibration circuit 1022 includes a second voltage-to-current converter 10221; an amplifier 1042 is used to convert the offset voltage generated by the buffer 1041 into a first offset current in the first phase; or, in the second phase, the input is short-circuited, and the offset voltage generated by itself is converted into a second offset current; a target quantizer 103 is used to integrate the first offset current to obtain a corresponding first voltage signal; or, to integrate the second offset current to obtain a corresponding second voltage signal; the first voltage-to-current converter 10211 is used to generate a first fine-tuning compensation current based on the first voltage signal and compensate the buffer 1041 with the first fine-tuning compensation current; the second voltage-to-current converter 10221 is used to generate a second fine-tuning compensation current based on the second voltage signal and compensate the amplifier 1042 with the second fine-tuning compensation current.

[0099] In this embodiment, the input terminals of the first voltage-to-current converter 10211 and the second voltage-to-current converter 10221 are both connected to the output terminal of the target quantizer. The output terminal of the first voltage-to-current converter 10211 is connected to the buffer 1041, and the output terminal of the second voltage-to-current converter 10221 is connected to the amplifier 1042.

[0100] In practical applications, in the first phase, the offset voltage generated by the buffer passes through an amplifier. The amplifier converts the offset voltage generated by the buffer and outputs a first offset current. This first offset current enters the target quantizer, which integrates the first offset current to obtain the corresponding first voltage signal. Based on this first voltage signal, the first voltage-to-current converter can generate a first fine-tuning compensation current. This first fine-tuning compensation current enters the buffer, thereby fine-tuning and calibrating the offset voltage generated by the buffer to further eliminate the offset voltage of the buffer.

[0101] In the second phase, the offset voltage generated by the amplifier is converted by the amplifier itself to output a second offset current. This second offset current enters the target quantizer, which integrates the second offset current to obtain the corresponding second voltage signal. Based on this second voltage signal, the second voltage-to-current converter can generate a second fine-tuning compensation current. This second fine-tuning compensation current enters the amplifier to fine-tune and calibrate the offset voltage generated by the amplifier, thereby further eliminating the amplifier's offset voltage.

[0102] Specifically, such as Figure 10 As shown, Figure 10 In this diagram, `buffer` represents a buffer, `AZ1` represents an amplifier, `INT` represents a target quantizer, `ph1` and `ph2` are switches for two phases respectively, `AZ2` represents a second voltage-to-current converter, and `AZ3` represents a first voltage-to-current converter. (For...) Figure 10 The buffer in the middle has an offset voltage of Vos1, and the amplifier AZ1 has an offset voltage of Vos2.

[0103] Therefore, for Vos1, under the first phase ph1, the reference voltage output from the reference voltage terminal Vref is buffered to generate Vos1, which first enters amplifier AZ1. Amplifier AZ1 converts Vos1 and outputs the first offset current. The first offset current enters the target quantizer INT. The target quantizer INT integrates the first offset current to obtain the corresponding first voltage signal. Then, the first voltage signal enters the first voltage-to-current converter AZ3. The first voltage-to-current converter AZ3 can generate the first fine-tuning compensation current from the first voltage signal, which will enter the buffer again, thereby fine-tuning and calibrating the Vos1 generated by the buffer to further eliminate the Vos1 in the buffer.

[0104] For Vos2, the reference voltage output from the reference voltage terminal Vref under the second phase ph2 is used to generate Vos2 through amplifier AZ1. Amplifier AZ2 converts Vos2 and outputs a second offset current. The second offset current enters the target quantizer INT. The target quantizer INT integrates the second offset current to obtain the corresponding second voltage signal. Then the second voltage signal enters the second voltage-to-current converter AZ2. The second voltage-to-current converter AZ2 can generate a second fine-tuning compensation current from the second voltage signal, which will enter amplifier AZ1 again, thereby fine-tuning and calibrating the Vos2 generated by amplifier AZ1 to further eliminate the Vos2 of amplifier AZ1.

[0105] exist Figure 10 In addition, it should be noted that Figure 10It also includes filter capacitors C1, C2, Cint31, Cint21, Cint32, Cint22, C31, C32, C21, and C22. These filter capacitors can be set according to actual needs, and they can eliminate high-frequency components in the circuit to achieve the filtering effect.

[0106] In this embodiment, the offset voltage generated by different offset generating devices is finely adjusted and calibrated by different phase calibration circuits under different phases, thereby eliminating the offset voltage and making the reference voltage of the target quantizer more accurate.

[0107] In addition, combined Figure 11 , Figure 11 The meanings of the components can be found in the preceding text. Figure 7 and Figure 10 The explanation will not be repeated here. So, in... Figure 11 The process of eliminating offset voltage in the coarse quantizer reference voltage is explained in two different ways.

[0108] In one embodiment, Figure 11 The process can be understood as including two steps: rapid correction and fine adjustment. For cases with large offset amplitudes, rapid correction is performed to reduce the offset to a smaller level. Then, the remaining offset after rapid adjustment is fine-tuned and calibrated to obtain the accurate reference voltage of the coarse quantizer.

[0109] Therefore, when eliminating the offset voltage of the coarse quantizer, this embodiment includes the following process:

[0110] (1) To quickly correct large offsets to a smaller offset level, the circuit for this process can be implemented using a mixed-signal circuit.

[0111] Specifically, this part of the mixed-signal circuit includes a comparator CMP, a 5-bit analog-to-digital converter SAR, a current compensator IDAC (also known as a current-to-analog converter), and a bidirectional offset control circuit.

[0112] The integrator INT generates an offset voltage based on the output current of AZ1. This offset voltage serves as the input to the comparator CMP. The comparator CMP outputs a potential signal based on this offset voltage. This potential signal, at different phases ph1 or ph2, enters the corresponding 5-bit SAR of the analog-to-digital converter. The 5-bit SAR provides a control signal to the current-to-analog converter IDAC based on this potential signal. This control signal controls the magnitude of the compensation current provided by the current-to-analog converter IDAC. The compensation current is then supplied to amplifier AZ1 or the buffer. Since the compensation current has a calibrating effect on the offset, essentially suppressing it, this compensation current can quickly reduce the offset. Figure 11 The offset voltages Vos1 and Vos2 in the system remain stable within a small range.

[0113] (2) The process of fine-tuning and calibrating the remaining offset after rapid adjustment can be achieved through analog circuits. This part mainly includes the AZ1, INT, and AZ2 loops in phase ph2. This loop performs self-zeroing on the offset of AZ1, etc. At this time, the input of AZ1 is short-circuited, and the output current of AZ1 is integrated through INT. The offset voltage generated after INT integration will enter the voltage-to-current converter AZ2. AZ2 will convert the offset voltage generated by INT integration into current compensation to amplifier AZ1, thereby eliminating the offset voltage Vos2 in the coarse quantizer, so as to achieve fine-tuning and calibration of the offset voltage Vos2 in the reference voltage of the coarse quantizer.

[0114] In phase ph1, the circuit mainly includes AZ1, INT, AZ2, and a buffer loop. This loop primarily calibrates the buffer offset. At this point, AZ1 captures the buffer offset voltage Vos1 as its input. The output current of AZ1 is integrated at INT. The offset voltage generated after integration by INT enters the voltage-to-current converter AZ3. AZ3 converts the offset voltage generated by INT integration into current compensation for the amplifier buffer, thereby eliminating the offset voltage Vos1 in the coarse quantizer and achieving fine-tuning calibration of the offset voltage in the coarse quantizer's reference voltage.

[0115] In another embodiment, see above. Figure 11 As shown, Figure 11 This can be understood as a calibration process with two phases, each phase corresponding to the elimination of a type of offset voltage. Specifically, phase ph2 eliminates the offset voltage Vos2 at amplifier AZ1, and phase ph1 eliminates the offset voltage Vos1 at the buffer, thereby obtaining the accurate reference voltage for the coarse quantizer.

[0116] Specifically, when eliminating the offset voltage of the coarse quantizer, this embodiment includes the following process: (1) Eliminating the offset voltage Vos2 at amplifier AZ1 is based on the principle that ph2 is closed and ph1 is open. At this time, the input of AZ1 is short-circuited, that is, the output current of AZ1 enters the integrator INT after being output from amplifier AZ1.

[0117] On one hand, the offset voltage generated after INT integration will be used as the input of comparator CMP. Based on this offset voltage, comparator CMP will output a potential signal. This potential signal will enter the 5-bit analog-to-digital converter SAR through the Ph2 terminal. The 5-bit SAR can provide a control signal to the current-to-analog converter IDAC according to this potential signal. This control signal is used to control the magnitude of the compensation current provided by the current-to-analog converter IDAC. The compensation current compensates to amplifier AZ1. Since the compensation current has a calibration effect on the offset, which is equivalent to the suppression of the offset, the compensation current can quickly stabilize the offset voltage Vos2 within a small range.

[0118] On the other hand, the offset voltage generated after INT integration will enter the voltage-to-current converter AZ2. AZ2 will convert the offset voltage generated by INT integration into current compensation for amplifier AZ1, thereby eliminating the offset voltage Vos2 in the coarse quantizer, so as to achieve fine adjustment and calibration of the offset voltage Vos2 in the reference voltage of the coarse quantizer.

[0119] (2) The principle for eliminating the offset voltage Vos1 at the buffer is as follows: ph2 is open and ph1 is closed. At this time, amplifier AZ1 captures the offset voltage Vos1 of the buffer and uses it as the input of AZ1. That is, the output current of AZ1 enters INT for integration.

[0120] On one hand, the offset voltage generated after INT integration will be used as the input of comparator CMP. Based on this offset voltage, comparator CMP will output a potential signal. This potential signal will enter the 5-bit analog-to-digital converter SAR through the Ph1 terminal. The 5-bit SAR can provide a control signal to the current-to-analog converter IDAC according to the potential signal. This control signal is used to control the magnitude of the compensation current provided by the current-to-analog converter IDAC. The compensation current compensates to amplifier AZ1. Since the compensation current has a calibration effect on the offset, it is equivalent to suppressing the offset. Therefore, the compensation current can quickly stabilize the offset voltage Vos1 within a small range.

[0121] On the other hand, the offset voltage generated after INT integration will enter the voltage-to-current converter AZ3. AZ3 will convert the offset voltage generated by INT integration into current compensation to the amplifier buffer, thereby eliminating the offset voltage Vos1 in the coarse quantizer, so as to achieve fine adjustment and calibration of the offset voltage in the reference voltage of the coarse quantizer.

[0122] in addition, Figure 11The filter capacitors C1, C2, Cint31, Cint21, Cint32, Cint22, C31, C32, C21, and C22 in the circuit can be set according to actual needs. They can eliminate high-frequency components in the circuit and achieve the filtering effect.

[0123] The above embodiments illustrate the process of eliminating offset voltage in the reference voltage of the target quantizer in different ways. Regardless of the method, different currents are fed back to the offset generation device to suppress the offset voltage, thereby eliminating the offset voltage in the reference voltage of the target quantizer and ensuring that the reference voltage source of the target quantizer is more accurate.

[0124] The above describes the process of offset voltage elimination calibration for the reference voltage of the coarse quantizer in the readout circuit. In one embodiment, for the fine quantizer in the readout circuit, since the noise of the reference voltage source of the fine quantizer is not dominant in the whole system, it is not necessary to eliminate its flicker noise. Moreover, the error caused by its mismatch or offset only changes the size of the least significant bit (LSB) of the fine quantizer, which is equivalent to introducing a linear gain error. This linear gain error can be eliminated in the system-level consistency gain calibration.

[0125] In practical applications, the mismatch in the reference voltage source buffer of the fine quantizer will be converted into LSB difference in the fine quantizer, which is only a linear gain error and will be eliminated in the system-level consistency gain calibration. For example, when the fine quantizer is used as a subsequent stage circuit, it is equivalent to having a fixed gain at the input to reduce noise.

[0126] Based on any of the above offset voltage cancellation circuits, such as Figure 12 As shown in the figure, this application embodiment also provides a readout circuit 20, which includes a coarse quantizer 201, a sample-and-hold circuit 202, a fine quantizer 203, and an offset voltage elimination circuit 10. The coarse quantizer 201 is used to coarsely quantize the analog signal to obtain a first quantized signal. The reference voltage of the coarse quantizer 201 is the voltage after offset voltage elimination processing by the offset voltage elimination circuit 10. The elimination processing includes initially correcting the offset voltage in the reference voltage of the coarse quantizer to stabilize the corrected offset voltage within a preset offset level, and then finely adjusting and calibrating the corrected offset voltage. The sample-and-hold circuit 202 is used to perform sample-and-hold processing on the first quantized signal. The fine quantizer 203 is used to finely quantize the first quantized signal after sample-and-hold processing to obtain the quantized value corresponding to the analog signal.

[0127] In one embodiment, the coarse quantizer is an integrator, and the fine quantizer is an analog-to-digital converter.

[0128] In one embodiment, multiple coarse quantizers correspond to one fine quantizer.

[0129] The readout circuit provided in this embodiment can be found in [reference]. Figure 1 The description of the provided readout circuit system framework will not be repeated here.

[0130] Additionally, embodiments of this application also provide a processor that includes any of the readout circuits provided in the preceding embodiments. In one embodiment, a computer device is also provided that includes a processor implemented with any of the readout circuits.

[0131] A processor can be viewed as a very large-scale integrated circuit, which includes an arithmetic logic unit (ALU), a control unit, registers, memory, and readout circuits, etc. Processors include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), digital signal processing units (DSPs), and application-specific integrated circuits (ASICs), etc., but the embodiments of this application do not limit this to a specific type.

[0132] Computer equipment refers to any terminal or electronic device that requires an external power source or has a built-in power source, such as various personal computers, laptops, mobile phones (smart mobile terminals), tablets, and portable wearable devices. This embodiment does not limit the scope of the application. If an external power source is used, it can be a power adapter, a portable power bank (power bank, travel charger), etc., and this embodiment also does not limit the application of this application. The computer equipment may include a processor implemented using any type of readout circuitry.

[0133] In addition, embodiments of this application also provide a method for eliminating offset voltage, such as... Figure 13 As shown, this offset voltage elimination method can be applied to a readout circuit. This embodiment includes:

[0134] S101 performs preliminary correction on the offset voltage in the reference voltage of the target quantizer so that the corrected offset voltage is stabilized within the preset offset level.

[0135] S102 performs fine-tuning and calibration on the corrected offset voltage to eliminate the offset voltage and obtain the accurate reference voltage of the target quantizer.

[0136] Specifically, a pre-set program instruction for offset voltage elimination can be implemented. Upon receiving this instruction, the computer device executes the corresponding operation: according to the pre-set program instruction, it initially corrects the offset voltage in the reference voltage of the target quantizer to obtain a corrected offset voltage, stabilizing it within a preset offset range. Then, the computer device can continue to execute the pre-set program instruction to fine-tune and calibrate the corrected offset voltage to eliminate it, thus obtaining a precise reference voltage for the target quantizer.

[0137] It is understood that the above process is implemented through computer program instructions provided to the processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device, such that the instructions executed by the processor of the computer or other programmable data processing device can achieve the offset voltage elimination of this embodiment. Alternatively, these computer program instructions may also be stored in a computer-readable storage medium that can direct the computer or other programmable data processing device to operate in a specific manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means. Alternatively, these computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby executing the computer program instructions on the computer or other programmable device to achieve the above-described function.

[0138] The principles and logic of implementing each step according to the program instructions in this embodiment are the same as those in the embodiments of the readout circuit described above, and will not be repeated here. Of course, when combining program instructions to implement noise suppression, the implementation method can be adapted, and this application does not limit it.

[0139] Based on the above offset voltage elimination methods, such as Figure 14 As shown in the figure, this application embodiment also provides an offset voltage elimination device 30, which includes: a coarse adjustment module 301 and a fine adjustment module 302, wherein:

[0140] The coarse adjustment module 301 is used to perform preliminary correction on the offset voltage in the reference voltage of the target quantizer so that the corrected offset voltage is stabilized within a preset offset level.

[0141] The fine-tuning module 302 is used to fine-tune and calibrate the corrected offset voltage to eliminate the offset voltage and obtain the accurate reference voltage of the target quantizer.

[0142] The implementation principle of each step in the above offset voltage elimination device is the same as the principle and logic of each embodiment of the offset voltage elimination method, offset voltage elimination circuit, and readout circuit. Please refer to the foregoing description, and it will not be repeated here.

[0143] In addition, this application also provides a computer device, including a memory and a processor. The memory stores a computer program. When the computer program is executed by the processor, the processor performs the steps of any of the offset voltage elimination methods provided in the above embodiments.

[0144] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of any of the offset voltage elimination methods provided in the above embodiments.

[0145] In some embodiments, this application also provides a chip, which includes the offset voltage elimination circuit or the readout circuit provided in any of the above embodiments. In one implementation, the chip is a system-on-a-chip (SoC) and integrates multiple functional devices. The chip can be connected to other related components through external interface devices. These related components may be, for example, a camera, a monitor, a mouse, a keyboard, a network card, or a Wi-Fi interface. In some application scenarios, the chip may integrate other processing units (e.g., video codecs) and / or interface modules (e.g., DRAM interfaces). In some embodiments, this application also provides a chip package structure that includes the above-described chip. In some embodiments, this application also provides a board that includes the above-described chip package structure.

[0146] Based on the above description, those skilled in the art will understand that this application also provides an electronic device or apparatus that may include one or more of the aforementioned boards.

[0147] Depending on the application scenario, the electronic devices or apparatus of this application may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, dashcams, navigators, sensors, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, home appliances, and / or medical devices. The vehicles include airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound machines, and / or electrocardiographs. The electronic devices or apparatus of this application can also be applied in fields such as the Internet, IoT, data centers, energy, transportation, public management, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and healthcare. Furthermore, the electronic devices or apparatus of this application can also be used in cloud, edge, and terminal applications related to artificial intelligence, big data, and / or cloud computing. In one or more embodiments, the high-computing-power electronic devices or apparatuses according to the present application can be applied to cloud devices (e.g., cloud servers), while the low-power electronic devices or apparatuses can be applied to terminal devices and / or edge devices (e.g., smartphones or cameras). In one or more embodiments, the hardware information of the cloud devices and the hardware information of the terminal devices and / or edge devices are compatible with each other, so that suitable hardware resources can be matched from the hardware resources of the cloud devices to simulate the hardware resources of the terminal devices and / or edge devices based on the hardware information of the terminal devices and / or edge devices, so as to complete the unified management, scheduling and collaborative work of end-to-cloud or cloud-edge-end integration.

[0148] In this application, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network units. Furthermore, depending on actual needs, some or all of the units can be selected to achieve the purpose of the solution described in the embodiments of this application. Additionally, in some scenarios, multiple units in the embodiments of this application may be integrated into one unit or each unit may exist physically independently.

[0149] In some implementation scenarios, the integrated unit described above can be implemented as a software program module. If implemented as a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable storage device (CMSDD). Therefore, when the solution of this application is embodied in the form of a software product (e.g., a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to cause a computer device (e.g., a personal computer, server, or network device) to execute some or all of the steps of the method described in the embodiments of this application. The aforementioned memory may include, but is not limited to, various media capable of storing program code, such as USB flash drives, flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0150] In other implementation scenarios, the integrated units described above can also be implemented in hardware, i.e., as specific hardware circuits, which may include digital circuits and / or analog circuits. The physical implementation of the circuit's hardware structure may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors. Therefore, the various devices described herein (e.g., computing devices or other processing devices) can be implemented using appropriate hardware processors, such as CPUs, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage units or storage devices can be any suitable storage medium (including magnetic storage media or magneto-optical storage media), such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), ROM, and RAM.

[0151] While numerous embodiments of this application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will arise for those skilled in the art without departing from the spirit and intent of this application. It should be understood that various alternatives to the embodiments of this application described herein may be employed in the practice of this application. The appended claims are intended to define the scope of protection of this application and therefore cover equivalents or alternatives within the scope of these claims.

[0152] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0153] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. Furthermore, any changes or modifications made by those skilled in the art based on the ideas of this application, and on the specific implementation methods and application scope of this application, are all within the scope of protection of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An offset voltage elimination circuit, characterized in that, The offset voltage elimination circuit includes a correction circuit and a calibration circuit; the correction circuit includes a comparator, an analog-to-digital converter, and a current compensator. The comparator is used to obtain a potential signal from the voltage signal converted from the offset voltage in the reference voltage of the target quantizer; the analog-to-digital converter is used to generate a control signal based on the potential signal, and control the current compensator to provide a compensation current through the control signal; the compensation current is used to initially correct the offset voltage so that the corrected offset voltage is stabilized within a preset offset level. The calibration circuit is used to fine-tune and calibrate the corrected offset voltage to eliminate the offset voltage and obtain the accurate reference voltage of the target quantizer.

2. The offset voltage elimination circuit according to claim 1, characterized in that, The target quantizer is the coarse quantizer in the readout circuit.

3. The offset voltage elimination circuit according to claim 1 or 2, characterized in that, The correction circuit also includes: a bidirectional offset control circuit; The compensation current provided by the current compensator is input to the offset generating device through the bidirectional offset control circuit to stabilize the offset voltage within the offset range; the offset generating device is a component that causes the reference voltage to generate an offset voltage.

4. The offset voltage elimination circuit according to claim 3, characterized in that, The offset generating device includes a buffer and an amplifier; wherein the phase of the compensation current input to the buffer is different from the phase of the compensation current input to the amplifier.

5. The offset voltage elimination circuit according to claim 4, characterized in that, The calibration circuit includes a first phase calibration circuit and a second phase calibration circuit; the first phase calibration circuit and the second phase calibration circuit respectively fine-tune and calibrate the offset voltage at different phases.

6. The offset voltage elimination circuit according to claim 5, characterized in that, The first phase calibration circuit includes a first voltage-to-current converter, and the second phase calibration circuit includes a second voltage-to-current converter; The amplifier is configured to convert the offset voltage generated by the buffer into a first offset current in the first phase; or, in the second phase, the input is short-circuited and the offset voltage generated by itself is converted into a second offset current. The target quantizer is used to integrate the first offset current to obtain a corresponding first voltage signal; or, to integrate the second offset current to obtain a corresponding second voltage signal. The first voltage-to-current converter is configured to generate a first fine-tuning compensation current based on the first voltage signal, and to compensate the buffer with the first fine-tuning compensation current; The second voltage-to-current converter is used to generate a second fine-tuning compensation current based on the second voltage signal, and to compensate the amplifier with the second fine-tuning compensation current.

7. A readout circuit, characterized in that, The readout circuit includes: a coarse quantizer, a sample-and-hold circuit, a fine quantizer, and an offset voltage cancellation circuit; The coarse quantizer is used to coarsely quantize the analog signal of the target device to obtain a first quantized signal; the reference voltage of the coarse quantizer is the voltage after offset voltage elimination processing by the offset voltage elimination circuit; the elimination processing includes preliminary correction of the offset voltage in the reference voltage of the coarse quantizer so that the corrected offset voltage is stabilized within a preset offset level, and fine adjustment and calibration of the corrected offset voltage. The sample-and-hold circuit is used to perform sample-and-hold processing on the first quantized signal; The fine quantizer is used to fine quantize the first quantized signal after sample-and-hold processing to obtain the quantized value corresponding to the analog signal.

8. A method for eliminating offset voltage, characterized in that, The method includes: The potential signal is obtained by converting the offset voltage in the reference voltage of the target quantizer into a voltage signal; A control signal is generated based on the potential signal, and the current compensator is controlled by the control signal to provide a compensation current; the compensation current is used to initially correct the offset voltage so that the corrected offset voltage is stabilized within a preset offset level. The corrected offset voltage is finely tuned and calibrated to eliminate the offset voltage, thereby obtaining the accurate reference voltage of the target quantizer.

9. An offset voltage elimination device, characterized in that, The device includes: The coarse adjustment module is used to obtain a potential signal from the voltage signal converted from the offset voltage in the reference voltage of the target quantizer; generate a control signal based on the potential signal, and control the current compensator to provide a compensation current through the control signal; the compensation current is used to initially correct the offset voltage so that the corrected offset voltage is stabilized within a preset offset level. The fine-tuning module is used to fine-tune and calibrate the corrected offset voltage to eliminate the offset voltage and obtain the accurate reference voltage of the target quantizer.

10. A computer device, comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the computer program is executed by the processor, the processor performs the steps of the method as described in claim 8.

Images