Semiconductor device comprising an insulated gate field effect transistor connected in series with a field effect transistor

Abstract

A semiconductor device comprises an insulated gate field effect transistor (1) connected in series with a field effect transistor (2) FET, wherein the FET (2) comprises a plurality of parallel conductive layers (n1-n5, p1-p4), and wherein a substrate (11) of a first conductive type is arranged as a base of the semiconductor device so as to extend below the two transistors (1, 2), and a first layer (n1) of a second conductive type is arranged to extend above the substrate (11), wherein a plurality of conductive layers having channels are arranged on top of the first layer (n1), the channels being formed by a plurality of epitaxial layers (n2-n4) doped with the second conductive type, the epitaxial layers (n2-n4) doped with the second conductive type 2-n4) on both sides having a first conductivity type layer (p1-p4), wherein the uppermost layer (p5) of the device is preferably substantially thicker than several parallel conductive layers (p1-p4, n1-n4) directly below the surface, the field effect transistor (2) JFET is separated on the source side of the JFET by a second conductivity type deep polysilicon trench DNPT (22), the insulated gate field effect transistor (1) is separated by a first conductivity type deep polysilicon trench DPPT (22, 23) on both sides, and another separated area (5) including logic and analog control functions is separated by a first conductivity type deep polysilicon trench DPPT (23, 24) on both sides.

Description

[0001] The present invention relates to a semiconductor device comprising an insulated gate field effect transistor connected in series with a field effect transistor having improved voltage and current capabilities, in particular a device having very low on-resistance. The present invention is a further development of the applicant's previous application PCT / SE2019 / 050229 filed on March 14, 2019.

[0002] To combine high-voltage power devices with low-voltage analog and digital functions on the same chip, insulated-gate field-effect transistors (such as MOSFETs) connected in series with JFETs within the silicon have long been the industry's workhorse. To improve voltage and current capabilities, there has been an evolution from single-sided JFETs to symmetrical JFETs that reduce on-resistance by half, as described in U.S. Patent No. 4,811,075A, which describes an insulated-gate field-effect transistor and a double-sided junction-gate field-effect transistor connected in series on the same chip to form a high-voltage MOS transistor. Further developments have included JFETs with two series-connected channels, further reducing on-resistance by 30%, as shown in U.S. Patent No. 5,313,082A.

[0003] U.S. Patent No. 6,168,983 B1 further improved upon the latest patent by proposing a JFET with several parallel conductive layers implemented vertically in a common N-well or N-type epitaxial layer on top of the substrate. It was later shown that if the series connection of the insulated gate field effect transistor and the JFET were made externally, the on-resistance could be further reduced, high-frequency performance improved, and reliability increased, as described in U.S. Patent No. 8,264,015 B2. This patent also proposed implementing several parallel JFET channels in series with the insulated gate field effect transistor in a common N-well, with the size of the insulated gate field effect transistor optimized to match the number of JFET channels. Due to the external connection, this was not possible in U.S. Patent No. 6,168,983 B1, as the connection was internal to the silicon.

[0004] The number of parallel conductive layers is actually set by the insulated gate transistor and further by the depth of the N-well, which is set to 15 μm in this patent. A similar limitation exists in US Pat. No. 8,264,015 B2, where the number of parallel conductive layers is set by the implantation energy.

[0005] The proposed concept of creating multiple conducting layers by ion implantation was not as successful as expected due to the previously mentioned very high implant energy being a fundamental limitation.

[0006] Other limiting issues are radiative losses that reduce mobility and the expansion of the profile of the implanted atoms. The current state of the art is still 2 to 3 parallel conductive layers, for example according to Don Disney et al., "High-Voltage Integrated Circuits: History, State of the Art, And Future Prospects," IEEE Transactions on Electron Devices, March 2017, No. 3, Vol. 64.

[0007] Current methods propose that the conductive layer be made through epitaxial growth with better control, without radiation losses. Furthermore, As can be used instead of P as a dopant in ion implantation, thus providing higher mobility. Using epitaxial technology, there is essentially no limit to the number of conductive layers that can be produced in parallel.

[0008] Since the resistance of the conductive layer is known, an estimate of the performance can be easily achieved as the figure of merit Ron*A of the device:

[0009] For 6-8 conductive layers, we can get:

[0010] For a 230V device, Ron*A is approximately 100mΩmm 2 , while the current technology level is 500mΩmm 2

[0011] For a 700V device, Ron*A is approximately 2Ω*mm 2 , while the current technical level is 15Ω*mm 2 For example, according to Don Disney et al., "High-Voltage Integrated Circuits: History, State of the Art, And Future Prospects," IEEE Transactions on Electron Devices, March 2017, No. 3, Vol. 64.

[0012] The area advantage certainly means lower cost, but it also means significantly reduced capacitance, increased switching speed and higher efficiency. Even at 1200V, there is a real opportunity to compete with vertical power MOS devices and SiC devices.

[0013] All of these have a modest number of parallel conducting layers, 6-8. The number of layers can be easily increased, as there are no fundamental limitations, only practical limitations.

[0014] The present invention will now be further described with reference to several non-limiting embodiments shown in the accompanying drawings, including embodiments of previous applications, in which Figure 1 schematically shows a first embodiment of a semiconductor device according to a previous invention in the form of a MOS transistor in series with a JFET comprising several conductive layers, Figure 2 A second embodiment of a semiconductor device according to the previous invention in the form of a MOS transistor in series with a JFET comprising several conducting layers, two implanted p-layers in each epitaxial layer, is shown. Figure 3 It shows that a similar method is realized by using SOI technology of BOX layer. Figure 1 devices, Figure 4 Shows the method for creating and Figure 1 or Figure 3 Another optional gate implant mask for a Schottky diode in parallel with the grounded drain of the device, Figure 5 Shows the method for creating and Figure 2 Optional gate implant mask for a Schottky diode in parallel with the grounded drain of the device, Figure 6 The implementation of the SOI based on Figure 2 The device is a LIGBT device in which the drain doping has been changed to p+ and is in contact with the DPPT, thus creating a latch-up-free LIGBT. Figure 7 It shows a similar Figure 1 , a first embodiment of a semiconductor device in the form of a MOS transistor in series with a JFET comprising several conductive layers, with a p-type upper layer for CMOS compatibility, Figure 8 Shown Figure 1 An alternative solution for devices in which an additional conductive layer is provided in the bottom layer to reduce the overall resistance, Figure 9 It shows a similar Figure 2 , a second embodiment of a semiconductor device in the form of a MOS transistor in series with a JFET comprising several conductive layers, two implanted p-layers in each epitaxial layer with a p-type upper layer for CMOS compatibility, Figure 10 Shown Figure 2 An alternative solution for a semiconductor device is shown, wherein an additional conductive layer is provided in the bottom layer to reduce the overall resistance.

[0015] Figure 1The figure shows a MOS transistor 1 on the left connected in series with a JFET 2 on the right, the JFET 2 comprising several conductive layers, a JFET channel formed by parallel n-layers n1-n5 as shown and separated by a common p-layer p1-p4 (gate). The layers are deposited in situ in an epitaxial reactor, or in two reactors, where the n-layer is deposited in one reactor and the p-layer in the other. If two reactors are used, it is a huge advantage if the wafer is transferred from one reactor to the other under vacuum by an interlock. The first layer starts on top of a p-type substrate with a resistivity in the range of 10Ωcm to 135Ωcm. The thickness of the layers and the doping concentration are determined by the resurf principle, which means that the product of the thickness of the layer and the doping concentration should be approximately 2*10 per square centimeter. 12 charge, which means that the thickness and doping concentration can be changed as long as this condition is met.

[0016] The first channel region in the figure is selected to be 2 μm thick and the doping concentration is 1*10 16 / cm 3 , then, the above conditions are met. Then the thickness and doping concentration of the next layer are selected to be 0.5 μm and 4*10 16 / cm 3 of doping concentration, and in fact may also be of a thickness and doping concentration similar thereto.

[0017] As a practical example, the number of parallel n layers n1-n5 stops before the n5 epitaxial layer, which is preferably made thicker, 2.5 μm, and has a thickness of 0.5 μm as the upper gate and a charge of 1*10 12 The masked implanted px layer 17. The px layer 17 is only used as the gate of the uppermost channel, which makes the channel layer thickness 2μm and has 5*10 15 / cm 3 The channel layers are connected together on the drain side by a deep N-polysilicon trench (DNPT) 20, and the channel layers are also connected together on the source side by a deep N-polysilicon trench (DNPT) 21. JFET2 is separated by a deep P-polysilicon trench (DPPT) 22, while connecting the p-layers p1-p4 that are usually grounded, and interrupting the source DNPT with a given interval of about 5μm using an opening 30 to contact the p-layers p1-p4 in the other direction. In addition to the separated regions 3 of JFET2 thus formed, the additional DPPT 23 can produce separated n-islands, such as 4 and 5 in the figure.

[0018] A body region 12 of a first conductivity type (eg, p-type material) is arranged within the separated n-type region 4 of the MOS transistor 1 and is arranged at a density of 100 nm per cm. 3 Internal 1*10 17 to 1*10 18 The main region 12 generally extends to a depth of 1 μm or less below the device surface. 3 Internal 1*10 18 to 1*10 20 The source region 13 is a second conductivity type (e.g., n+ type material) doped with N atoms. The source region 13 extends, for example, 0.4 μm or less below the device surface. The body contact region 121 in the first conductivity type body region 12 on the left side of the source region 13 is doped with N atoms per cm. 3 Internal 1*10 18 to 1*10 20 The body contact region 121 extends, for example, 0.4 μm or less below the device surface. By extending the body region 12 and the body contact region 121 beyond the formed recessed region, both the body region 12 and the body contact region 121 can be electrically connected to the substrate.

[0019] The contact area 16 of the drain of the MOS transistor 1 of the second conductivity type (eg, n+ type material) is per cm 3 Internal 1*10 18 to 1*10 20 The drain contact region 16 extends, for example, 0.4 μm or less below the device surface.

[0020] The JFET 2 is arranged in the isolation region 3 with a spacing of 1 cm 3 Internal 1*10 18 to 1*10 20 The source region 18 and the drain region 19 are doped with a second conductivity type (eg, n+ type material) by atoms. The source region 18 and the drain region 19 extend, for example, 0.4 μm or less below the surface of the device.

[0021] The contact region 16 of the drain of the MOS transistor 1 is in electrical contact with the contact region 18 of the source of the JFET 2 , thereby forming the MOS transistor 1 in series with the JFET 2 .

[0022] The breakdown voltage of the device will be determined by the drift region LD between the source region 18 and the drain region 19 of the JFET 2 and the substrate resistivity.

[0023] As examples of logic and analog control functions, several separate areas 5 can be easily made.

[0024] Even if logic and MOS devices can Figure 1 While shown in separate n-layers and implemented as described in the prior application, p-layers are also more preferred for the logic and operation of the MOS device and are an object of the present invention.

[0025] P-type regions can be produced in a similar manner, see Figure 7 After the p-layer p4, a thin epitaxial n-layer n5 is deposited, followed by an epitaxial p-layer p5 which is preferably made thicker, 2.5 μm, and has a masked implanted nx layer 31. As a 0.5 μm thick and 1*10 12 The upper conductive layer, the thickness of the p5 layer under the surface is 2μm and the charge is 2*10 per square centimeter. 12 , then, it is equal to 1*10 16 / cm 3 The p-type regions 4 and 5 will have the same doping concentration and a thickness of 2.5 μm, which is the standard for CMOS at the current state of the art. A 1*10 15 / cm 3 The starting p-type material doping concentration is the older standard for CMOS, where the first p-layer thickness is 1μm and the doping concentration is 2*10 16 , another p-layer is on top with a thickness of 1.5 μm and a doping concentration of 1*10 15 The masked nx layer 31 should then cover the top of the p5 layer.

[0026] The device can preferably be made symmetrical, with a mirror image on the right side of the figure, where 26 indicates the line of symmetry.

[0027] Figure 1 An important requirement for the operation of the device shown is that the pinch-off voltage of either FET in JFET 2 is lower than the breakdown voltage of MOS transistor 1. The pinch-off voltage will appear at the common source 18 of the FETs, which is then connected to the drain 16 of the isolated MOS transistor 1. Figure 1 The figure shows that the first layer n1 on top of the p-type substrate 11 is thicker in order to meet the requirement of high breakdown voltage. For a breakdown voltage of about 800V, the thickness of this layer should be about 6-7μm, and the pinch-off voltage should be 50V or higher. This means that the MOS transistor will withstand 50V with a good margin. In addition, a 50V MOS transistor will take up more space and have lower performance than a 10V MOS device. Therefore, it is first recommended to design the remaining n layers for a pinch-off voltage of 10V, and the first layer to shield the source 18 of the JFET2 through the shielding layer 29, as shown in FIG. Figure 1 shown.

[0028] Then, to solve the problem that the n1 layer does not contribute to the current and resistance, it is now proposed to remove the shielding layer 29 and place a new p-type region pa in the middle of the n1 layer near the source. Thus, two new channels are generated, one on top of pa and the other below pa, both of which will pinch off below 10V. The length of pa is about 3μm, and the charge is about 1*10 per square centimeter. 13 This is Figure 8 These two short channels will slightly increase the resistance of the n1 layer from drain to source (10-15%). In total, adding a fifth conductive layer in parallel to the first four reduces the on-resistance by about 20%. For higher breakdown voltages, which require thicker n1 layers, it is proposed to add another p-type region pb and possibly more regions pc, and so on, until the desired performance is achieved.

[0029] As the drain voltage of the JFET increases (e.g. up to 800V), the pinch-off voltage (or actually the source voltage) of the common JFET should be low and constant. This will not happen because as the drain voltage increases, the source voltage increases. By increasing the doping concentration in the gate layers p1-p5 close to the JFET source 18, a shielding region 17" is formed along the edges of the gate layers p1-p5, thereby forming a conventional FET in series with a superjunction FET, where the gate layer will never be fully depleted. This will allow the source voltage of JFET2 to remain constant as the drain voltage of the JFET increases to 800V. This will further reduce the important Miller capacitance by orders of magnitude. Since the doping concentration in the region shown has been greatly increased, it can be used to greatly reduce the grounding frequency of the gate layer and increase the effective width of the JFET. The amount of charge in the shielding region can be on the order of 2*10 per square centimeter. 13 .

[0030] Gate layers p1-p5 will preferably be grounded via fingers 17' that contact this layer with DPPT layer 22 in the same region where DNPT 21 is interrupted by openings 30 in the mask, creating a region where fingers 17' extend from the gate layer and where contact to the n+ sources 18, 18' is interrupted. It is also possible to connect all gate layers via DPPT fingers extending from DPPT 22 in the region where source DNPT 21 is interrupted to contact each of the p-layers p1-p5, replacing fingers 17'. DPPT fingers can very frequently contact the p-layer every 4-5 μm. The DPPT fingers will also act as side gates for the n-layer, which will then provide the same performance advantages as the shielded region 17" described above.

[0031] The substrate 11 is of the first conductivity type and is typically grounded as a layer of the first conductivity type. When the voltage on the drain (i.e., the n1 layer) increases, this layer will be depleted from the substrate and the first p-layer p1. Therefore, the substrate will act as a second gate for the first layer of the second conductivity type n1.

[0032] Figure 2 A MOS transistor 1 is shown in series with a JFET 2 comprising several conductive layers, parallel JFET channels ( Figure 2 The conductive n-layer in the gate is separated by a patterned common p-layer (gate).

[0033] A first n-type epitaxial layer with a thickness of 2 μm is grown on top of a p-type substrate with a resistivity range of 10 Ωcm to 135 Ωcm. The wafer is removed from the reactor and two conductive layers, n1 and n2, are formed by implanted gate layers p1 and p2.

[0034] The thickness and doping concentration of the layer are determined by the resurf principle, which means that the product of the thickness of the layer and the doping concentration should be approximately 2*10 per square centimeter. 12 charge, which means that the thickness and doping concentration can be changed as long as this condition is met.

[0035] The first channel region n1 in the figure is selected to be 0.5 μm thick and the doping concentration is 4*10 16 / cm 3 , then the above conditions are met.

[0036] Then the thickness and doping concentration of the next layer are selected to be 0.5 μm and the doping concentration is 4*10 16 / cm 3 , and in fact can also be a thickness and doping concentration similar thereto.

[0037] As a practical example, five epitaxial layers N1-N5 are deposited, each of which has two implanted p-layers.

[0038] On the drain side, the channel layer is connected to an n+ drain implant 19 in the surface. On the source side, the channel layer is connected to an n+ source implant 18 in the surface.

[0039] The JFET 2 is isolated by a deep p-type polysilicon trench (DPPT) 22 on the source side of the JFET. The DPPT 22 on the source side has fingers connecting the p-layers p1-p10 at given intervals.

[0040] The upper p10 gate layer 17 will contact the DPPT layer through openings 30 in the mask, creating a region where fingers 17' extend from the gate layer and where the contact to the n+ source 18, 18' is interrupted. The same mask will be used to create and contact all other gate layers. Fingers 17' will ensure contact to all n-layers.

[0041] In or partially within the isolated n-type region, the bulk region of the first conductivity type (eg, p-type material) is 100% by weight per cm 3 Internal 1*10 17 to 1*10 18 The body region 12 typically extends to a depth of 1 μm or less below the device surface.

[0042] In the body region 12 of the MOS transistor 1, the source region 13 of the second conductivity type (eg, n+ type material) is arranged at a thickness of 1 cm 3 Internal 1*10 18 to 1*10 20 The source region 13 extends below the device surface for example 0.4 μm or less. The body contact region 121 in the body region 12 to the left of the source region of the first conductivity type is doped with atoms per cm 3 Internal 1*10 18 to 1*10 20 The body contact region 121 extends, for example, 0.4 μm or less below the device surface. By extending the body region 12 and the body contact region 121 outside the recess region, both the body region 12 and the body contact region 121 can be electrically connected to the substrate.

[0043] The drain contact region 16 of the second conductivity type (eg, n+ type material) is per cm 3 Internal 1*10 18 to 1*10 20 The drain contact region 16 extends below the surface by, for example, 0.4 μm or less.

[0044] The JFET is arranged in separate regions 3 with a spacing of 1 / cm 3 Internal 1*10 18 to 1*10 20 The source region 18 and the drain region 19 are doped with a second conductivity type (eg, n+ type material) by atoms. The source region 18 and the drain region 19 extend, for example, 0.4 μm or less below the surface.

[0045] The contact region 16 of the drain of the MOS transistor 1 is in electrical contact with the contact region 18 of the source of the JFET 2 , thereby forming the MOS transistor 1 in series with the JFET 2 .

[0046] The breakdown voltage of the device will be determined by the drift region LD and the substrate resistivity.

[0047] As previously mentioned, it is beneficial to have the uppermost thicker layer be p-type rather than n-type, which is an object of the present invention.

[0048] Alternatively, the thickness of the epitaxial layer N4 can be reduced from 2 μm to 1.5 μm by removing p8 from the epitaxial layer N4 and depositing a doping concentration of 1*10 16 / cm 3 The 2.5μm thick p-epitaxial layer PX is modified Figure 2 The device shown in the figure is injected with a thickness of 0.5 μm and a charge of 1*10 per square centimeter on the top of the device. 12 The nx layer 31. This Figure 9 The thickness of the p-layer below the surface is now 2 μm, and the charge is 2*10 per square centimeter. 12 , then, corresponding to 1*10 16 / cm 3 The p-type regions 4 and 5 will have the same doping concentration and a thickness of 2.5 μm, which is the standard for CMOS at the current state of the art. 15 / cm 3 The older standard for CMOS starting p-type material doping concentrations is where the first p-layer is 1 μm thick and has a doping concentration of 2*10 16 , another p-layer is on top with a thickness of 1.5 μm and a doping concentration of 1*10 15 The masked nx layer 31 should then cover the top of the p5 layer. A DNPT is also added on the source side.

[0049] As examples of logic and analog control functions, several separate areas 5 can be easily made.

[0050] Figure 2 An important requirement for the operation of the device shown is that the pinch-off voltage of any one of the FETs in JFET 2 is lower than the breakdown voltage of the MOS transistor 1. The pinch-off voltage will appear at the common source 18 of the FETs, which is then connected to the drain 16 of the isolated MOS transistor 1. Figure 1In the same way as shown, the first layer n1 on top of the p-type substrate 11 is thicker. This is to meet the requirement of high breakdown voltage. For a breakdown voltage of about 800V, the thickness of this layer should be about 6-7μm, and the pinch-off voltage is 50V or higher. This means that the MOS transistor will withstand 50V with a good margin. In addition, a 50V MOS transistor will take up more space than a 10V MOS device and have lower performance. Therefore, it is recommended to first design the remaining n layers for a pinch-off voltage of 10V, and the first layer is formed by Figure 2 A shielding layer 29 is shown to shield the source 18 of the JFET 2 .

[0051] Then, in order to solve the problem that 29 and p1 of the first layer do not contribute to the current and resistance, 29 and p1 of the first layer are removed, as shown in FIG. Figure 10 As shown. The thickness below p2 should then be 6 μm. This layer is designated n2. A new p-type region, pa, is placed roughly in the middle of this thickness. Two new channels are then created, one on top of pa and one below pa, both of which pinch off below 10 V. These two short channels will slightly increase the drain-to-source resistance of the n2 layer (10-15%). For higher breakdown voltages, which require thicker n2 layers, it is proposed to add another p-type region, pb, and possibly more regions, pc, and so on, until the desired performance is achieved.

[0052] As the voltage at the drain 19 of the JFET increases (e.g. up to 800V), the pinch-off voltage of the common JFET (or actually the voltage at the source 18) should be low and constant. This will not happen because the source voltage increases as the drain voltage increases. By increasing the doping concentration in the gate layers p1-p10 close to the source 18 of the JFET, a shielding region 17" is formed along the edges of the gate layers p1-p10, thereby forming a conventional FET in series with a superjunction FET, in which the gate layer will never be fully depleted. This will allow the voltage at the source 18 of JFET2 to remain constant as the drain voltage of the JFET increases to 800V. This will further reduce the significant Miller capacitance by orders of magnitude. Since the doping concentration in the region shown has been greatly increased, it can be used to greatly reduce the grounding frequency of the gate layer and increase the effective width of the JFET. The amount of charge in the shielding region can be on the order of 2*10 per square centimeter. 13 .

[0053] Figure 3A MOS transistor 1 is shown in series with a JFET 2 comprising several conductive layers, parallel JFET channels (n layers n1-n5 in the figure, separated by a common p layer p1-p4 (gate)). These layers are deposited in situ in an epitaxial reactor on top of an oxide layer 10 carried by a p-type substrate 11. Before starting to grow the epitaxial layers n1-n5, p1-p4, a thin seed layer is present on top of the oxide layer 10.

[0054] The thickness and doping concentration of the layer are determined by the resurf principle, which means that the product of the thickness of the layer and the doping concentration should be approximately 2*10 per square centimeter. 12 charge, which means that the thickness and doping concentration can be changed as long as this condition is met.

[0055] In the attached figure, these epitaxial layers are formed with equal thickness of 0.5 μm and 4*10 16 / cm 3 Starting from a doping concentration of, and in fact can be a thickness and doping concentration similar thereto.

[0056] As a practical example, the number of epi layers stops before the n5 epi layer, which is made thicker at 4.5 μm and has a px layer 17 as a masked implant for the upper gate, which is 0.5 μm thick and has a charge of 1*10 12 The implanted px layer is only used as a gate of a channel, which makes the channel layer thickness 4μm and the doping concentration 5*10 15 / cm 3 .

[0057] The px gate layer 17 will pass through the finger 17' to Figure 1 The device is contacted with the DPPT 22 in the same manner.

[0058] Channel layers n1-n5 are connected together on the drain side using a deep N-type polysilicon trench (DNPT) 20. The channel layers are also connected together on the source side by a deep N-type polysilicon trench (DNPT) 21. JFET 2 is isolated by a deep p-type polysilicon trench (DPPT) 22, which connects the p-layers p1-p4, which are normally grounded, and interrupts the source DNPT 21 at given intervals to contact the p-layers p1-p4 in the other direction. In addition to the isolated region 3, additional DPPTs 23 and 24 can create isolated n-islands, such as 4 and 5 in the figure.

[0059] In the separated n-type region 4 or partially in the separated n-type region 4, the body region 12 of the first conductivity type (eg, p-type material) is per cm 3 Internal 1*10 17 to 1*10 18The main region 12 generally extends to a depth of 1 μm or less below the device surface. In the main region 12 of the MOS transistor 1, the source region 13 of the second conductivity type (e.g., n+ type material) is doped with 1 μm of N-type material per cm. 3 Internal 1*10 18 to 1*10 20 The source region 13 extends below the device surface, for example, by 0.4 μm or less. The body contact region 121 in the body region 12 is arranged on the left side of the source region 12 of the first conductivity type, and the body contact region 121 is doped with a doping agent per cm 3 Internal 1*10 18 to 1*10 20 The body contact region 121 extends, for example, 0.4 μm or less below the device surface. By extending the body region 12 and the body contact region 121 outside the recess region, both the body region 12 and the body contact region 121 can be electrically connected to the substrate.

[0060] The drain contact region 16 of the second conductivity type (eg, n+ type material) is per cm 3 Internal 1*10 18 to 1*10 20 The drain contact region 16 extends, for example, 0.4 μm or less below the device surface.

[0061] The JFET 2 is arranged in the separated area 3 with a width of 1 cm 3 Internal 1*10 18 to 1*10 20 The source region 18 and the drain region 19 are doped with a second conductivity type (eg, n+ type material) of 100 Å atoms. The source region 18 and the drain region 19 extend, for example, 0.4 μm or less below the surface of the device.

[0062] The contact region 16 of the drain of MOS transistor 1 will be in electrical contact with the contact region 18 of the source of JFET 2, thereby forming MOS transistor 1 in series with JFET 2. The breakdown voltage of the device will be determined by the drift region LD.

[0063] As examples of logic and analog control functions, several separate areas 5 can be easily made.

[0064] In combination Figure 3 In the embodiment shown and described, the epitaxial layer is located on top of the oxide layer 10. This implementation can also be combined with Figure 2 The illustrated and described embodiments are provided together in which a p-layer is implanted into an epitaxial n-layer.

[0065] A high voltage Schottky diode in parallel with the drain and connected to ground can be easily implemented internally.

[0066] Figure 1 The px finger 17' is divided into two parts (see Figure 4 ), creating an n-type surface region 27 in the middle. This contact with the Schottky metal or silicide 28 creates a Schottky diode in parallel with the PN junction. A high-performance diode is essential in many motor applications, where forward-biased diodes generate significant parasitic power when switching back to their normal reverse state. Integrated Schottky diodes solve this problem, eliminating the need for external diodes.

[0067] By utilizing Figure 2 and split the P10 finger into two parts (see Figure 5 ), creating an n-type surface region 27 in the middle to form the corresponding device, and this contact with the Schottky metal or silicide 28 will create a Schottky diode in parallel with the PN junction.

[0068] A lateral LIGBT is a combination of a MOS transistor and a lateral PNP transistor, where the MOS transistor drives the base of the PNP transistor. This device is susceptible to latch-up, which limits its current capability. In conventional devices, the MOS transistor and the lateral PNP transistor are fabricated in the same N-well (N-type region). By separating these devices, a latch-up-free LIGBT with significantly improved current capability can be created. See U.S. Patent No. 8,264,015 B2.

[0069] exist Figure 6 middle, Figure 2 The device in Figure 1 is implemented on SOI, where the drain 19 doping has been changed to p+ and is in contact with the DPPT 20. This forms a lateral PNP transistor, where the emitter is the p+-connected DPPT 20, and the base is the entire conductive n-layer connected to the base contact area. The collector is the entire gate layer connected to the DPPT 20. Because the base is fed by an external MOS transistor, the result is a latch-up-free LIGBT with numerous conductive n-type regions, significantly increasing current capability.

[0070] In all components that can be made symmetrical, there is a mirror image on the right side of the figure, and reference numeral 26 indicates the symmetry line.

[0071] The invention described herein can also be modified so that all n-layers described are replaced with p-layers, and correspondingly, all p-layers including a p-type substrate are replaced with n-layers.

Claims

1. A semiconductor device comprising: Insulated gate field effect transistor, which is connected in series with a high voltage JFET, Among them, the high-voltage JFET includes several parallel conductive layers. It is characterized in that A substrate of the first conductivity type is arranged as a base of the semiconductor device so as to extend below the two transistors, a first layer of a second conductivity type arranged to extend above the substrate, Among them, a plurality of parallel conductive layers with channels are arranged on top of the first layer, and the channels are formed by a plurality of epitaxial layers doped with the second conductivity type, and the epitaxial layers doped with the second conductivity type are flanked by layers of the first conductivity type. wherein the uppermost layer of the device is of a first conductivity type and is substantially thicker than several parallel conductive layers directly below, and has a masked implanted layer of a second conductivity type at the surface of the device, thereby covering the top of the uppermost layer, the masked implanted layer being connected to the contact region of the source and the contact region of the drain of the JFET, The high voltage JFET is separated on the source side of the JFET by a deep polysilicon trench of the first conductivity type, the deep polysilicon trench of the first conductivity type being connected to several parallel conductive layers of the first conductivity type, The insulated gate field effect transistor is separated by deep polysilicon trenches of the first conductivity type on both sides. Another separate region including logic and analog control functions is separated by deep polysilicon trenches of the first conductivity type on either side.

2. The semiconductor device according to claim 1, It is characterized in that The layer of the first conductivity type including the doped gate includes a shielding region on a side close to the JFET source, the shielding region having a higher doping concentration than another portion of the layer including the doped gate.

3. The semiconductor device according to claim 1 , It is characterized in that A first layer of the second conductivity type arranged to extend above the substrate is provided with a shielding layer of the first conductivity type on a side close to the JFET source, thereby blocking any current from the first layer of the second conductivity type from reaching the source via the deep polysilicon trench of the second conductivity type.

4. The semiconductor device according to claim 1 , It is characterized in that The first layer of the second conductivity type arranged to extend above the substrate is provided with at least one p-type region located in the middle of the n1 layer on a side close to the JFET source, thereby generating new channels above and below the at least one p-type region.

5. The semiconductor device according to claim 1, It is characterized in that The opening is arranged in the source connection region so that all gate layers contact the deep polysilicon trench.

6. The semiconductor device according to claim 2, It is characterized in that Fingers of the first conductivity type are arranged to extend through the openings in the source connection region, thereby connecting the shielding region with the deep polysilicon trench.

7. The semiconductor device according to claim 2, It is characterized in that Fingers of the first conductivity type material are arranged to extend through the opening in the source connection region, connecting the deep polysilicon trenches of the first conductivity type with the p-layer at regular intervals proximate the source.

8. The semiconductor device according to claim 1, It is characterized in that The gate doped with the first conductivity type is formed by implanting ions into the epitaxial layer doped with the second conductivity type to produce a conductive layer, and then repeating the same steps after depositing the next epitaxial layer doped with the second conductivity type, and finally depositing the epitaxial layer doped with the first conductivity type.

9. The semiconductor device according to claim 1, It is characterized in that The channel layers are connected together on the drain side of the JFET through a deep n-type polysilicon trench of the second conductivity type, and the channel layers are connected together on the source side of the JFET through a deep n-type polysilicon trench of the second conductivity type.

10. The semiconductor device according to claim 1, It is characterized in that The contact region of the drain of the insulated gate field effect transistor is in electrical contact with the contact region of the source of the junction field effect transistor JFET.

11. The semiconductor device according to claim 1, It is characterized in that An insulated gate field effect transistor is a MOS transistor.

12. The semiconductor device according to claim 1, It is characterized in that An integrated high-speed Schottky diode is connected in parallel between a deep polysilicon trench of the second conductivity type and a deep polysilicon trench of the first conductivity type, and the integrated high-speed Schottky diode is implemented on the source side of the JFET separated from the MOS transistor by contacting the n-channel layer with the Schottky metal.

13. The semiconductor device according to claim 9, It is characterized in that The device is a latch-up free LIGBT where the doping of the drain of the JFET has been changed from the second conductivity type to the first conductivity type, creating a lateral PNP transistor where the base of the PNP is fed by the MOS transistor.

14. The semiconductor device according to claim 1, It is characterized in that The first conductivity type is p-type, and the second conductivity type is n-type.

15. The semiconductor device according to claim 1, It is characterized in that The first conductivity type is n-type, and the second conductivity type is p-type.

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