This includes diodes, particularly those with at least two passivation layers locally stacked to optimize passivation, formed specifically by dielectrics.

Abstract

The diode (100) includes a stack (101) of semiconductor layers and an active region (102) disposed within the stack (101). The stack (101) includes a side surface (103). The diode (100) includes a first passivation layer (107) and a second passivation layer (108), the first passivation layer (107) being in contact with the side surface (103) and the second passivation layer (108) being in contact with the side surface (103). The second passivation layer (108) is partially formed on the first passivation layer (107).

Description

Technical Field

[0001] The technical field of this invention relates to diodes, preferably light-emitting diodes (LEDs), and more specifically to LEDs based on inorganic semiconductors. More specifically, the invention relates to a diode comprising a semiconductor layer stack, the stack including side surfaces and the diode including an active region disposed within the stack. Background Technology

[0002] In the prior art, it is known how to manufacture light-emitting diodes (LEDs) comprising a stack of semiconductor layers. An LED includes an active region located within the stack, in which charge carriers recombine with each other during LED operation. The stack of semiconductor layers is typically passivated on its sides by passivation layers. These sides can be formed by planes parallel to or substantially parallel to the direction of current flow in the stack. Such passivation layers have the advantage of limiting parasitic electrical, optical, or photoelectric effects at the edges of the LED. These limitations are advantageous because they improve the performance of the LED.

[0003] Existing passivation methods for LEDs cannot optimize their efficiency. This is because it has been found that the efficiency of LEDs depends on their size; that is, the efficiency of LEDs decreases monotonically with their size. Summary of the Invention

[0004] The purpose of this invention is to improve the passivation of diodes to enhance their performance.

[0005] Therefore, the present invention relates to a diode, comprising:

[0006] - A stack of semiconductor layers, including side surfaces.

[0007] - Active areas arranged within this stack

[0008] The semiconductor includes a first passivation layer and a second passivation layer, the first passivation layer being in contact with a side surface, and the second passivation layer being in contact with a side surface. The second passivation layer 108 is partially formed on the first passivation layer 107.

[0009] This makes it possible to address the issue of improving diode passivation. Therefore, if the diode is a light-emitting diode (LED), this also allows for a more specific passivation of portions of the LED, thereby improving the diode's efficiency, which is independent of its size. For current-carrying diodes, the improved passivation allows for the limitation of current caused by recombination across the diode.

[0010] A diode may also have one or more of the following characteristics:

[0011] - The stack includes a first type doped semiconductor material layer and a second type doped semiconductor material layer, and the diode is such that: a first passivation layer contacts the first type doped semiconductor material layer at a side surface; a second passivation layer contacts the active region at a side surface; the active region is disposed between the first type doped semiconductor material layer and the second type doped semiconductor material layer, or the active region is disposed at the junction between the first type doped semiconductor material layer and the second type doped semiconductor material layer;

[0012] - The diode includes a third passivation layer, which is in contact with a second type of doped semiconductor material layer at its side surface;

[0013] - The first passivation layer is formed of a first dielectric material, and the second passivation layer is formed of a second dielectric material;

[0014] - The third passivation layer is formed of a third dielectric material;

[0015] - The diode is designed such that the conductivity of the first dielectric material is at least three orders of magnitude lower than that of the first type of doped semiconductor material, and the conductivity of the second dielectric material is at least three orders of magnitude lower than that of the semiconductor material forming the active region.

[0016] - A diode is configured such that the active region includes intrinsic semiconductor material, and the band offset between the valence band of the intrinsic semiconductor material and the valence band of the second dielectric material is strictly greater than 3kT / q, and the band offset between the conduction band of the intrinsic semiconductor material and the conduction band of the second dielectric material is strictly greater than 3kT / q, where k is the Boltzmann constant, T is the ambient temperature in Kelvin, and q is a constant corresponding to the elementary charge in coulombs;

[0017] - The conductivity of the third dielectric material is at least three orders of magnitude lower than that of the second type of doped semiconductor;

[0018] - For a diode to be of type n, the band offset between the conduction band of the first dielectric material and the conduction band of the first type doped semiconductor material is strictly greater than 3kT / q, and for a diode to be of type p, the band offset between the valence band of the third dielectric material and the valence band of the second type doped semiconductor material is strictly greater than 3kT / q.

[0019] Where k is the Boltzmann constant, T is the ambient temperature in Kelvin, and q is a constant corresponding to the elementary charge in coulombs;

[0020] - For a diode to be of type n, the band offset between the conduction band of the third dielectric material and the conduction band of the second type doped semiconductor material must be strictly greater than 3kT / q, and for type p, the band offset between the valence band of the first dielectric material and the valence band of the first type doped semiconductor material must be strictly greater than 3kT / q.

[0021] Where k is the Boltzmann constant, T is the ambient temperature in Kelvin, and q is a constant corresponding to the elementary charge in coulombs.

[0022] The present invention also relates to a method for manufacturing the diode as described above, the method comprising:

[0023] - The step of forming a stack of semiconductor layers, a portion of which is used to form the active region of a diode.

[0024] - The step of forming and passivating the side surface of the stack of semiconductor layers, the step of forming and passivating the side surface includes forming a first passivation layer and forming a second passivation layer, the first passivation layer and the second passivation layer being in contact with the side surface, the second passivation layer being partially formed on the first passivation layer.

[0025] The manufacturing method may include one or more of the following features:

[0026] - The steps of forming and passivating the side surface sequentially include: a first etching step of etching the stack to form a first portion of the side surface; a step of depositing a first dielectric material to form a first passivation layer, the first passivation layer covering the first portion of the side surface; a second etching step of etching the deposited first dielectric material and the stack to form a second portion of the side surface; and a step of depositing a second dielectric material to form a second passivation layer, the second passivation layer covering the second portion of the side surface and in contact with the first passivation layer;

[0027] -The first part and the second part are preferably formed of different materials;

[0028] - The manufacturing method includes: a first processing step applied to a first portion of a side surface before performing a step of depositing a first dielectric material, and a second processing step applied to a second portion of a side surface before performing a step of depositing a second dielectric material;

[0029] The first and second processing steps are different;

[0030] - The first processing step includes cleaning the first part and / or etching the surface of the first part and / or transferring elements onto the first part;

[0031] - The second processing step includes cleaning the second part and / or etching the surface of the second part and / or transferring elements onto the second part;

[0032] - The steps of forming and passivating the side surface include: a third etching step of etching the deposited second dielectric material and the stack to form a third portion of the side surface; and a step of depositing a third dielectric material to form a third passivation layer, the third passivation layer covering the third portion of the side surface and contacting the second passivation layer.

[0033] -The third part is preferably formed of a material different from the material forming the second part;

[0034] -The manufacturing method includes a third processing step of treating a third portion of the side surface prior to performing the step of depositing a third dielectric material;

[0035] - The third processing step includes cleaning the third part and / or etching the surface of the third part and / or transferring elements onto the third part;

[0036] -The manufacturing method is to form a stack of semiconductor layers by the following steps: the stack includes a first type doped semiconductor material layer and a second type doped semiconductor material layer, a first portion of the side surface is defined by a portion of the first type doped semiconductor material layer, and a second portion of the side surface is defined by a portion of the active region;

[0037] - The active region is disposed between the first type of doped semiconductor material layer and the second type of doped semiconductor material layer, or the active region is disposed at the junction between the first type of doped semiconductor material layer and the second type of doped semiconductor material layer;

[0038] - The third part of the side surface is defined by a portion of a second type of doped semiconductor material layer.

[0039] Other features and advantages will be more readily apparent from the following detailed description. Attached Figure Description

[0040] The invention will be more readily understood by reading the following detailed description, which is provided by way of non-limiting example only, and with reference to the accompanying drawings listed below.

[0041] Figure 1 A diode according to a specific embodiment of the invention is schematically shown in cross-section, wherein the diode is preferably a light-emitting diode.

[0042] Figure 2 A variant of a diode according to a specific embodiment of the invention is shown schematically in cross-section, wherein the diode is preferably a light-emitting diode.

[0043] Figure 3 The cross-sectional view shows the process of manufacturing. Figure 1 The formation of diode stacks.

[0044] Figure 4 Shown in cross-sectional view Figure 3 The cross section at the end of the etch stacking step.

[0045] Figure 5 Shown in cross-sectional view Figure 4 The cross section at the end of the step of depositing the first dielectric material.

[0046] Figure 6 Shown in cross-sectional view Figure 5 The cross-section at the end of another step of the etching stack.

[0047] Figure 7 Shown in cross-sectional view Figure 6 The cross section at the end of the step of depositing the second dielectric material.

[0048] Figure 8 Shown in cross-sectional view Figure 7 The cross-section at the end of another step of the etching stack.

[0049] Figure 9 Shown in cross-sectional view Figure 8 The cross section at the end of the step of depositing the third dielectric material.

[0050] Figure 10 The application is shown in a cross-sectional view. Figure 9 The cross-section of the etching step is used to form an opening, particularly in the third dielectric material.

[0051] Figure 11 A series of steps of a manufacturing method according to a specific embodiment of the present invention are shown.

[0052] In these figures, the same reference numerals are used to denote the same elements. Detailed Implementation

[0053] "Basically parallel" means parallel within ±30 degrees.

[0054] "Between two values" means that the boundary defined by these two values ​​is contained within the range of the related values.

[0055] "Different materials" refers to materials with different compositions, although they may contain one or more common elements.

[0056] "Based on" refers to a material-based device (e.g., a diode) where the material constitutes the largest portion of the device's composition.

[0057] This invention relates to a diode 100, a specific embodiment of which is described below. Figure 1 and 2As shown in the figure. Diode 100 includes a stack 101 of semiconductor layers. Diode 100 includes an active region 102 disposed within the stack 101; that is, the active region 102 forms part of the stack 101. The stack 101 of semiconductor layers includes a side surface 103.

[0058] "Active region 102 arranged within stack 101" means that stack 101 can define the active region 102, and its edge can define the corresponding part of side surface 103.

[0059] In the field of diode technology, the active region 102 is also referred to as the active area. The active region 102 is optically active in the sense that it can be used, for example, to absorb or emit photons. Specifically, the active region 102 is formed of a corresponding semiconductor material.

[0060] Therefore, the active region 102 can be configured to allow recombination of charge carriers, thereby causing the diode 100 to emit electromagnetic radiation, such as photons.

[0061] Alternatively, the active region 102 can be configured to absorb photons via, for example, the photovoltaic effect, thereby causing charge carriers to be generated by the diode 100, which are then collectable. This causes the diode 100 to generate electricity.

[0062] Each charge carrier mentioned in this specification may be a first charge carrier or a second charge carrier. A first charge carrier is different from a second charge carrier. For example, a first charge carrier may be a hole or an electron, while a second charge carrier may be a hole or an electron.

[0063] Therefore, as can be seen from the above description, diode 100 is an optoelectronic device. Diode 100 can be a light-emitting diode, a photodiode, a photodetector, a photovoltaic cell, or a laser diode.

[0064] Despite Figure 1 The active region 102 is schematically represented by a single block, but the active region 102 can be:

[0065] - Formed from an intrinsic semiconductor layer, then formed Figure 1 The block is represented as active region 102; for example, if diode 100 is a multi-quantum-well type, these intrinsic semiconductor layers are formed by multiple quantum wells, and when diode 100 is a light-emitting diode, charge carriers in these intrinsic semiconductor layers can recombine, or if the diode is a photodiode or photodetector, photons can be absorbed to generate electrons and holes.

[0066] - Formed by the space charge region in the pn junction, Figure 2The area is surrounded by dashed lines, provided that the diode 100 comprises a pn junction formed by two semiconductor material layers 109 and 110 stacked 101, for example, doped p-type and doped n-type layers respectively.

[0067] - Formed from an intrinsic semiconductor layer, and then formed in a pin junction. Figure 1 The active region 102 is provided that the diode 100 includes the pin junction.

[0068] In this specification, the intrinsic semiconductor layer is an intrinsic semiconductor material layer.

[0069] The semiconductor layer stack 101 is preferably defined according to the stacking axis A1 of the semiconductor layers of the stack 101. Figure 1 and Figure 2 The axis A1 is represented by a dashed line. This axis is also called the "stack direction" when oriented. The stack axis A1 is parallel or substantially parallel to the direction in which the thickness of each semiconductor layer in the stack of semiconductor layers 101 is measured.

[0070] Specifically, the semiconductor layer stack 101 may relate to two opposing surfaces 104, 105 about the stack axis A1. A side surface 103 is preferably formed to extend between these two opposing surfaces 104, 105 and, for example, connects these two opposing surfaces 104, 105. For example, in Figure 1 and 2 In the stack of semiconductor layers 101, one side 105 is in contact with the substrate 112, and another side 104 of the stack of semiconductor layers 101 is in contact with an electrode, such as an anode 113.

[0071] Therefore, the side surface 103 is preferably partially defined by a set of points, for which the normal of the side surface 103 is orthogonal to the stacking axis A1 at each of the points in the set of points.

[0072] The side surface 103 may include multiple faces, each of which forms one side of the stack 101 of semiconductor layers.

[0073] Generally, diode 100 includes a first passivation layer 107 and a second passivation layer 108. The first passivation layer 107 is in contact with the side surface 103. The second passivation layer 108 is in contact with the side surface 103. In other words, diode 100 includes a passivation structure 106, which includes the first passivation layer 107 and the second passivation layer 108.

[0074] In other words, the side surface 103 may include a first portion 103a and a second portion 103b. The first passivation layer 107 contacts the first portion 103a of the side surface 103, and the second passivation layer 108 contacts the second portion 103b of the side surface 103.

[0075] The second passivation layer 108 is partially formed on the first passivation layer 107. Therefore, another portion of the second passivation layer 108 provides contact between the second passivation layer 108 and the side surface 103. This allows for a partial overlap of the first passivation layer 107 and the second passivation layer 108, which advantageously allows the first and second portions 103a, 103b of the side surface 103 to contact the first passivation layer 107 and the second passivation layer 108 at the same time, respectively. This also allows the first and second portions 103a, 103b to preferably be surface-treated differently, thereby providing each of these first and second portions 103a, 103b with passivation optimized for the corresponding first or second portion 103a, 103b.

[0076] In other words, the first passivation layer 107 is disposed between the portion of the stack 101 and the portion of the second passivation layer 108 formed on the first passivation layer 107.

[0077] Preferably, a first passivation layer 107 surrounds a portion of the stack 101 of semiconductor layers about a stacking axis A1, and a second passivation layer 108 surrounds a portion of the stack 101 of semiconductor layers about a stacking axis A1. This has the advantage of providing passivation around the stack 101 of the diode 100.

[0078] Preferably, the first passivation layer 107 also contacts the active region 102 to ensure that a portion of the stack 101 located in the extension of the active region 102 is sufficiently passivated by the passivation layer 107.

[0079] Because of the presence of this passivation structure 106 having at least two passivation layers formed by first and second passivation layers 107, 108, the passivation of the diode 100 can be optimized, and therefore, if the diode 100 is a light-emitting diode, the efficiency of the diode 100, independent of its size, tends to be achieved by more specifically passivating portions of the diode 100. Furthermore, and preferably, the presence of these first and second passivation layers 107, 108 can, particularly during the manufacturing of the diode 100, allow the diode 100 to be passivated differently by specific treatment of portions of the side surface 103, as described in more detail below.

[0080] Furthermore, when the materials of these first and second passivation layers 107, 108 are different, for example by using aluminum oxide (such as Al2O3) and silicon oxide (such as SiO2) as different materials, the first and second passivation layers 107, 108 can passivate the side surface 103 of the stack 101 differently.

[0081] The materials of the first and second passivation layers can be the same, especially if the first and second portions 103a, 103b of the side surface 103 are specifically treated during the manufacture of the diode 100.

[0082] Therefore, compared to a light-emitting diode having a single passivated side surface made of the same material, it is proposed here to use at least two passivation layers, each applicable to a specific portion of the side surface 103, thus providing the advantage of allowing for passivation adjustments and custom designs for that specific portion. Thus, the use of these first and second passivation layers 107, 108 advantageously addresses the problem of improving the operation of the diode 100, for example by limiting the trapping of charge carriers at the interface between the side surface 103 and the first and second passivation layers 107, 108, and / or by limiting the reduction in charge carrier mobility at the interface between the side surface 103 and the first and second passivation layers 107, 108.

[0083] In this specification, passivation refers to the engineering design of surface and / or interface defects with the aim of producing passivated surfaces and / or interfaces related to:

[0084] - Intentional external behaviors, such as doping amorphous silicon after passivating defects with hydrogen, thereby filling dangling bonds.

[0085] - Unconscious external effects, such as adsorption or oxidation.

[0086] The purpose of passivation is to control the position of the Fermi level at the passivated surface and / or passivated interface. More specifically, with respect to diode 100, passivation provides partial or complete suppression of electronic surface or interface states, thus tending to limit all parasitic electrical, optical, or photoelectric effects at the edge of diode 100, that is, at the interface between the side surface 103 formed by the semiconductor material stacked 101 and the external environment of diode 100. The aim is to tend to eliminate electrical and / or optical characteristics that limit the performance of diode 100, which depend on the interface states of diode 100. Therefore, the passivation according to this specification is so-called "electro-optic" passivation.

[0087] In this specification, "interface" refers to the transition region between two adjacent material volumes, forming abrupt planes that mark the discontinuity of the properties of the two adjacent materials, but is equivalent to a junction region with a typically very small thickness, such as the thickness of an atomic layer.

[0088] At the interface between side surface 103 and the passivation layer, defects, i.e., imperfections larger than dangling bonds, may occur. These imperfections may include impurities, gaps, antisites, compositional disturbances, surface adsorption, or specific bond angles.

[0089] Therefore, passivation is selected in a way that confines defects within diode 100, which may interact with charge carriers through trapping and / or diffusion mechanisms.

[0090] When diode 100 is unbalanced, that is, particularly when a voltage is applied to the terminals of diode 100, a trapping mechanism, also known as a localization mechanism, occurs. The charge carrier states trapped by the interface states are no longer available for the desired effect (e.g., emitting photons or collecting these charge carriers to generate electricity). This unavailability is temporary if the charge carriers are released after a period of time, or final if the charge carriers nonradiatively recombine with charge carriers of opposite sign. The intensity of the phenomenon caused by this trapping mechanism is a function of the interface state density and also of the exchange dynamics (surface recombination rate) of the charge carriers with the allowed bands of the semiconductor where the trapping occurs.

[0091] The diffusion mechanism corresponds to the decrease in the mobility of free charge carriers at the interface between the side surface 103 and the passivation structure 106. This is due to the fluctuation of the surface potential at the side surface 103 caused by the roughness and interface charge at the side surface 103 and the existence of charge carrier diffusion.

[0092] In the context of diode 100, the surface passivated by passivation structure 106 is side surface 103, because charge carriers preferably travel at least in active region 102, mainly parallel or substantially parallel to the stacking axis A1 of stack 101.

[0093] In summary, if diode 100 is a light-emitting diode, then side surface 103 can be a surface on which parasitic mechanisms and electroluminescence operate in parallel.

[0094] According to a specific embodiment, the stack 101 of semiconductor layers may include a first-type doped semiconductor material layer 109 and a second-type doped semiconductor material layer 110. A first passivation layer 107 contacts the first-type doped semiconductor material layer 109 at a side surface 103. A second passivation layer 108 contacts the active region 102 at the side surface 103. In other words, a first portion 103a of the side surface 103 is part of the first-type doped semiconductor material layer 109, and a second portion 103b of the side surface 103 is part of the active region 102. Therefore, the first passivation layer 107 can passivate a portion of the first-type doped semiconductor material layer 109, and the second passivation layer 108 can passivate a portion of the active region 102. This specific embodiment can provide passivation suitable for contact with the active region 102, wherein the purpose is to limit the trapping of charge carriers and provide passivation suitable for contact with the first-type doped semiconductor material layer 109. Passivation of the active region 102 at the side surface 103 is therefore preferably considered a priority because it is the most sensitive. The passivation of the active region 102 can also limit undesirable radiative recombination when necessary because of their small gaps; these undesirable radiative recombinations are also known as SRH (Shockley-Read-Hall) surface recombinations. On the other hand, this also preferably allows the first and second passivation layers 107, 108 to be deposited sequentially during manufacturing, so that the first and second portions 103a, 103b undergo different surface treatments. Typically, after their treatment, the first portion 103a is protected by the first passivation layer 107 during the surface treatment of the second portion 103b.

[0095] Therefore, taking into account the specific characteristics of each of the first type doped semiconductor material layer 109 and the active region 102, and in particular, the compositional differences or defects to be eliminated between the material of the first type doped semiconductor material layer 109 and the material of the active region 102, if appropriate, the passivation structure 106 can make it possible to passivate the material of the active region 102 on the second portion 103b and the material of the first type doped semiconductor material layer 109 on the first portion 103a in different ways.

[0096] The active region 102 may be disposed between the first type doped semiconductor material layer 109 and the second type doped semiconductor material layer 110. This may be the case if the active region 102 is formed by one or more layers, especially intrinsic semiconductor layers.

[0097] Alternatively, the active region 102 is disposed at the junction between the first type-doped semiconductor material layer 109 and the second type-doped semiconductor material layer 110. This may be the case if the junction of the first type-doped semiconductor material layer 109 and the second type-doped semiconductor material layer 110 makes it possible to form the active region 102, which corresponds to the space charge region of the junction, particularly forming a pn junction.

[0098] Type I doping is the opposite of Type II doping. Type I doping can be p-type doping (also called p-doping), in which case Type II doping is n-type doping (also called n-doping), and vice versa.

[0099] As can be clearly seen from the above description, the aim is to limit the trapping of charge carriers in the active region 102 and the SRH recombination in the active region 102, so as to provide the maximum expected recombination of charge carriers if the diode 100 emits electromagnetic radiation, or to maximize the collection of charge carriers generated in the active region 102 if the diode 100 generates electricity. Furthermore, during operation of the diode 100, the second charge carriers can be represented in a majority form relative to the first charge carriers. Therefore, preferably, the first type makes the first type doped semiconductor material layer 109 suitable (i.e., configured for) the migration of the first charge carriers; the second type makes the second type doped semiconductor material layer 110 suitable (i.e., configured for) the migration of the second charge carriers; during operation of the diode 100, particularly in the case of a GaN-based light-emitting diode, the first charge carriers in the active region 102 are fewer than the second charge carriers present in the active region 102. As a result, in this case, in addition to the passivation of the active region 102, the passivation of the first type of doped semiconductor material layer 109 takes precedence over the passivation of the second type of doped material layer 110, and such that if the diode emits photons, the loss of the first charge carriers available for recombination with the second charge carriers in the active region can be limited. Clearly, if the number of the first and second charge carriers is balanced within the diode 100, particularly in the active region 102, then the passivation of the first type of doped semiconductor material layer 109 does not take precedence over the passivation of the second type of doped material layer 110.

[0100] The above description describes the use of different layers to passivate the stack 101 at the first type-doped semiconductor material layer 109 and the active region 102. To further improve the passivation of the stack 101, the diode 100 may include a third passivation layer 111, such as... Figure 1 and 2As shown. The third passivation layer 111 contacts the second type-doped semiconductor material layer 110 at the side surface 103. In other words, the passivation structure 106 may include this third passivation layer 111. Therefore, the side surface 103 may include a third portion 103c corresponding to a portion of the second type-doped semiconductor material layer 110. Thus, the third passivation layer 111 can passivate a portion of the second type-doped semiconductor material layer 110. This allows the passivation of the stack 101 to be locally adapted to a specific material, such as the second type-doped semiconductor material of the second type-doped semiconductor material layer 110. As described below, this adaptation of passivation can be provided by using a specific treatment of the third portion 103c. The second type-doped semiconductor material is significantly different from the first type-doped semiconductor material and may be at least partially different from the material of the active region 102.

[0101] The third passivation layer 111 is preferably partially formed on the second passivation layer 108. Therefore, another portion of the third passivation layer 111 provides contact between the third passivation layer 111 and the side surface 103.

[0102] Preferably, the third passivation layer 111 surrounds a portion of the semiconductor layer stack 101 around the stack axis A1 to function as passivation around the stack 101.

[0103] For example, the first to third passivation layers 107, 108, and 111 are arranged to contact and partially overlap the first, second, and third portions 103a, 103b, and 103c of the side surface 103, respectively. For example, in Figure 1 and Figure 2 middle:

[0104] -At the horizontal position where the first passivation layer 107 contacts the first portion 103a of the side surface 103, the first to third passivation layers 107, 108, and 111 are stacked sequentially.

[0105] - At the level where the second passivation layer 108 contacts the second portion 103b of the side surface 103, the second and third passivation layers 108 and 111 are stacked.

[0106] As can be seen from the above description, the number of passivation layers is not limited to two or three. This is because the passivation structure 106 can include more than three passivation layers, each in contact with a specific material to be passivated on a corresponding portion of the side surface 103 of the stack 101 forming the semiconductor layer. This makes it possible, for example, to process more than three portions of the side surface of the diode 100 in different ways. In other words, each passivation layer can be designed to allow a specific passivation method to be used on the corresponding material-bound portion of the side surface 103 of the stack 101.

[0107] In fact, the passivation structure 106 can be used to confine trapping at all interfaces between the layers of the stack 101 and the passivation layer, and to limit unwanted radiative recombination when necessary, because they have small gaps (SRH recombination).

[0108] Preferably, each passivation layer is an electrically insulating material layer, also known as a dielectric material, whose conductivity is at least three orders of magnitude lower than that of the material to be passivated in stack 101. One order of magnitude corresponds to 1. This makes it possible to prevent current leakage through the passivation layer.

[0109] Therefore, the first passivation layer 107 can be formed of a first dielectric material, the second passivation layer 108 can be formed of a second dielectric material, and if a third passivation layer 111 exists, the third passivation layer 111 can be formed of a third dielectric material.

[0110] The first, second, and third dielectric materials can be the same, especially if the first, second, and third portions 103a, 103b, and 103c of the side surface 103 are specifically treated during the manufacture of the diode 100.

[0111] The first and second passivation layers 107 and 108, and the third passivation layer 111, if necessary, can each be a multilayer structure.

[0112] In addition, to prevent current leakage:

[0113] The conductivity of the first dielectric material can be at least three orders of magnitude lower than that of the first type of doped semiconductor material.

[0114] - The conductivity of the second dielectric material can be at least three orders of magnitude lower than that of the semiconductor material forming the active region 102.

[0115] -If necessary, if a third passivation layer 111 is present, the conductivity of the third dielectric material may be at least three orders of magnitude lower than that of the second type of doped semiconductor material.

[0116] Furthermore, the active region 102 may include or be formed of an intrinsic semiconductor material. In this case, the band offset between the valence band of the intrinsic semiconductor material and the valence band of the second dielectric material can be strictly greater than 3 kT / q, and the band offset between the conduction band of the intrinsic semiconductor material and the conduction band of the second dielectric material can be strictly greater than 3 kT / q. This prevents the trapping of charge carriers in the second dielectric material and, if necessary, prevents surface conduction of the second dielectric material.

[0117] If the first type is n-type, the band offset between the conduction band of the first dielectric material and the conduction band of the first type doped semiconductor material can be strictly greater than 3kT / q. This prevents electrons from being trapped in the first dielectric material and ensures that the surface conduction channels of the first dielectric material are not supplied with electron-type charge carriers.

[0118] If the second type is n-type, the band offset between the conduction band of the third dielectric material and the conduction band of the second type doped semiconductor material can be strictly greater than 3kT / q. This prevents electrons from being trapped in the third dielectric material and ensures that the surface conduction channels of the third dielectric material are not supplied with electron-type charge carriers.

[0119] If the second type is p-type, the band offset between the valence band of the third dielectric material and the valence band of the second-type doped semiconductor material can be strictly greater than 3kT / q. This prevents holes from being trapped in the third dielectric material and ensures that the surface conduction channels of the third dielectric material are not supplied with hole-type charge carriers.

[0120] If the first type is p-type, the band offset between the valence band of the first dielectric material and the valence band of the first type doped semiconductor material can be strictly greater than 3kT / q. This prevents holes from being trapped in the first dielectric material and ensures that the surface conduction channels of the first dielectric material are not supplied with hole-type charge carriers.

[0121] In "3kT / q", it is also expressed as "3×k×T / q", where k is the Boltzmann constant, T is the ambient temperature in Kelvin, and q is a constant corresponding to the elementary charge in coulombs. The ambient temperature T can be from 300K to 500K.

[0122] In this descriptive sense, "offset" refers to a difference. Depending on the context, band offset can specifically refer to the energy difference between the conduction bands of two materials or the energy difference between the valence bands of two materials.

[0123] This document describes a specific example of a diode 100 forming a gallium nitride (GaN)-based light-emitting diode. According to this specific example, a stack 101 of semiconductor layers may sequentially include, preferably, a substrate 112 (e.g., a sapphire or silicon substrate) disposed thereon:

[0124] - An n-type doped gallium nitride layer is formed in the second type of doped semiconductor material layer 110 for electron transport.

[0125] - One or more alternating layers to form the active region 102, each alternating layer comprising an undoped indium gallium nitride (InGaN) layer and a gallium nitride (GaN) layer, wherein the indium ratio is modulated as a function of the desired emission wavelength of the light-emitting diode.

[0126] - A p-type doped gallium nitride layer is formed as a first-type doped semiconductor material layer 109. The top of the stack 101 is preferably in contact with the anode 113 compared to the substrate 112. The n-type doped gallium nitride layer is preferably in contact with an electrode, which, in a particular example, is formed by a cathode 117.

[0127] Based on this specific example:

[0128] Then, the first portion 103a is formed by p-type doped gallium nitride (the p-type dopant can be magnesium), and the first dielectric material forming the first passivation layer 107 can be aluminum oxide, such as Al2O3, or silicon oxide, such as SiO2.

[0129] Then, the second portion 103b is formed by alternating layers of the active region 102, and the second dielectric material forming the second passivation layer 108 can be aluminum oxide, such as Al2O3.

[0130] -Then the third part 103c is formed by n-type doped gallium nitride (the n-type dopant can be silicon), and the third dielectric material forming the third passivation layer 111 can be aluminum oxide, such as Al2O3, or silicon oxide, such as SiO2.

[0131] According to this particular example, diode 100 may also include:

[0132] Between the second-type doped semiconductor material layer 110 and the active region 102, one or more layers of undoped gallium nitride (not shown) are used to prevent the diffusion of n-type dopants in the active region 102. This or these undoped gallium nitride layers then become barrier layers for dopant diffusion.

[0133] Between the active region 102 and the first type of doped semiconductor material layer 109, one or more layers of undoped gallium nitride (not shown) are used to prevent the diffusion of p-type dopants in the active region 102. This or these undoped gallium nitride layers then become barrier layers for dopant diffusion.

[0134] - If necessary, an aluminum gallium nitride (AGaN) layer is formed between the active region 102 and the first type of doped semiconductor material layer 109 to form an electron blocking layer, the proportion of aluminum in the electron blocking layer being adapted according to the required blocking height; if the active region 102 is an alternation of undoped InGaN / GaN layers, the AGaN layer can be in contact with the active region 102, or if the active region 102 is formed only by an InGaN layer, the AGaN layer can be spaced apart from the active region 102, for example, to form a pin junction.

[0135] According to this specific example, holes are the least present in the active region 102. This is because holes are less mobile than electrons, and the ionization energy of p-type dopants is greater (therefore, the hole density in the active region 102 is low, and the injection barrier is high).

[0136] For this particular example, the differences in the function and properties (i.e., the differences in composition) of the layers of stack 101 highlight the fact that it is difficult to define a single passivation method that is perfectly applicable to all layers of stack 101 forming the light-emitting diode 100. The presence of a passivation structure 106 with at least two passivation layers allows for optimal adaptation to the properties and functions of the layers of stack 101 of the light-emitting diode 100.

[0137] The present invention also relates to a method for manufacturing a diode 100, embodiments of which are described in... Figure 1 and Figures 3 to 10 As shown in the figure. Therefore, all the contents applicable to the diode 100 described above can also be applied to the method of manufacturing the diode 100, and all the contents applicable to the method of manufacturing the diode 100 can also be applied to the diode 100 that can be manufactured by the method described above. Figure 11 An example of the sequence of steps in the manufacturing method is also illustrated.

[0138] The manufacturing method includes step E1, which forms a stack 101 of semiconductor layers, a portion of which is intended to form the active region 102 of a diode 100. Figure 3 In fact, during the manufacturing process, the resulting stack 101 is modified so that the final product is a diode 100 comprising the modified stack 101. The stack 101 is shown between the two dashed lines.

[0139] The manufacturing method includes step E2, which involves forming and passivating the side surfaces 103 of a stack 101 of semiconductor layers. Specific examples of its embodiments are described in... Figures 4 to 9 As shown in the image.

[0140] To facilitate the production of diode 100, prior to forming and passivating side surface 103 (step E2), a material layer 114 for forming the electrodes (e.g., anode 113) of diode 100 can be formed on top of stack 101, for example, on the opposite end of substrate 112 where the substrate of stack 101 is located. A hard mask 115 can then be formed on the material layer 114 for forming the electrodes. A photolithography step can then define a mask called an "etch mask 116" within the hard mask 115, which can be used to etch stack 101 in a direction parallel to the stack axis A1, for example, anisotropic etching. Figures 4 to 8 ).

[0141] The step E2 of forming and passivating the side surface 103 includes the formation of the first passivation layer 107 (E2-1) and the formation of the second passivation layer 108 (E2-2). Figures 4 to 7 The first and second passivation layers 107 and 108 are in contact with the side surface 103, and the second passivation layer 108 is partially formed on the first passivation layer 107. The second passivation layer 108 is then formed after the first passivation layer 107. Therefore, step E2 enables the formation of a passivation structure 106 comprising these first and second passivation layers 107 and 108. As described above, forming two passivation layers for passivating the side surface 103 allows for localized improvement of passivation; preferably, different materials are permitted to form the side surface 103 during passivation.

[0142] Since the first and second passivation layers 107 and 108 are required to facilitate the passivation of the side surface 103, it is necessary to find a technical solution to form these layers at the edge of the stack 101 of the diode 100. For this purpose, step E2 of forming and passivating the side surface 103 may sequentially include:

[0143] -First etching step E2-1-1( Figure 4 and 11 The etching process involves preferably anisotropic etching on the stack 101 to form a first portion 103a of the side surface 103; the first etching step E2-1-1 can partially define the periphery of the active region 102, and, if necessary, can define an electrode such as the aforementioned anode 113.

[0144] -deposition( Figure 5 In step E2-1-2, the first dielectric material is used to form the first passivation layer 107, which covers and thus contacts the first portion 103a of the side surface 103.

[0145] -Second etching step E2-2-1( Figure 6The etching process, preferably anisotropic, is performed on the deposited first dielectric material and stack 101 to form a second portion 103b of the side surface 103, and preferably, to define a portion of the periphery of the active region 102 at the side surface 103, particularly the remaining periphery.

[0146] - Step E2-2-2: Depositing a second dielectric material to form a second passivation layer 108, the second passivation layer 108 covers and thus contacts the second portion 103b of the contact side surface 103, and the second passivation layer 108 contacts the first passivation layer 107. Figure 7 ).

[0147] The first and second portions 103a and 103b of the side surface 103 can be formed of different materials. For example, if the active region 102 is formed of one or more layers of, for example, intrinsic semiconductor, the materials of the first and second portions 103a and 103b are different. For example, if the active region 102 is formed at the junction between a first type doped semiconductor material layer 109 and a second type doped semiconductor material layer 110, the second portion 103b can be formed of a portion of the first type doped semiconductor material layer 109 and / or a portion of the second type doped semiconductor material layer 110, which allows portions of the side surface 103 to be passivated according to their function. This series of steps facilitates the formation of the side surface 103 in contact with the two passivation layers using simple microelectronic techniques, such as etching, for example, by means of an etching mask 116 and deposition of the first and second dielectric materials by conformal deposition. Firstly, this allows different surface treatments to be provided for the first portion 103a and the second portion 103b, regardless of whether the first portion 103a and the second portion 103b are made of the same or different or partially different materials.

[0148] The formation of the first and second passivation layers 107 and 108 in the manner described above has a further advantage: the first portion 103a is formed and then passivated by the first passivation layer 107 before the second portion 103b is formed and then passivated by the second passivation layer 108. Therefore, in the manufacturing method, this allows the first and second portions 103a and 103b of the side surfaces 103 to be treated independently and specifically, also known as surface treatments, to improve their passivation and thus ultimately improve the overall passivation of the stack 101 of the diode 100. These treatments allow for the complete or partial elimination of the aforementioned defects within the diode 100, which may interact with charge carriers through trapping and / or diffusion mechanisms. Therefore, preferably, the manufacturing method includes a first treatment step E2-1-3 applied to the first portion 103a of the side surface 103 before performing step E2-1-2 of depositing the first dielectric material, and a second treatment step E2-2-3 applied to the second portion 103b of the side surface 103 before performing step E2-2-2 of depositing the second dielectric material. The first processing step E2-1-3 and the second processing step E2-2-3 are different so as to process the first and second portions 103a and 103b of the side surface 103 in different ways, for example, by using different materials. Therefore, for example, the first and second portions 103a and 103b can be processed in different ways by taking into account the semiconductor material forming the first portion 103a and the semiconductor material forming the second portion 103b. In particular, the second processing step E2-2-3 has the advantage of being performed when the first portion 103a is covered by the first passivation layer 107.

[0149] Therefore, step E2, which forms and passivates the side surface 103 before forming the first passivation layer 107, may include a first processing step E2-1-3 for preparing a first portion 103a of the side surface 103 to receive the first passivation layer 107. Step E2, which forms and passivates the side surface 103 before forming the second passivation layer 108, may include a second processing step E2-2-3 for preparing a second portion 103b of the side surface 103 to receive the second passivation layer 108. This second processing step E2-2-3 is performed after the formation of the first passivation layer 107, and the first processing step E2-1-3 is different from the second processing step E2-2-3.

[0150] Preferably, in order to form the third passivation layer 111 belonging to the passivation structure 106 in E2-3, Figure 9 and Figure 11 Step E2, which forms and passivates the side surface 103, includes a third etching step E2-3-1, in which the deposited second dielectric material and the stack 101 are etched to form a third portion 103c of the side surface 103 (from...). Figures 7 to 8Step E2, which forms and passivates side surface 103, further includes step E2-3-2, which deposits a third dielectric material to form a third passivation layer 111. Figure 9 The third passivation layer 111 covers and thus contacts the third portion 103c of the side surface 103. The third passivation layer 111 also contacts the second passivation layer 108. The third portion 103c can be formed of a different material than the material forming the second portion 103b. In the case of bonding between the first type doped semiconductor material layer 109 and the second type doped semiconductor material layer 110, the third portion 103c can be formed of the same material as the second portion 103b or of a material that is the same as a portion of the second portion 103b, thereby enabling portions of the side surface 103 to be passivated according to their function. The third portion 103c is in particular formed of a different material than the material forming the first portion 103a. These steps have the advantage of allowing the third portion 103c of the side surface 103 to be passivated in a suitable manner. If desired, this also has the advantage that the specific treatment of the second portion 103b (via the second treatment step E2-2-3) is performed without affecting the third portion 103c formed after that specific treatment.

[0151] Furthermore, the formation of the third portion 103c of the side surface 103 as described above allows for a third processing step E2-3-3 of applying the third portion 103c to the side surface 103 to be performed before performing the step E2-3-2 of depositing the third dielectric material. This third processing step E2-3-3 has the advantage of being performed when the second portion 103b is covered by the second passivation layer 108.

[0152] For example, each processing step described in this specification enables the processing of an associated region, which is: a first portion 103a for the first processing step E2-1-3, a second portion 103b for the second processing step E2-2-3, or, if appropriate, a third portion 103c for the third processing step E2-3-3. The processing step improves the passivation of the region when a corresponding dielectric material (whichever is first, second, or third dielectric material) is deposited on the region to form a passivation layer that passivates the region. Therefore, each processing step may include one or more of the following steps: a cleaning step for removing hydrocarbons and / or carbon and / or oxygen adsorbed on the associated processing region; a step of surface etching of the native oxide of the material in the associated processing region, for example, forming the native oxide on the surface of the associated processing region (e.g., if the native oxide is an oxide of indium nitride, the surface etching step is NH4OH etching); a step of selectively etching the amorphous semiconductor already formed on the associated processing region (e.g., if the amorphous semiconductor is amorphous gallium nitride, a step of etching by TMAH, where TMAH represents tetramethylammonium hydroxide); a step of slowly etching the material forming the associated processing region, i.e., sufficiently repeatable etching to avoid etching the entire diode (e.g., if the material is GaN, the etching step is KOH etching, where KOH represents potassium hydroxide; when the associated processing region contains GaN, KOH can expose some crystal faces and obtain a very smooth surface, resulting in a processing region with far fewer structural defects); and a step of transplanting elements onto the associated processing region to prevent re-adsorption on the region and / or oxidation of the region. One advantage of transplanting elements is that these elements temporarily bring the region to equilibrium before the corresponding dielectric material is deposited on it, and the deposition of the dielectric material also eliminates the transplanted elements.

[0153] More generally, each processing step can be used to process the region associated with it, while preventing unsatisfactory molecular bonds from forming in the region during the deposition of the corresponding dielectric material.

[0154] Surface etching is considered a so-called "finishing" etching process used to obtain a surface of the etched material with a composition and crystal structure that is as close as possible to the composition and crystal structure of the corresponding solid semiconductor material.

[0155] Therefore, as a general rule, the first processing step E2-1-3 may include cleaning the first portion 103a and / or surface etching the first portion 103a and / or transferring elements onto the first portion 103a. The second processing step E2-2-3 may include cleaning the second portion 103b and / or surface etching the second portion 103b and / or transferring elements onto the second portion 103b. If necessary, the third processing step E2-3-3 may include cleaning the third portion 103c and / or surface etching the third portion 103c and / or transferring elements onto the third portion 103c. In the context of this paragraph, each etching step may remove adsorbed and / or amorphous material in the corresponding processed portion (first, second, or third portion 103a, 103b, 103c) of the side surface, and smooth and homogenize the electronic interface of the corresponding processed portion of the side surface 103 before depositing the corresponding dielectric material to avoid defects that could introduce trap energy levels into the gaps of the corresponding material. In the context of this paragraph, each step of the transplanting of elements, for example, if these elements are atoms, allows dangling bonds to be temporarily broken by thermodynamically stable atoms. These transplanted elements can introduce bonds into the corresponding portions of side surface 103, but these bonds will be broken during the deposition of the corresponding dielectric material onto the corresponding portions of side surface 103. For example, sulfur can prevent the oxidation of semiconductors by replacing oxygen. These atoms can be sulfur atoms, which are particularly useful for preventing the oxidation of GaN, InGN, AlGaN, GaP, InGaP, and AlInGaP. During the deposition of dielectric material on the corresponding portions of the side surface, the bonds of the transplanted elements / atoms break, in which case the deposition can be performed at high temperatures (typically strictly above 100°C), and plasma can be used if necessary. In fact, in the case of transplanted atoms, the transplant must have thermodynamically stable bonds at ambient temperature (in this case, ambient temperature is specifically equal to 300 Kelvin) to protect the surface to which it is transplanted, and these bonds must break at the deposition temperature of the corresponding dielectric material, which may be strictly above 100°C and strictly below 400°C. The cleaning steps described in this paragraph can be as described above; in other words, these cleaning steps, especially each of them, can ensure the removal of hydrocarbons and / or carbon and / or oxygen that have been adsorbed on, which may be, in some cases, the corresponding first portion 103a, second portion 103b or third portion 103c of the side surface 103.

[0156] Preferably, step E1, which forms the semiconductor layer stack 101, causes the stack 101 to include a first type of doped semiconductor material layer 109 and a second type of doped semiconductor material layer 110. In this case:

[0157] A first portion 103a of the side surface 103 is defined by a portion of the first type of doped semiconductor material layer 109.

[0158] The second portion 103b of the side surface 103 is defined by a portion of the active region 102.

[0159] - If needed, the third portion 103c of the side surface 103 may be defined by a portion of the second type of doped semiconductor material layer 110.

[0160] In this configuration, the active region 102 can be disposed between the first type-doped semiconductor material layer 109 and the second type-doped semiconductor material layer 110. Alternatively, the active region 102 can be disposed at the junction between the first type-doped semiconductor material layer 109 and the second type-doped semiconductor material layer 110. This structure is particularly suitable for the formation of the diode 100.

[0161] For each of the first and second dielectric materials, and, if appropriate, for the third dielectric material, the thickness of the corresponding dielectric material and its etching conditions are selected such that the deposited dielectric layer is not completely etched in any etching step following the deposition of that layer, thereby providing the desired function of the corresponding passivation layer in the diode 100. In summary, increasing the thickness of the deposited dielectric material, i.e., selecting an etching method that exhibits high etch selectivity between the semiconductor and dielectric materials of the stack 101 to be etched, or by increasing the polarization voltage or bias voltage, or by any one or all of these alternatives, makes the etching more directional.

[0162] The properties of the first to third dielectric materials described in the context of diode 100 are obviously applicable to the manufacturing method.

[0163] The deposition of each of the first to third dielectric materials is preferably performed conformally to allow for uniform and non-destructive deposition on the surface on which the deposition is performed (i.e., the deposition does not degrade the initial chemical and electronic state of the surface on which the deposition is performed).

[0164] Typically, in a finished diode 100, each passivation layer (specifically each of the first, second, and, if necessary, third passivation layers) has a negligible thickness, and is at least one atomic layer thick. Each passivation layer can have a thickness ranging from a few atomic layers to several hundred nanometers. In fact, the thickness must be sufficient to protect the passivation surface during any subsequent etching process, and during subsequent processing (if any), which may consume some of the previously deposited passivation layer.

[0165] According to a specific embodiment of the manufacturing method, wherein the diode 100 to be manufactured is a gallium nitride-based light-emitting diode, and in particular according to the specific example described above, the manufacturing method is described by way of example as follows.

[0166] When a stack 101 has already been provided, for example by forming a stack 101 on a substrate 112, and consisting of an anode material layer 114 and a hard mask 115 ( Figure 3 The hard mask 116 is covered and photolithography is performed to define the etched mask 116 in the hard mask.

[0167] The first etching step E2-1-1 may be chlorine / argon ICP (short for "inductively coupled plasma") etching, used to etch a hard mask 115 outside the etching mask 116, then etching the anode material used to form the anode 113, and then etching a first type doped semiconductor material layer 109 to define a first portion 103a of the side surface 103, which is then formed by p-type doped gallium nitride belonging to the first type doped semiconductor material layer 109. Figure 4 The first etching step E2-1-1 stops in the active region 102 (or, if appropriate, if the purpose is to manufacture...). Figure 2 The diode 100 stops in the second type of doped semiconductor material layer 110. It is worth noting that the first etching step E2-1-1 is performed anisotropically in a direction parallel to the stack axis A1 according to the etching mask 116.

[0168] Then the first processing step E2-1-3 can be applied to the first part 103a (especially in...). Figure 4 (Middle). This first processing step includes etching the first portion 103a by NH4OH etching, KOH etching, TMAH etching, or deoxidation etching. Deoxidation etching can be dilute HF (hydrofluoric acid) etching or buffered oxide etching, also known as BOE. This first processing step E2-1-3 tends not to consume the etching mask 116 and the anode 113 to avoid a situation where the first portion 103a is no longer encapsulated by the first dielectric material after the first dielectric material deposition step.

[0169] Step E2-1-2 for depositing the first dielectric material Figure 5 This allows aluminum oxide (e.g., Al2O3) or silicon oxide (e.g., SiO2) to be conformally deposited as a first dielectric material. This first dielectric material can be deposited using ALD (atomic layer deposition) or PE-ALD (plasma-enhanced atomic layer deposition).

[0170] Second etching step E2-2-1 Figure 6The etching process can be chlorine / argon ICP etching, used to etch the first dielectric material and the second type-doped semiconductor material layer 110. Stopping the second etching step E2-2-1 after reaching the second type-doped semiconductor material layer 110 helps define the active region 102. The result of this second etching step E2-2-1 is that the second portion 103b is formed from the material of the active region 102. This second etching step E2-2-1 tends not to consume the first dielectric material deposited on the first portion 103a.

[0171] The second processing step E2-2-3 can then be applied to the second part 103b (especially in...). Figure 6 (Middle). The second processing step E2-2-3 includes etching the second portion 103b by using etchant of NH4OH and / or (NH4)2S. Preferably, the second processing step E2-2-3 tends not to consume the first dielectric material deposited on the first portion 103a, or preferably does not consume the etch mask 116.

[0172] Step E2-2-2 for depositing the second dielectric material Figure 7 This allows alumina (e.g., Al2O3) to be conformally deposited as a second dielectric material. This second dielectric material can be deposited via ALD or PE-ALD.

[0173] Third etching step E2-3-1 Figure 8 The etching process can be chlorine / argon ICP etching, used to etch the second dielectric material and the second type-doped semiconductor material layer 110 to define a third portion 103c of the side surface 103. The result of this third etching step E2-3-1 is that the third portion 103c is formed of n-type doped gallium nitride belonging to the second type-doped semiconductor material layer 110. Specifically, the second portion 103c is separated from the second portion 103b by a portion of the second type-doped semiconductor material layer 110.

[0174] The third processing step E2-3-3 can then be applied to the third part 103c (especially in...). Figure 8 (Middle). The third processing step E2-3-3 includes etching the third portion 103c by NH4OH etching, KOH etching, or TMAH etching. The third processing step E2-3-3 tends not to consume the etch mask 116 and the second dielectric material deposited on the second portion 103b of the side surface 103.

[0175] Step E2-3-2 for depositing the third dielectric material Figure 9 This allows alumina (e.g., Al2O3) or silicon oxide (e.g., SiO2) to be conformally deposited as a third dielectric material. This third dielectric material can be deposited via ALD or PE-ALD.

[0176] Then, after step E2-3-2 of depositing the third material, it is possible to deposit it in two regions 118 and 119. Figure 10 The third passivation layer 111 is opened in order to allow at least a portion of the etch mask 116 to be removed so that the anode 113 can be accessed, and also to allow the cathode 117 ( Figure 1 It can be formed to contact with the second type of doped material layer 110.

[0177] The present invention is preferably applicable to so-called small light-emitting diodes, i.e., at least one of the dimensions in the stacked plane of semiconductor layers is less than or equal to 100 times the maximum diffusion length of an electron or hole or exciton in one of the semiconductors forming the stack 101.

[0178] The present invention is also applicable to arrays of light-emitting diodes, i.e., juxtaposition of light-emitting diodes to form an assembly of light-emitting diodes that are spatially close, or collective formation of light-emitting diodes that share the same support plate.

[0179] Although the examples of the embodiments primarily relate to gallium nitride-based light-emitting diodes, the invention is applicable to any other inorganic semiconductor and all light-emitting diode architectures.

[0180] Specifically, depending on the first type of doping and the second type of doping, the electrodes (anode and cathode) can be reversed for the first type of doped semiconductor material layer 109 and the second type of doped semiconductor material layer 110, respectively. Therefore, in general, the diode 100 may include electrodes configured to interact with the stack 101.

[0181] This invention describes industrial applications in the manufacture and use of diodes.

Claims

1. A diode, comprising: - A stack of semiconductor layers defined along a stacking axis, the stack including side surfaces. - Active regions arranged within the stack - A first passivation layer and a second passivation layer, each of which extends along an axis substantially parallel to the stacking axis at ±30 degrees. The first passivation layer and the second passivation layer are formed of a first dielectric material and a second dielectric material, respectively, thereby achieving passivation of the side surface by restricting the trapping of charge carriers; The first passivation layer is in contact with the side surface, and the second passivation layer is in contact with the side surface. The second passivation layer is partially formed on the first passivation layer. The stack includes a first type of doped semiconductor material layer and a second type of doped semiconductor material layer. - The first passivation layer contacts the first type of doped semiconductor material layer at the side surface. - The second passivation layer contacts the active region at the side surface. - The active region is disposed between the first type of doped semiconductor material layer and the second type of doped semiconductor material layer, or the active region is disposed at the junction between the first type of doped semiconductor material layer and the second type of doped semiconductor material layer.

2. The diode according to claim 1, characterized in that, The diode includes a third passivation layer that contacts the second type of doped semiconductor material layer at the side surface.

3. The diode according to claim 2, characterized in that, The third passivation layer is formed of a third dielectric material.

4. The diode according to claim 1, characterized in that: - The conductivity of the first dielectric material is at least three orders of magnitude lower than that of the first type of doped semiconductor material. - The conductivity of the second dielectric material is at least three orders of magnitude lower than that of the semiconductor material forming the active region.

5. The diode according to claim 1, characterized in that, The active region includes an intrinsic semiconductor material, and the band offset between the valence band of the intrinsic semiconductor material and the valence band of the second dielectric material is strictly greater than 3kT / q, and the band offset between the conduction band of the intrinsic semiconductor material and the conduction band of the second dielectric material is strictly greater than 3kT / q, where k is the Boltzmann constant, T is the ambient temperature in Kelvin, and q is a constant corresponding to the elementary charge in coulombs.

6. The diode according to claim 3, characterized in that, The conductivity of the third dielectric material is at least three orders of magnitude lower than that of the second type of doped semiconductor material.

7. The diode according to claim 3, characterized in that: - The first type is n-type, and the band offset between the conduction band of the first dielectric material and the conduction band of the first type of doped semiconductor material is strictly greater than 3kT / q. - The second type is p-type, and the band offset between the valence band of the third dielectric material and the valence band of the second type of doped semiconductor material is strictly greater than 3kT / q. Or it lies in - The second type is n-type, and the band offset between the conduction band of the third dielectric material and the conduction band of the second type of doped semiconductor material is strictly greater than 3kT / q. - The first type is p-type, and the band offset between the valence band of the first dielectric material and the valence band of the first type of doped semiconductor material is strictly greater than 3kT / q. Where k is the Boltzmann constant, T is the ambient temperature in Kelvin, and q is a constant corresponding to the elementary charge in coulombs.

8. A method for manufacturing a diode, the method comprising: - The step of forming a stack of semiconductor layers, a portion of which is used to form the active region of the diode. - The step of forming and passivating the side surface of a stack of semiconductor layers, the step of forming and passivating the side surface including forming a first passivation layer and forming a second passivation layer, the first passivation layer and the second passivation layer being in contact with the side surface, the second passivation layer being partially formed on the first passivation layer. The steps of forming and passivating the side surface include, in sequence: - A first etching step is performed on the stack to form a first portion of the side surface. - The step of depositing a first dielectric material to form the first passivation layer, the first passivation layer covering a first portion of the side surface. A second etching step is performed to etch the deposited first dielectric material and the stack to form a second portion of the side surface. - The step of depositing a second dielectric material to form the second passivation layer, the second passivation layer covering a second portion of the side surface and contacting the first passivation layer. The step of forming the stack of semiconductor layers makes the stack include: -Type 1 doped semiconductor material layer, - Second type doped semiconductor material layer, Its features are: - A first portion of the side surface is defined by a portion of the first type of doped semiconductor material layer. - The second portion of the side surface is defined by a portion of the active region. - The active region is disposed between the first type of doped semiconductor material layer and the second type of doped semiconductor material layer, or the active region is disposed at the junction between the first type of doped semiconductor material layer and the second type of doped semiconductor material layer.

9. The manufacturing method according to claim 8, characterized in that, The manufacturing method includes: - A first processing step applied to the first portion of the side surface prior to the step of depositing the first dielectric material. - A second processing step applied to the second portion of the side surface prior to the step of depositing the second dielectric material. The first processing step and the second processing step are different.

10. The manufacturing method according to claim 9, characterized in that: - The first processing step includes cleaning the first portion and / or etching the surface of the first portion and / or transferring elements onto the first portion. - The second processing step includes cleaning the second part and / or etching the surface of the second part and / or transferring elements onto the second part.

11. The manufacturing method according to claim 8, characterized in that, The steps of forming and passivating the side surface include: - A third etching step is performed to etch the deposited second dielectric material and the stack to form a third portion of the side surface. - The step of depositing a third dielectric material to form a third passivation layer, the third passivation layer covering a third portion of the side surface and in contact with the second passivation layer.

12. The manufacturing method according to claim 11, characterized in that, The manufacturing method includes a third processing step applied to a third portion of the side surface prior to performing the step of depositing the third dielectric material.

13. The manufacturing method according to claim 12, characterized in that, The third processing step includes cleaning the third part and / or etching the surface of the third part and / or transferring elements onto the third part.

14. The manufacturing method according to claim 11, characterized in that, The third portion of the side surface is defined by a portion of the second type of doped semiconductor material layer.

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