Perovskite semiconductor device

Abstract

A semiconductor device, including a semiconductor device comprising: a first electrode comprising a conductive material, wherein the conductive material is deposited by ink deposition (e.g., a layered material ink, such as graphene and / or graphite), or wherein the conductive material comprises CVD-grown graphene or carbon nanotubes; a first charge transport layer, wherein the first charge transport layer is doped with the conductive material of the first electrode; an optional insulating layer; a perovskite active layer; a second charge transport layer; and a second electrode.

Description

[0001] As a result, the project for which this application was submitted has received funding from the EU Hotizon 2020 Research and Graphene Flagship Grant Agreement No. 785219 and the Marie Skłodowska-Curie Grant Agreement No. 747381 under the Innovation Program. Technical Field

[0002] This invention relates to perovskite-based semiconductor devices. Semiconductor devices include solar cells and light-emitting devices. Background Technology

[0003] Perovskite-based semiconductor devices have been described previously, such as in WO2015166066, WO2016083783, and WO2017001542. Due to the high efficiency at low cost, metal halide perovskite devices have generated considerable interest in their use.

[0004] For example, metal halide perovskite solar cells (PSCs) are considered the most promising low-cost photovoltaic (PV) technology due to their high photovoltaic efficiency and solution processability. PSCs have significant potential because halide perovskite semiconductors have complementary absorption spectra compared to silicon (Si), allowing for the creation of tandem solar cells by stacking PSCs on top of Si solar cells, thereby significantly improving the efficiency of existing silicon photovoltaics.

[0005] However, the commercialization of PSCs still faces ongoing challenges, including low device stability under environmental conditions, the use of expensive components such as metal electrodes (gold or silver) and hole transport materials (spiral-MeOTAD and PTAA), and the need for high processing conditions, including high-temperature ultra-high vacuum deposition equipment. These complexities combine to increase manufacturing costs and complexity, and reduce the scalability of device fabrication.

[0006] Therefore, new perovskite-based semiconductor devices are still needed to overcome or mitigate some or all of the problems mentioned above. Summary of the Invention

[0007] The applicant has discovered that, according to the present invention, using a specific electrode in conjunction with a doped implantation layer and a perovskite active layer can provide a semiconductor device with enhanced properties.

[0008] According to one aspect of this disclosure, a semiconductor device is provided, comprising:

[0009] The first electrode includes a conductive material, wherein the conductive material is deposited by ink deposition (e.g., layered material ink, such as graphene and / or graphite), or wherein the conductive material includes CVD-grown graphene or carbon nanotubes.

[0010] A first charge transport layer, wherein the first charge transport layer is doped with the conductive material of the first electrode;

[0011] Optional insulation layer;

[0012] Perovskite active layer;

[0013] The second charge transport layer; and

[0014] Second electrode.

[0015] The device according to the present invention has improved performance compared to existing devices. Improved performance may include increased efficiency (e.g., power conversion efficiency or PCE). Improved performance may also include enhanced device stability. Manufacturing the device according to the present invention can reduce production costs, thereby resulting in an overall improvement in device cost efficiency.

[0016] Another advantage of providing a conductive material in the first electrode and serving as a dopant in the first charge transport layer is that it enhances the low initial conductivity of the first charge transport layer (which may be a hole transport injection layer) and forms a better network to extract holes from the perovskite active layer.

[0017] By avoiding the need for standard metal electrodes while maintaining sufficient performance levels, device scalability can be improved and production speeds can be significantly increased, for example, by avoiding the thermal evaporation process required for metal-based electrodes. By utilizing this invention, for example, commercially attractively efficient and cost-effective printable electrodes can be manufactured.

[0018] In another aspect, a method for manufacturing a semiconductor device is provided, comprising: applying a first electrode to the device by ink deposition, wherein the ink comprises a conductive material dispersed in a solvent, wherein the selected solvent is compatible with the perovskite layer, and wherein the solvent is selected from IPA, ethanol, and ethyl acetate.

[0019] Optionally, the first electrode can be a nanoplate electrode, i.e., a printed nanoplate electrode, wherein the nanoplate may comprise microfluidized graphite or graphene. Advantageously, this allows for the fabrication of PSCs in a low-cost and fully printable manner.

[0020] By utilizing a conductive material (e.g., ink) dispersed in a solvent to form the first electrode, the scalability of the device is improved, and production speed can be significantly increased, for example, by avoiding the thermal evaporation process required for metal-based electrodes. Using this invention, commercially attractive, efficient, and cost-effective devices based on printable electrodes can be manufactured. The use of specific solvents in this invention protects other layers in the device.

[0021] In another aspect, a method for manufacturing a semiconductor device is provided, the semiconductor device including a first electrode, the method comprising: doping a charge transport layer adjacent to the first electrode with a conductive material of the first electrode. For example, a graphene / graphite electrode is used and an adjacent charge transport layer is doped with graphene / graphite.

[0022] This method improves the efficiency of devices, such as power conversion efficiency (PCE).

[0023] In another aspect, the present invention provides a semiconductor device comprising: a first electrode; a first charge transport layer, wherein the first charge transport layer is doped with a conductive material of the first electrode; an insulating layer; and a perovskite active layer. This combination has been found to possess particularly advantageous characteristics in terms of both efficiency and stability.

[0024] In another aspect of the invention, a semiconductor device is provided, comprising a charge-injected layer doped with a material for forming adjacent electrodes. This method improves the performance of the device.

[0025] In another aspect, a solar cell is provided, comprising a semiconductor device according to the invention.

[0026] In another aspect, an LED is provided, comprising a semiconductor device according to the invention. Attached Figure Description

[0027] Figure 1 An exemplary device according to the present invention is shown.

[0028] Figure 2 Another exemplary device according to the present invention is shown.

[0029] Figure 3 The viscosity of the ink manufactured according to the present invention as a function of shear rate is shown.

[0030] Figure 4 shows the stability of the nanoplate electrode ink over several months.

[0031] Figure 5 Images show fresh ink and ink that has been stored at room temperature for several months.

[0032] Figure 6 A schematic diagram of charge transport layer doping is shown.

[0033] Figure 7 The following are shown: (a) a halide perovskite film on glass, (b) a blade-coated graphene ink on a perovskite layer, (c) a perovskite / graphene heterostructure after the ink has been cured at room temperature, and (d) the thickness of the printed and cured microfluidic graphene film.

[0034] Figure 8The IV curve of the device manufactured according to the present invention is shown.

[0035] Figure 9 The stability test of the PSC manufactured according to the present invention with a device having an Au back electrode is shown (the unpackaged device was exposed to harsh conditions of 60°C / 60% relative humidity).

[0036] Figure 10 The IV curves of a device manufactured according to the present invention are shown, compared with a device having a gold back electrode but otherwise identical.

[0037] Figure 11 The stability test of the device under environmental conditions without packaging is shown in the PSC according to the present invention.

[0038] Figure 12 The graphene interlayer ink prepared in which the nanoplate concentration in IPA is 1 mg / ml is shown.

[0039] Figure 13 A (a) front view, (b) back view and (c) front schematic diagram of a PSC fabricated using graphene counter electrodes according to the present invention are shown.

[0040] Figure 14 Exemplary devices according to the invention are shown in the following: (a) an exemplary device with a 25 μm thick graphene counter electrode, (b) an exemplary device according to the invention having a graphene interlayer and a 10 μm thick graphene counter electrode, and (c) an exemplary device according to the invention using a LiTFSI / ACN solution for post-fabrication processing.

[0041] Figure 15 The IV profiles of the device manufactured according to the present invention before and after post-manufacturing LiTFSI treatment are shown.

[0042] Figure 16 The following figures illustrate (a) photovoltage versus light intensity, (b) photovoltage increase, and (c) normalized photovoltage decrease of a device manufactured according to the present invention before and after post-manufacturing LiTFSI treatment. Detailed Implementation

[0043] The following embodiments apply to all aspects of the present invention. The present invention provides a semiconductor device comprising: a semiconductor device comprising: a first electrode including a conductive material, wherein the conductive material is deposited by ink deposition (e.g., layered material ink, such as graphene and / or graphite), or wherein the conductive material comprises CVD-grown graphene or carbon nanotubes; a first charge transport layer, wherein the first charge transport layer is doped with the conductive material of the first electrode; an optional insulating layer; a perovskite active layer; a second charge transport layer; and a second electrode.

[0044] The term "semiconductor device" can refer to a solar cell. A semiconductor device can also be a light-emitting device. A semiconductor device can be a transistor, a photodetector, or a laser.

[0045] In another embodiment, a solar cell including the semiconductor device as described herein is provided. In another embodiment, a light-emitting device including the semiconductor device as described herein is provided.

[0046] The "first electrode" according to the invention deposits or includes CVD-grown nanomaterials via ink deposition. Suitable electrodes are deposited from printable conductive inks. Such inks can be perovskite-compatible inks that incorporate low-temperature processing and solvent compatibility.

[0047] Conductive materials suitable for printable conductive inks include layered material inks. Suitable layered material inks include graphene, graphite, and MXenes. The layered material can be a nanoplate, including graphite / graphene nanoplates. The first electrode can be a first nanoplate electrode.

[0048] Conductive materials suitable for printable conductive inks also include carbon inks (such as carbon black, carbon / graphite, graphite, and carbon nanotube inks).

[0049] Conductive materials suitable for printable conductive inks also include metallic inks, such as nanowire inks, including silver and copper inks, such as silver and copper nanowire inks.

[0050] Once deposited, the first electrode will include conductive materials such as graphene, graphite, carbon nanotubes, silver or copper nanowires, etc.

[0051] In an alternative embodiment, the first electrode is not deposited by ink deposition, but comprises nanomaterials grown by chemical vapor deposition (CVD), including graphene or carbon nanotubes.

[0052] Therefore, the first electrode comprises a variety of materials, primarily nanomaterials deposited via CVD, but more preferably via ink deposition. Once deposited, this layer forms a suitable electrode.

[0053] In a preferred embodiment, the first electrode is a first nanoplate electrode. In another embodiment, the first electrode is a layered material electrode. In yet another embodiment, the first electrode is a graphene / graphite nanoplate electrode.

[0054] The “first nanoplate electrode” comprises a layered material containing graphite / graphene nanoplates. Typically, a single nanoplate is understood to consist of multiple stacked layers, forming a plate, i.e., a structure whose width is greater than its thickness. This can also be referred to as aspect ratio. Graphite nanoplates can also be defined as “single-layer / multi-layer graphene”.

[0055] To avoid ambiguity, the term "first nanoplate electrode" refers to an electrode that includes nanoplates. The electrode itself is not nanoscale, but rather comprises nanoscale materials.

[0056] More generally, nanoplates typically involve high aspect ratio structures, i.e., an aspect ratio greater than about 5. The thickness of an individual nanoplate can be less than about 100 nm and greater than about 500 nm. When formed as electrodes, nanoplates can form or resemble nematic structures, i.e., structures associated with the following state: the nanoplates are generally or locally parallel-oriented, but not arranged in a well-defined plane (e.g., layers in bulk graphite).

[0057] When in bulk materials or during manufacturing, graphite nanoplates may be referred to as microfluidic graphite, comprising multiple stacked layers of graphene. Preferably, this may correspond to a thickness of about 10 nm or less, or about 20 or fewer individually stacked graphene layers. Most preferably, these layers are pristine graphite and the nanoplate is a graphite nanoplate.

[0058] However, it should be understood that graphene nanoplates may comprise stacked graphene layers of more or fewer layers. Advantageously, the use of high pressure (>30 kpsi) during the exfoliation step included in the fabrication of microfluidic graphite can achieve graphite / graphene nanoplates with very small thicknesses (e.g., monolayer / several layers of graphene, less than 10 layers thick) to achieve a useful concentration of only monolayer / several layers of graphene.

[0059] US 2018 / 0312404 (the contents of which are incorporated herein by reference) discloses a method for producing layered material dispersions using a high-shear microfluidic process. Such layered materials are suitable for use in this invention.

[0060] In a preferred embodiment, the first nanoplate electrode is made of a conductive ink comprising graphite / graphene nanoplates. The conductive ink comprises nanoplates dispersed in a suitable carrier liquid.

[0061] The nanoplate electrode can be printed from a precursor material, which can be a dispersion comprising graphene nanoplates at a concentration of about 5 g / L or higher in a suitable solution. This forms a viscous paste, allowing for subsequent printing, such as by screen and flexographic printing, spraying, doctor blade printing, etc. Advantageously, the high viscosity provided by the high concentration prevents flocculation (i.e., undesirable agglomeration) in the nanoplates. More preferably, the layered material (e.g., graphene nanoplates) is present in the precursor dispersion at a concentration of at least about 10 g / L.

[0062] Preferably, the conductive ink is obtained by processing graphite with a microfluidic device to obtain graphite / graphene nanoplates.

[0063] This invention allows for the production of stable nanoplates from layered materials via microfluidization without the need for stabilizers. This enables the production of highly conductive pure dispersions (with sheet resistance below 5 ohms per square for approximately 20 μm films) in the case of graphite / graphene nanoplates.

[0064] The purity and lack of additives allow these dispersions to be used in room temperature or low temperature processing without the need for high-temperature treatments like annealing to achieve high conductivity. This makes them suitable for devices with other materials or components that cannot withstand high-temperature processing, such as halide perovskite absorbers and organic hole transport materials.

[0065] The concentration of the dispersion can be 5 g / L or higher, preferably forming a viscous paste, which can be applied by screen printing and flexographic printing, spraying and doctor blade application.

[0066] In a preferred embodiment, the nanoplate is dispersed in a solvent compatible with other layers in the device, such as a charge transport layer or an active perovskite layer. The solvent may be selected such that the material used for the charge transport layer is insoluble. The solvent may be selected to be compatible with the perovskite layer. The solvent may be selected to be compatible with the microfluidic device. A suitable solvent is IPA. Other suitable solvents include ethanol and ethyl acetate.

[0067] Therefore, in one aspect of the present invention, a method for manufacturing a semiconductor device having nanoplate electrodes is provided, wherein the nanoplate electrodes are applied by means of a conductive ink and the conductive ink uses a solvent compatible with perovskite and / or charge transport layer, such as IPA, ethanol and ethyl acetate, most preferably IPA.

[0068] For example, direct microfluidization of graphite in IPA allows for the production of stable graphite / graphene nanoplate inks without the need for stabilizers (which is beneficial for the required low-temperature processing).

[0069] As another example, P3HT has a solubility of less than 0.1 mg / ml in IPA, so the injection layer can protect all other layers underneath.

[0070] The "first charge transport layer" can be formed of a semiconductor material. In another embodiment, the first charge transport layer can be formed of an organic semiconductor material.

[0071] The first charge transport layer can be a hole-carrying organic or inorganic semiconductor material. This material can be selected from the group consisting of PEDOT, PSS, PANI (polyaniline), polypyrrole, and optionally substituted doped poly(ethylene dioxythiophene) (PEDOT).

[0072] Organic hole transport materials include poly(triarylamines), such as PTAA (poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine]); benzodithiophene (BDT) based polymers; polymers, poly(p-phenylene)PPP; lead phthalocyanine (PbPc); poly(9,9-dioctylfluorene-co-N-(4-(3-methylpropyl))diphenylamine (TFB); polythiophene (PT); poly(4,4'-bis(N-carbazolyl)-1,1'-biphenyl) (PPN).

[0073] Inorganic hole transport materials include nickel oxide (NiO); copper thiocyanate (CuSCN); copper iodide (CuI); CuInS2 (quantum dots); and ternary oxides: Li 0.05 Mg 0.15 Ni 0.8 O.

[0074] The first charge transport layer can include small organic molecules such as HTM (spiro-OMeTAD); FDT (triazine based on dithiophene); and PCP-TPA, a triphenylamine-based compound.

[0075] The first charge transport layer may be a hole-transporting organic semiconductor material selected from polyfluorene (preferably F8, TFB, PFB or F8-TFB) or spiro-OMe TAD or polycarbazole (preferably poly(9-vinylcarbazole)) or 4,4'-bis(N-carbazolyl)-1,1'-biphenyl, or poly(3-hexylthiophene-2,5-diyl) (P3HT).

[0076] In a preferred embodiment, the first charge transport layer is poly(3-hexylthiophene-2,5-diyl) (P3HT). In a preferred embodiment, the first charge transport layer is poly[2,2””-bis[[(2-butyloctyl)oxy]carbonyl][2,2':5',2”:5”,2””-tetrathiophene]-5,5”’-diyl] (PDCBT). In a preferred embodiment, the first charge transport layer is poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] (PTAA). In a preferred embodiment, the first charge transport layer is copper thiocyanate (CuSCN). In a preferred embodiment, the first charge transport layer is diketopyrrolopyrrole (pDPP5T-2).

[0077] More preferably, the first charge transport layer is P3HT, PDCBT, or CuSCN.

[0078] In a preferred embodiment, the first charge transport layer is P3HT. In a preferred embodiment, the first charge transport layer is PDCBT. In a preferred embodiment, the first charge transport layer is CuSCN.

[0079] In a preferred embodiment, the first charge transport layer is a doped charge injection layer. In a preferred embodiment, the charge transport layer is doped with a first electrode material. For example, a device using graphene / graphite layered material in the first electrode can have a charge injection layer doped with the same layered material.

[0080] More specifically, in a further preferred embodiment, the first charge transport layer may be a hole injection layer (or more generally, a hole transport material) disposed adjacent to the first electrode. The first electrode may include graphene / graphite nanoplates and the first charge transport layer is doped with graphene / graphite nanoplates. Advantageously, doping the hole injection / transport layer with graphene provides a non-hygroscopic dopant while achieving high conductivity.

[0081] As mentioned earlier, traditional PSC devices use lithium salt dopants in the hole transport layer, which is detrimental to the long-term stability of solar cells and is relatively expensive. Using graphene / graphite nanosheets can avoid the need for such lithium salts in the hole transport layer.

[0082] Furthermore, graphene / graphite nanosheets (or microfluidic graphite) or other conductive materials can be printed to form electrodes, which allows for fully printable PSC devices.

[0083] In a preferred embodiment, the charge transport layer has 0.5 to 3%, 0.5 to 2.5%, 1 to 3%, 1 to 2%, 0.5, 1, 1.5, 2, 2.5 or 3% doping.

[0084] In a preferred embodiment, the charge transport layer is doped with the same material as the first electrode. However, in other embodiments, different but suitable load-doping materials may be used. In a preferred example, the first charge transport layer (which may be a hole transport layer) is doped with a small amount (about 2%) of low concentration (e.g., about 2 mg / ml) of microfluidized graphite ink, and the first electrode further includes a higher concentration (up to 100%) of the same microfluidized graphite (i.e., graphene nanoplatelets).

[0085] Therefore, according to the present invention, a semiconductor device including a charge injection layer doped with an electrode material is provided. In a preferred embodiment, the electrode material is graphene / graphite. In another preferred embodiment, the charge injection layer is a hole injection layer. In yet another preferred embodiment, the hole injection layer is P3HT. In still another embodiment, the charge injection layer has a doping content of 0.5 to 3%, 0.5 to 2.5%, 1 to 3%, 1 to 2%, 0.5, 1, 1.5, 2, 2.5, or 3%. In a preferred embodiment, the active layer is perovskite. In another preferred embodiment, an insulating layer exists between the active layer and the doped charge injection layer.

[0086] The "insulating layer" may be formed of an insulating polymer and is selected from the group consisting of poly(ethyleneimine) (PEI), polyethyleneimine-ethoxylated (PEIE), polystyrene (PS), poly(methyl methacrylate) (PMMA), and organohalide salts such as phenylethyl ammonium iodide (PEAI), guanidine iodide (GuI), guanidine bromide (GuBr), n-butylammonium iodide (BAI), n-butylammonium bromide (n-BABr), and ethylenediammonium diiodide (EDAI2). In a preferred embodiment, the insulating layer is an organohalide salt. In another preferred embodiment, the insulating layer is phenylethyl ammonium iodide (PEAI).

[0087] The insulating layer can be deposited by any suitable method, including atomic layer deposition, ALD, spin coating, or thermal evaporation.

[0088] In the embodiments, thin layers of selected molybdenum trioxide and tungsten trioxide less than 30 nm are deposited between the electrode and the perovskite layer, between the charge transport layer and the electrode, between the electrode and the charge transport layer, between the perovskite layer and the charge transport layer, or between the perovskite layer and the electrode.

[0089] The "perovskite active layer" may include halide perovskites. The halide perovskite may be an organometal halide perovskite, an inorganic metal halide perovskite, or a mixed organo-inorganic metal halide perovskite material. This invention does not impose any particular limitation on the selection of the perovskite active layer, as long as it possesses the desired properties. Therefore, in embodiments of this invention, any suitable perovskite layer can be used. The perovskite may be a 3D perovskite. The perovskite may have a lower dimensionality. The perovskite may be a 2D perovskite. The perovskite may be a 1D perovskite. The perovskite may be a quasi-2D perovskite (i.e., a 2D / 3D perovskite).

[0090] In the embodiments, the perovskite may be an organometal halide perovskite and may have an AMX3 structure, wherein A is a monovalent organic cation or a monovalent metal cation, M is a divalent cation, and X is a halide anion.

[0091] In the embodiments, A can be a monovalent organic cation or a monovalent metal cation.

[0092] A can be a... 1-i B i A dication with a structure in which: A and B are both monovalent organic cations or monovalent metal cations, wherein A and B are different; and i is between 0 and 1.

[0093] A can be a... α B β C γThe structure is a trivalent cation, wherein A, B, and C are monovalent organic cations or monovalent metal cations, and A, B, and C are different; and the combination of α, β, and γ is equal to 1.

[0094] A can be a... α B β C γ D δ The structure is a tetravalent cation in which: A, B, C and D are all monovalent organic cations or monovalent metal cations, and A, B, C and D are different; and the combination of α, β, γ and δ is equal to 1.

[0095] Monovalent organic cations can be primary, secondary, or tertiary ammonium cations [HNR] 1 R 2 R 3 ] + , where R 1 R 2 and R 3 Each of them can be the same or different and is selected from hydrogen, unsubstituted or substituted C. 1 -C 20 Alkyl groups and unsubstituted or substituted C 5 -C 18 Aryl. Examples of suitable substituents for alkyl groups are alkoxy groups having 1-20 carbon atoms, hydroxy groups, mono- and dialkylamino groups having 1-20 carbon atoms (each alkyl group may be the same or different), cyano, nitro, thiol, sulfinyl, sulfonyl, and aryl groups having 5 to 18 carbon atoms. Examples of suitable substituents for alkyl groups are alkyl groups having 1-20 carbon atoms, alkenyl and ynyl groups each having 2-20 carbon atoms, alkoxy groups having 1-20 carbon atoms, haloalkyl groups having 1-20 carbon atoms, hydroxy groups, mono- and dialkylamino groups having 1-20 carbon atoms (each alkyl group may be the same or different), cyano, nitro, thiol, sulfinyl, and sulfonyl.

[0096] In the embodiments, the monovalent organic cation may have [R 1 R 2 N-CH=NR 3 R 4 ] + Format:

[0097]

[0098] Among them, R 1 R 2 R 3 and R 4 Each of them may be the same or different, and is selected from hydrogen, unsubstituted or substituted C1-C. 20 Alkyl and unsubstituted or substituted C5-C18 Aryl.

[0099] In the embodiments, the monovalent organic cation can be (R 1 R 2 N)(R 3 R 4 N)C=N + R 5 R 6 Format:

[0100]

[0101] Among them, R 1 R 2 R 3 R 4 R 5 and R 6 They can be the same or different, and are selected from hydrogen, unsubstituted or substituted C1-C. 20 Alkyl and unsubstituted or substituted C5-C 18 Aryl.

[0102] In the embodiments, the monovalent metal cation can be an alkali metal cation.

[0103] In the embodiment, the monovalent metal cation is cesium (Cs). + ), Rubidium (Rb + ) and / or potassium (K + ).

[0104] In the examples, M is a divalent cation.

[0105] In another embodiment, M has M 1-j N j The structure is given by , where M and N are both divalent metal cations; and j is between 0 and 1.

[0106] In another embodiment, M has M ε N ζ O η The structure is such that M, N, and O are all divalent metal cations, wherein M, N, and O are different; and the combination of ε, ζ, and η equals 1.

[0107] The divalent cation M can be a divalent metal cation, such as, but not limited to, tin ions (Sn). 2+ ), lead ions (Pb) 2+ ), cobalt ions (Co) 2+ ) and / or zinc ions (Zn 2+ ).

[0108] In the embodiments, X is a halide anion.

[0109] In another embodiment, X has a structure X. 3-k Y k In this context, X and Y are both halide anions, but X and Y are different; and k is between 0 and 3.

[0110] In yet another embodiment, X has X α Y β Z γ The structure is such that X, Y, and Z are all halide anions, A, B, and C are different, and the combination of α, β, and γ equals 1.

[0111] Halogen anions can be selected from chlorides, bromides, iodides, and fluorides, while sulfide anions can be selected from sulfides, selenides, arsenides, and tellurides.

[0112] Preferably, the halide anion may be selected from chloride ions, bromide ions, iodide ions, and fluoride ions. Preferably, at least one of X, Y, or Z includes a bromide.

[0113] The present invention, as described above, includes all combinations of the aforementioned perovskites. For example, perovskites can take the following forms:

[0114]

[0115]

[0116] Perovskites can also be tetravalent cations and / or ternary metals, and their arrangement is available.

[0117] Trivalent cation perovskites are particularly preferred. Mixed halide perovskites are also preferred.

[0118] The "second charge transport layer" can be formed of a semiconductor material. In another embodiment, the second charge transport layer can be formed of an organic semiconductor material.

[0119] The second charge transport layer can be an electron transport organic semiconductor material. This material can be selected from poly(fluorene), preferably from the group consisting of F8, TFB, F8BT, or F8-TFB AB copolymer (95:5 F8:TFB).

[0120] The electron transport semiconductor material can be selected from electron transport materials (ETLs), including inorganic ETLs such as TiO2; ZnO; SnO2; ZrO2; SrTiO3; ZnSnO4; or WO3; or organic ETLs such as PCBM: polystyrene; C60; PEHT; or polyethyleneimine (PEI) or poly(ethyleneimine) ethoxylated (PEIE) or 2-methoxyethanol; PCBM or PCBM: PMMA. The material can be a mesoporous membrane. Alternatively, the material can be a bulk / dense thin film.

[0121] The second charge transport layer can be an electron transport inorganic semiconductor material selected from the group consisting of titanium dioxide (TiO2), zinc oxide (ZnO), zinc magnesium oxide (MgZnO), and aluminum-doped ZnO (AZO).

[0122] In a preferred embodiment, the second charge transport layer is TiO2. In a preferred embodiment, the second charge transport layer is ZnO. In a preferred embodiment, the second charge transport layer is SnO2. In a preferred embodiment, the second charge transport layer is C60. In a preferred embodiment, the second charge transport layer is PCBM. In a preferred embodiment, the second charge transport layer is ZnSnO4.

[0123] In a preferred embodiment, the second charge transport layer is TiO2. In a preferred embodiment, the second charge transport layer is SnO2. In a preferred embodiment, the second charge transport layer is PCBM or PCBM:PMMA.

[0124] For the avoidance of doubt, the charge transport layers (first and / or second charge transport layers) described herein may include combinations of the materials outlined above. For example, an electron transport layer may include ZnO coated with PEIE. Other combinations include dense and / or mesoporous TiO2 coated with LiTFSI or C60, PCBM, PCBM:PMMA, PCBA, or benzoic acid.

[0125] In one embodiment, the device may include a TiO2 electron transport layer and a spiro-MeOTAD hole transport layer. The device may be a solar cell. In an alternative embodiment, the device may include a ZnO-PEIE electron transport layer and a TFB hole transport layer. The device may be an LED.

[0126] The "second electrode" can preferably be formed of a transparent conductive material.

[0127] The second electrode can be formed from indium tin oxide (ITO), fluorine-doped tin oxide (FTO), indium zinc oxide, graphene, carbon nanotubes, and silver nanowires. The electrode can also be formed from metal. The thickness of the metal can reach 100-150 nm.

[0128] Figure 1 An example device according to the present invention is shown, which illustrates a first electrode (102), a first charge-injected layer (104), an insulating layer (106), a perovskite active layer (108), a second charge-injected layer (110), and a second electrode layer (112). The first charge-injected layer (104) may be a doped charge-injected layer. This layer may be doped with the same material as the first electrode, for example, graphene.

[0129] Additional layers or regions may exist between each region. For example, an insulating layer may exist between the perovskite active layer and the second charge-injected layer. However, typically, each region described is in contact with both the front and back regions as disclosed herein. The invention does not exclude the presence of additional layers. In fact, one advantage of the invention is that it can be incorporated, for example, into tandem solar cells. For the avoidance of doubt, the multilayers described herein have been identified as leading to advantageous characteristics. The invention does not exclude the presence of additional layers in the device. These additional layers may be on either side of the layers described herein. These additional layers may also be between the layers described herein. However, in the later embodiments, additional layers do not negate the technical effects obtained by the current layer orientation described herein.

[0130] In embodiments of the present invention, the first electrode may have a layer thickness >1 μm. In embodiments, the first charge-injected layer has a layer thickness >10 nm. In embodiments, the insulating layer has a layer thickness <30 nm. In embodiments, the active perovskite layer has a layer thickness >100 nm. In embodiments, the electron-injected layer has a layer thickness >100 nm, for example, dense (c-)TiO2 >10 nm; mesoporous (m-)TiO2 >100 nm. In embodiments, the second electrode may have a layer thickness >250 nm.

[0131] Figure 2 Another example device is shown. Although the graphene shown is 2% doped, this can be changed as described herein.

[0132] In embodiments of the invention, an interlayer may exist between the first electrode and the first charge transport layer. The "interlayer" according to the invention may include a conductive material. Alternatively, the "interlayer" according to the invention may include an ultrathin (below 5 nm) insulating film. The interlayer may be deposited by ink deposition or may include CVD-grown nanomaterials. The conductive interlayer may include any material described as suitable for forming the first electrode. The ultrathin insulating interlayer may include any insulating material as defined herein.

[0133] In an embodiment, the interlayer may comprise the same material as the first electrode. The interlayer material may be produced from a conductive ink comprising graphite / graphene nanoplates. The conductive ink comprises nanoplates dispersed in a suitable carrier liquid. The interlayer may be printed from a precursor material, which may be a dispersion comprising graphene nanoplates of varying concentrations in a suitable solution. When both the interlayer and the first electrode are printed from a precursor material, the concentration of graphene nanoflakes in the precursor material used to print the interlayer may be lower than the concentration of graphene nanoflakes used to print the first electrode.

[0134] The concentration of graphene nanosheets, which are precursor materials for the printed interlayer, can be from about 0.1 g / L to 5 g / L. Other ranges include 0.2 g / L to 4 g / L, 0.5 g / L to 3 g / L, 0.5 g / L to 2 g / L, 1 g / L to 5 g / L, about 1 g / L, 1 g / L or more.

[0135] The interlayer according to the present invention can be deposited by spin coating.

[0136] In embodiments, the thickness of the interlayer can be between about 2 and 50 nm. In preferred embodiments, the interlayer can have a thickness of about 2 to 40 nm, 2 to 30 nm, 5 to 20 nm, 5 to 15 nm, or about 10 nm.

[0137] The interlayer described herein can serve as a conductive bridge between the first electrode and the first charge transport layer. Not wishing to be bound by theory, the interlayer described herein can also act as a support during the formation of the first electrode, which can improve the uniformity of the first electrode and enhance the reproducibility of the device. Compared to devices without an interlayer, devices including the interlayer described herein can fabricate a thinner first electrode without reducing the achievable PCE of the device. For example, compared to a device with a thicker first electrode and no interlayer, a device with an interlayer can have a first electrode thickness of less than 5 μm without sacrificing PCE. Preferably, the thickness of the first electrode in a device with an interlayer is approximately 10 μm.

[0138] In a preferred embodiment, the device may include an interlayer layer between a first electrode and a first charge transport layer as defined herein, wherein the thickness of the first electrode is less than 25 μm, preferably less than 20 μm, less than 15 μm, less than 12 μm, less than 10 μm, less than 8 μm, less than 6 μm, about 1 to 25 μm, about 3 to 20 μm, about 5 to 15 μm, about 7 to 12 μm, about 5 μm, about 6 μm, about 7 μm, about 8 μm, about 9 μm, about 10 μm, about 11 μm, about 12 μm, about 13 μm, about 14 μm, about 15 μm; preferably, about 10 μm. The interlayer layer may have a thickness of about 2 to 40 nm, 2 to 30 nm, 5 to 20 nm, 5 to 15 nm, or about 10 nm.

[0139] In embodiments of the invention, a metal salt or a salt having electron-accepting (p-type doping) properties may be present at one or more interfaces between layers of the semiconductor device. Such devices may exhibit improved performance, including improved fill factor and / or improved PCE, compared to devices where the metal salt is absent at one or more interfaces between layers. It is not intended to be theoretically restrictive, but the improved performance may be due to improved interfacial contact between layers of the semiconductor device, reduced trap-assisted recombination at the interfaces, and / or increased carrier lifetime.

[0140] According to embodiments, metal salts may be present at the interface between the perovskite active layer and the layer of the semiconductor device adjacent to the perovskite active layer, at the interface between the first charge transport layer and the layer of the semiconductor device adjacent to the first charge transport layer, and / or at the interface between the first electrode and the layer of the semiconductor device adjacent to the first electrode. For example, the presence of metal salts at the interfaces can reduce gaps between the layers of the device manufactured according to the present invention.

[0141] After device fabrication, a metal salt can be introduced into the device manufactured according to the present invention. In one embodiment, the metal salt can be introduced into the device by applying the metal salt to the surface of the first electrode. In another embodiment, the metal salt can be introduced into the device by depositing a solution comprising the metal salt onto the first electrode. The solution may comprise a metal salt in acetonitrile (ACN). The solution may be spin-cast / permeate over the first electrode. Alternatively, the salt can be applied by solution treatment or thermal evaporation.

[0142] It is undesirable to be bound by theory that the solution cannot penetrate the device any deeper than the interface between the first electrode and the first interlayer or the first charge transport layer.

[0143] It should be understood that depositing salt onto the finished device after manufacturing according to the invention is different from applying salt to each layer of the device during manufacturing. It should also be understood that the post-manufacturing treatment with metal salts according to the invention can improve devices with or without interlayer layers.

[0144] In embodiments of the present invention, any suitable metal salt having electron-accepting (p-type doping) properties can be used.

[0145] The metal salt can be a lithium metal salt. An exemplary (but not limited to) lithium metal salt is lithium bis(trifluoromethane)sulfonylimide (LiTFSI) salt.

[0146] The metal salt can be a cobalt metal salt. Exemplary (but not limited to) cobalt metal salts include tris(2-(1H-pyrazol-1-yl)pyridine)cobalt(III) (FK102), tris(2-(1H-pyrazol-1-yl)-4-tert-butylpyridine)cobalt(III)tris[hexafluorophosphate] (FK209), bis(2,6-bis(1H-pyrazol-1-yl)pyridine)cobalt(III)tris(bis(trifluoromethanesulfonyl)imine) (FK269), tris[2-(1H-pyrazol-1-yl)pyrimidine]cobalt(III)tris[bis(trifluoromethanesulfonyl)imine] (MY11), and bipyridine cobalt complexes.

[0147] The metal salt can be a copper metal salt. Exemplary (but not limited to) copper metal salts include CuI, CuSCN, copper(II)-pyridine complexes comprising bis[di(pyridin-2-yl)methane]copper(II)bis[bis(trifluoromethyl-sulfonyl)imide][Cu(bpm)2] and bis[2,2'-(chloromethylene)-bipyridine]copper(II)bis[bis(trifluoromethyl-sulfonyl)imide][Cu(bpcm)2], and Cu(bpcm)2.

[0148] The metal salt may be a silver metal salt. Exemplary (but not limited to) silver metal salts include AgTFSI. The metal salt may also be an iron metal salt. Exemplary (but not limited to) iron metal salts include FeCl3.

[0149] Preferably, the metal salt is lithium bis(trifluoromethane)sulfonylimide (LiTFSI) salt.

[0150] The invention will now be described with reference to the following non-limiting examples.

[0151] Materials and manufacturing technologies

[0152] Material

[0153] Unless otherwise stated, all other materials were purchased from Sigma-Aldrich.

[0154] FTO (TEC7), precursor solutions for c-TiO2 (acetylacetone and diisopropoxide titanium bis(acetylacetone)), Li-TFSI powder, P3HT powder, and all solvents used (IPA, ethanol, DFM, DMSO, chlorobenzene, dichlorobenzene) were purchased from Sigma-Aldrich. 30NR-D paste for m-TiO2 layers, organic salts (methylammonium bromide and) formamidinium iodide and PEAI powder for perovskite solution preparation were purchased from GreatCell Solar. All other compounds used for perovskite solution preparation (PbI2, PbBr2, and CsI) were purchased from TCI. Graphite powder was purchased from Imerys Graphite and Carbon.

[0155] Nanoplate Electrode Ink preparation

[0156] Prepare suitable nanoplate electrode inks according to the process described in US 2018 / 0312404.

[0157] The high viscosity of the paste prevents the flocculation of graphite / graphene nanosheets due to the complex network that forms the metastable colloidal suspension. This can be seen from... Figure 3 As can be seen from the figure, the viscosity of the ink prepared according to the present invention is a function of shear rate.

[0158] Compared to fresh dispersions, the inks produced according to the present invention remain stable for several months and exhibit a negligible decrease in conductivity (the sheet resistance of a 20 μm film is slightly above 5 ohms per square). This can be seen in Figure 4. Figure 4a The sheet resistance of fresh and aged ink-based films is shown as a comparison. Figure 4b The dependence of film resistivity on the number of microfluidization cycles of fresh samples was shown. Although it decreased slightly over time, the film resistivity of aged ink-based films remained significantly lower than that of commercial carbon inks after sintering at 400°C.

[0159] Preferably, the dispersion according to the invention is produced by 10 or more microfluidic cycles, more preferably 15 or more, 20 or more, 30 or more, 40 or more, 50 or more, 60 or more, or 70 or more microfluidic cycles.

[0160] The dispersion prepared according to the present invention can be stored at room temperature for several months. This can be achieved from... Figure 5 As can be seen in the figure, this illustrates the long-term stability of the graphite / graphene nanoplate ink manufactured according to the present invention. The left image shows fresh ink, and the right image shows aged ink.

[0161] Preparation of graphene dispersions for charge transport layer doping

[0162] A small amount (approximately 1 ml) of microfluidized graphene ink was dried overnight at 80°C to ensure complete evaporation of the solvent (IPA). The resulting graphene powder was dispersed in dichlorobenzene (DCB) at a concentration of approximately 2 mg / ml and sonicated in an ultrasonic bath for approximately 1 hour. Once a homogeneous graphene dispersion was obtained, the graphene solution was mixed with poly(3-hexylthiophene-2,5-diyl) (P3HT) powder at varying weight percentage concentrations. Chlorobenzene (CB) was then added to the P3HT:graphene mixture to maintain a constant ratio between the CB and DCB solvents. Finally, the P3HT:graphene mixture in the CB / DCB was sonicated for approximately 30 minutes to ensure proper mixing of the blend.

[0163] A schematic diagram showing the doping of the charge transport layer is shown below. Figure 6 As shown.

[0164] In step b), preferably, the amount of dried ink is at least 100 μl to ensure sufficient quantity during the doping process in 1 ml of P3HT solution. The graphene concentration in the DCB varies: 0.1, 0.3, 0.5, 0.75, 1, 1.5, 2, and 5 mg / ml. Different graphene / P3HT doping ratios were tested, as were different DCB / CB ratios (1, 2.5, 5, 7.5, 10, 15, 20, and 25%). The effect of different doping percentages was investigated using graphene electrodes and P3HT hole transport layers doped with different amounts of graphene. 0% doping resulted in a PV power conversion efficiency (PCE) of 11.5%. Doping the charge transport layer resulted in the following PCE values: 1% and 2% doping improved the PCE to approximately 13% (2% doping was slightly better). 5% doping had a PCE performance of approximately 11.5%. 10% and 15% doping had a PCE of approximately 5%.

[0165] In a preferred embodiment, the charge transport layer is doped with 0.1% to 5% of nanoplate material (e.g., graphene / graphite). Preferably, the charge transport layer is doped with 0.5% to 3%, 0.5% to 2.5%, 1% to 3%, 1% to 2%, 0.5%, 1%, 1.5%, 2%, 2.5%, or 3% of nanoplate material.

[0166] Solar cell manufacturing

[0167] Solar cells were fabricated by patterning a fluorine-doped tin oxide (FTO) glass substrate (Aldrich, 70 hm / sq) using a wet etching process with zinc powder and concentrated hydrochloric acid. The patterned glass / FTO substrate was then ultrasonically cleaned with a detergent containing deionized water, acetone, and isopropanol. A dense TiO2 (c-TiO2) layer was deposited on the glass / FTO substrate preheated to 450 °C via spray pyrolysis. A mesoporous TiO2 (m-TiO2) solution (30NR-D in ethanol) was spin-coated onto the c-TiO2 film, followed by sintering at 450 °C for 30 minutes. m-TiO2 doping was achieved by spin-coating a 0.1 M Li-TFSI acetonitrile solution followed by an additional 30-minute sintering step at 450 °C. See: F. Giordano et al., Nat. Commun. 2016, 7, 10379. After cooling to 150°C, the sample was transferred to a nitrogen-filled glove box, and then a trivalent cationic lead-based mixed halide precursor solution was spin-coated onto the m-TiO2 layer (using a double spin procedure), followed by an antisolvent quenching step with CB.

[0168] Following this, to convert the spin-coated precursor film into perovskite, the sample was placed on a hot plate at 100°C for 60 minutes. (See M. Saliba et al., Energy Environ. Sci. 2016, 9, 1989). After cooling the sample to room temperature, a phenylethyl ammonium iodide solution was spin-coated onto the perovskite film as a thin passivation layer. Subsequently, P3HT (undoped or doped graphene at different wt% concentrations) in a CB / DCB solution was spin-coated onto the PEAI-passivated perovskite film. Finally, the device was completed by coating the P3HT or P3HT:Gr layer with a microfluidized graphite doctor blade. The thickness of the wet-fluidized graphite film was set to 1–1.5 mm, which was then dried to a thickness of approximately 20 μm. The deposition of the paste was achieved in an inert atmosphere, followed by annealing the sample at 80°C for approximately 30 minutes to achieve good interfacial contact between the graphene electrode and the P3HT or P3HT:Gr layer. Unencapsulated devices were characterized under ambient conditions.

[0169] Device characterization

[0170] The device was placed in an area with a single solar radiation intensity (100mW / cm²). 2 The current-voltage profile was measured using a solar simulator (calibrated with a Si reference cell) and a source meter (Keithley, 2400) was used. Stability tests were conducted in a climate chamber (Weiss WKL) under ambient conditions of room temperature or 60°C / 60% relative humidity.

[0171] discuss

[0172] As can be seen, this invention uses highly conductive (Figure 4) and stable ( Figure 5 The ink, which can be cured at room temperature (or preferably, at a low temperature, i.e., 80°C), exhibits significantly lower sheet resistance compared to other similar materials used in PV devices, such as porous carbon black. To test its compatibility with PSC manufacturing, the ink's printability and the final halide perovskite stability were tested together. The final structures at different manufacturing stages are shown below. Figure 7 As shown.

[0173] By applying (printing) this new ink onto a perovskite layer to create a microfluidic graphite layer (approximately 20 μm thick), degradation of the perovskite layer can be avoided. This is because the ink is processed with a perovskite-compatible solvent (isopropanol) when dried in a nitrogen-filled glove box and can be cured at room temperature or low temperature (if desired).

[0174] The room-temperature curing process avoids the degradation of the perovskite active layer, which is sensitive to high-temperature degradation. Therefore, this invention utilizes a conductive ink based on a compatible solvent, allowing the fabrication of semiconductor devices at low temperatures. For example, the devices can be cured at temperatures below 100°C, preferably below 80°C.

[0175] Subsequently, PSCs with a typical mesoscopic architecture were fabricated as described in the text to produce devices with the following architecture: FTO / c-TiO2 / m-TiO2 / perovskite / PEAI / P3HT:Gr / Gr-electrode. Following the above procedure, microfluidic graphite ink was printed onto the sample and then cured at 80°C to complete device fabrication. The fabricated PSCs with graphene-based back electrodes were then exposed to a solar simulator, and characteristic IV curves were obtained to calculate the photovoltaic performance of the device. The results are as follows... Figure 8 As shown, the device achieves an excellent PCE of 13.23%.

[0176] According to the optimization of the semiconductor device of the present invention, a very high PCE is achieved in the PSC, significantly higher than the approximately 11.5% PCE achieved in the prior art. This improvement in PCE is due to the use of the features of the present invention and represents the highest reported PCE to date for a fully printable PSC.

[0177] The present invention also significantly reduces costs due to the printable conditions used in manufacturing. This allows for the fabrication of devices according to the invention using cost-effective and scalable processes. For example, considering PSC (Power Slot Capacity), reduced manufacturing costs ensure that the devices are cost-effective in terms of energy production.

[0178] In addition to advantageous performance and product cost, devices according to the invention were tested to determine their robustness. Devices according to the invention (having an FTO / c-TiO2 / m-TiO2 / perovskite / PEAI / spiral-Ometad / Au architecture) were tested for devices including gold electrodes and without graphene-doped hole transport layers. Results are as follows... Figure 9 As shown, stability testing of the PSC is illustrated. A device according to the invention, comprising a 2% graphene-doped P3HT hole injection layer and a graphene back electrode fabricated according to the invention, was tested against a similar device comprising a helical-OMe TAD (with Li doping) / Au device. It is clearly evident that the device according to the invention is significantly more stable under stress testing at 60°C / 60% relative humidity compared to the device with a gold electrode. It is also evident that even under these conditions, the device according to the invention outperforms standard PSCs of the prior art (e.g., see Domanski et al., ACS Nano, 2016, 10, 6306-6314).

[0179] It is important to note that the fabrication of the device according to the present invention does not involve any encapsulation process to prevent oxygen / moisture diffusion within the device. However, it is not desirable to be bound by theory; a thick graphene paste-like substrate can serve as an encapsulation.

[0180] In another experiment, PCE was evaluated using the device according to the invention (P3HT:Gr / Gr) against the same device but using an Au back electrode (P3HT:Gr / Au). The results are as follows... Figure 10 As shown, devices with microfluidic graphite exhibit significantly higher photovoltaic efficiency compared to gold devices.

[0181] In another experiment, the stability of the device according to the invention was further evaluated. Figure 11 The device according to the invention was shown to exhibit no degradation during stability testing (D1 ISOS protocol, self-degradation) for over 400 hours. In fact, its efficiency appears to be improving.

[0182] In summary, this invention identifies semiconductor devices with improved performance. Improved performance can increase efficiency. Improved performance can increase stability. This invention also identifies semiconductor device manufacturing processes that reduce production costs.

[0183] This invention avoids the need for conventionally deposited metal electrodes while maintaining sufficient performance levels. The use of printable electrodes improves device scalability and can significantly increase production speed, for example, by avoiding the thermal evaporation process required for metal-based electrodes. By utilizing this invention, commercially attractive efficiency and cost-effective printable electrode-based devices can be fabricated.

[0184] The devices in this invention can be used, for example, in PSCs, including perovskite single-junction and tandem solar cells.

[0185] This invention simplifies the manufacturing complexity of material preparation (fewer material production steps) and provides a low-cost, low-temperature curable, and highly conductive electrode material.

[0186] Including interlayer

[0187] The semiconductor device according to the invention may include an interlayer between the first electrode and the first charge transport layer. A non-limiting example of a semiconductor device according to the invention comprising a graphene interlayer will now be described.

[0188] Graphene interlayer ink formation

[0189] The graphene interlayer ink was prepared using the same ink used for the aforementioned counter electrode. In the first step, a fixed amount of microfluidized graphene ink was dried overnight at 80°C. Afterward, the dried graphene nanoplate powder was dispersed in isopropanol (IPA) at a concentration of 1 mg / ml. Finally, the dispersion was sonicated for approximately 15 minutes until the graphene nanoplate powder was well dispersed, thus forming a stable ink (see [link to original text]). Figure 12 ).

[0190] have Manufacturing of interlayer solar cells

[0191] The heterostructure sub-cell is fabricated based on the steps described above up to the formation of the P3HT or P3HT:Gr layer (see: Solar Cell Fabrication). However, after the formation of the P3HT or P3HT:Gr layer, a graphene interlayer film is prepared by depositing (spin-coating) the prepared ink on the P3HT:graphene hybrid HTL film at a speed of 3000 rpm. The device is then completed by coating the graphene interlayer with microfluidic graphene ink using a doctor blade. Figure 13 a, 13b, and 13c show the front view, back view, and front schematic diagram of the device, respectively.

[0192] The thickness of the wet-processed microfluidic graphene nanoplate film was set to approximately 0.5 mm, which was transformed into a film of approximately 10 μm thickness after the drying process. The deposition of the paste was achieved under ambient conditions, followed by the transfer of the device to an oven for drying at 80°C for approximately half an hour. The unencapsulated device was then placed in the drying oven overnight.

[0193] discuss

[0194] The characterization of these devices is as described above (see: Characterization of Devices).

[0195] Figure 14 a shows a schematic diagram of an example of an interlayer-free device manufactured according to the aforementioned manufacturing method (see: Solar Cell Manufacturing). Figure 14 b shows a schematic diagram of an example device having an interlayer layer of about 10 nm thick, manufactured according to the method for manufacturing solar cells with interlayer layers.

[0196] As can be seen, compared to devices without an interlayer (graphene counter electrode thickness approximately 25 μm), this invention comprises a thin (approximately 10 nm) graphene interlayer film (deposited between the counter electrode and the hole transport layer) and has a much thinner (approximately 10 μm thick) graphene counter electrode. This can be attributed to the graphene interlayer film acting as a bridge / scaffold for optimal graphene counter electrode deposition. Devices with a thin graphene interlayer and approximately 10 μm thick graphene counter electrodes exhibit an improved fill factor (>64%) compared to devices without an interlayer (63%). Devices with an interlayer and approximately 10 μm thick graphene counter electrodes achieve a PCE >13% (see [link to documentation]). Figure 15 The characteristic IV curve ("before LiTFSI fabrication") is similar to that of a device with a graphene counter electrode of approximately 25 μm thickness. Therefore, by including a graphene interlayer film, the amount of graphene counter electrode ink required is reduced by more than 2 times while maintaining a high PCE.

[0197] Therefore, by including a thin graphene interlayer film, the present invention can achieve a significant reduction in the materials required to produce graphene electrodes.

[0198] Post-manufacturing processing

[0199] Further improvements to the performance of the semiconductor device according to the present invention can be achieved by post-manufacturing processing of the device with metal salts. It is not desirable to be bound by theory, but such processing can significantly improve the interfacial contact between the first electrode and the first interlayer or first charge transport layer. Post-manufacturing processing with metal salts can reduce the gaps between the layers of the device.

[0200] Metal salts can be deposited on devices through solution treatment or thermal evaporation.

[0201] It should be understood that depositing salt onto the finished device after device fabrication is different from applying salt to each layer of the device during fabrication. It should also be understood that post-fabrication treatment using metal salts can improve devices with or without interlayer layers.

[0202] Post-manufacturing processing may include depositing a solution comprising a metal salt onto the first electrode. It is undesirable to be bound by theory to ensure that the solution does not penetrate the device further than the interface between the first electrode and the first interlayer or first charge transport layer.

[0203] In a non-limiting example, a post-manufacturing treatment with LiTFSI salt is performed on a solar cell having an interlayer layer as described above (see: Manufacture of a solar cell having an interlayer layer).

[0204] Follow these steps to illustrate Figure 14Figure c shows that, without encapsulation, after being placed in a drying oven overnight and characterizing the initial IV, the device was placed in a nitrogen-filled glove box, and a 20 mM LiTFSI (Sigma-Aldrich) acetonitrile (ACN) solution was spin-cast / permeated onto the graphene counter electrode at 3000 rpm. The device was then stored in a drying oven overnight again. Finally, the LiTFSI-treated device was tested using the exact same experimental conditions as before treatment.

[0205] Figure 15 The diagram shows a comparison of the IV curves obtained before and after the post-fabrication LiTFSI treatment. It can be seen that the absolute value of the device efficiency after post-fabrication treatment is reproducibly improved by 3%, equivalent to a 21% improvement in PCE compared to the pre-treatment PCE.

[0206] Summary of various photovoltaic parameters (short-circuit current, IT) of different devices fabricated and tested in the non-limiting embodiments described herein. SC Open circuit voltage, V OC (FF; PCE) are provided in Table 1.

[0207] Table 1. Summary of photovoltaic parameters for different devices

[0208] Devices <![CDATA[I SC (mA / cm 2 )]]> <![CDATA[V OC (V)]]> FF (%) PCE (%) %ΔPCE No interlayer 23.00 0.911 63.07 13.21 - Interlayer 22.46 0.914 64.15 13.17 - Interlayer + LiTFSI treatment 23.46 0.963 70.44 15.93 +20.9

[0209] After LiTFSI treatment, all photovoltaic parameters of the device manufactured according to the present invention increase, wherein, compared to the same device before LiTFSI treatment, I SC V OC Both FF and FF reached approximately 23.5 mA / cm. 2 (4.5% increase), approximately 0.96V (5.5% increase), and approximately 70.4% (approximately 10% increase) (see Table 1). The maximum efficiency of the device manufactured according to the invention is approximately 16%, which is one of the highest (if not the highest) ever reported for any monolithic integrated fully printed PSC with HTL.

[0210] Figure 16 Figure a shows a comparison of the measured photovoltage response versus light intensity of the devices before and after post-fabrication LiTFSI treatment. An increase in photovoltage was observed in the LiTFSI-treated devices at different light intensities, and the ideality factor of each solar cell was improved after post-fabrication LiTFSI treatment (approximately 1.6 for the LiTFSI-treated cells, compared to approximately 2 for the untreated cells). Without being bound by theory, this may indicate a reduction in trap-assisted recombination at the interfaces. Specifically, trap-assisted recombination can be reduced at the interface between the perovskite active layer and the first charge transport layer, and at the interface between the first charge transport layer and the interlayer and / or the first electrode.

[0211] Figure 16 b shows the higher photovoltage and faster rise of the photovoltage in the device treated with LiTFSI solution. This could indicate faster charge carrier extraction at the corresponding selective contacts. Figure 16 c shows that the LiTFSI-treated device exhibits slower photovoltage decay (longer lifetime), which may further indicate reduced recombination and increased carrier lifetime at the interface.

[0212] Without being bound by theory, the reduced recombination and faster charge carrier extraction observed at interfaces in devices fabricated according to the present invention are likely due to improved interfacial contacts between the layers of the device. For example, post-fabrication processing using LiTFS can reduce the presence of interlayer gaps at a given interface.

[0213] Further experiments on devices with different interface designs demonstrate that post-fabrication LiTFSI treatment is generally applicable to improving any fully printable solar cell structure with printable counter electrodes according to the present invention.

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[0233] 19 Tingwei He,Saisai Li,Yuanzhi Jiang,Chaochao Qin,Minghuan Cui,LuQiao,Hongyu Xu,Jien Yang,Run Long,Huanhua Wang&Mingjian Yuan,NATURECOMMUNICATIONS|(2020)11:1672|https: / / doi.org / 10.1038 / s41467-020-15451-1。

[0234] 20 Zhang et al ACS Appl.Mater.Interfaces 2020,12,30,33751-33758。

Claims

1. A semiconductor device, comprising: The first electrode includes a conductive material, wherein the conductive material is graphene or graphite ink deposited by ink deposition, or wherein the conductive material includes CVD-grown graphene. A first charge transport layer, wherein the first charge transport layer is doped with 0.1% to 3% of the conductive material of the first electrode; Perovskite active layer; Second charge transport layer; as well as Second electrode.

2. The semiconductor device according to claim 1, further comprising: An interlayer is located between the first electrode and the first charge transport layer.

3. The semiconductor device according to claim 2, wherein, The interlayer includes: a conductive material or an ultrathin insulating film.

4. The semiconductor device according to claim 3, wherein, The first electrode and the interlayer comprise the same conductive material.

5. The semiconductor device according to claim 2, wherein, The thickness of the interlayer is between 2 nm and 50 nm.

6. The semiconductor device according to claim 2, wherein, The interlayer is deposited by printable conductive ink, which includes conductive materials and solvents.

7. The semiconductor device according to claim 1, wherein, The first electrode is a first nanoplate electrode, which comprises graphite and / or graphene nanoplates.

8. The semiconductor device according to claim 1, wherein, The first charge transport layer is an organic semiconductor material.

9. The semiconductor device according to claim 1, wherein, The first charge transport layer is a hole transport organic semiconductor material selected from the group consisting of: PEDOT:PSS, PANI (polyaniline) and polypyrrole.

10. The semiconductor device according to claim 1, wherein, The first charge transport layer is selected from poly(triarylamine); copper thiocyanate (CuSCN); benzodithiophene (BDT) based polymer; poly(p-phenylene)PPP; lead phthalocyanine (PbPc); poly(9,9-dioctylfluorene-co-N-(4-(3-methylpropyl))diphenylamine (TFB); polythiophene (PT); poly(4,4'-bis(N-carbazolyl)-1,1'-biphenyl) (PPN); nickel oxide (NiO); copper iodide (CuI); CuInS2; Li 0.05 Mg 0.15 Ni 0.8 O; Screw-OMeTAD; FDT; or PCP-TPA.

11. The semiconductor device according to claim 1, wherein, The first charge transport layer is a hole transport organic semiconductor material, which is selected from the group consisting of polyfluorene, spiro-OMeTAD, polycarbazole, 4,4'-bis(N-carbazolyl)-1,1'-biphenyl, 4,4'-bis(N-carbazolyl)-1,1'-biphenyl, poly(3-hexylthiophene-2,5-diacyl) (P3HT), or poly[(4,4'-bis(2-butyloctyloxycarbonyl-[2,2'-dithiophene]-5,5-diacyl)-alt-(2,2'-dithiophene-5,5'-diacyl) (PDCBT).

12. The semiconductor device according to claim 1, wherein, The first charge transport layer is an electron transport organic semiconductor material, which includes polyfluorene.

13. The semiconductor device according to claim 1, wherein, The first charge transport layer is doped with 0.5% to 3% of the conductive material.

14. The semiconductor device according to claim 1, wherein, The perovskite is a halide perovskite.

15. The semiconductor device according to claim 1, wherein, The perovskite is a 3D perovskite, a 2D perovskite, a 1D perovskite, and / or a quasi-2D perovskite.

16. The semiconductor device according to claim 1, wherein, The perovskite is an organometal halide perovskite, an inorganic metal halide perovskite, or a mixed organo-inorganic metal halide perovskite material.

17. The semiconductor device according to claim 16, wherein, The metal halide perovskite has an AMX3 structure, where A is a monovalent cation, M is a divalent cation, and X is a halide anion.

18. The semiconductor device according to claim 17, wherein, A could be: Monovalent organic cations or monovalent metal cations; Having A 1-i B i A binary cation with a structure in which A and B are different and are both monovalent organic cations or monovalent metal cations, and i is between 0 and 1; Having A α B β C γ A ternary cation with a structure in which A, B, and C are different and each is a monovalent organic cation or a monovalent metal cation, and the combination of α, β, and γ equals 1; or Having A α B β C γ D δ The structure is a quaternary cation in which A, B, C and D are all monovalent organic cations or monovalent metal cations, wherein A, B, C and D are different, and the combination of α, β, γ and δ is equal to 1.

19. The semiconductor device according to claim 17, wherein, M can be: Divalent cations; With structure M 1-j N j Where M and N are both divalent metal cations, and j is between 0 and 1; or With structure M ε N ζ O η Where M, N and O are all divalent metal cations, M, N and O are different, and the combination of ε, ζ and η is equal to 1.

20. The semiconductor device according to claim 17, wherein, X3 could be: Halogen anions; Having structure X 3-k Y k Where X and Y are both halide anions, X and Y are different, and k is between 0 and 3; or Having structure X α Y β Z γ Where X, Y and Z are all halide anions, X, Y and Z are different, and the combination of α, β and γ equals 1.

21. The semiconductor device according to claim 17, having a structure selected from the following: 。 22. The semiconductor device according to claim 17, wherein, The monovalent cation is an alkali metal cation.

23. The semiconductor device according to claim 22, wherein, The alkali metal cation is selected from cesium (Cs). + ), Rubidium (Rb + ) and / or potassium (K + ).

24. The semiconductor device according to claim 17, wherein, The monovalent cation is a primary, secondary, or tertiary ammonium cation [HNR] 1 R 2 R 3 ] + , where R 1 R 2 and R 3 Each of them is the same or different and is selected from hydrogen, unsubstituted or substituted C1-C. 20 Alkyl groups, and unsubstituted or substituted C5-C 18 Aryl.

25. The semiconductor device according to claim 17, wherein, The monovalent cation has the form [R] 1 R 2 N-CH=NR 3 R 4 ] + : ， Wherein, the R 1 R 2 R 3 and R 4 Each of them is the same or different and is selected from hydrogen, unsubstituted or substituted C1-C. 20 Alkyl groups, and unsubstituted or substituted C5-C 18 Aryl.

26. The semiconductor device according to claim 17, wherein, The monovalent cation has the form (R) 1 R 2 N)(R 3 R 4 N)C=NR 5 R 6 : ， Among them, R 1 R 2 R 3 R 4 R 5 and R 6 Each of them is the same or different and is selected from hydrogen, unsubstituted or substituted C1-C. 20 Alkyl groups, and unsubstituted or substituted C5-C 18 Aryl.

27. The semiconductor device according to claim 17, wherein, The divalent cation M is a divalent metal cation.

28. The semiconductor device according to claim 27, wherein, The divalent metal cation is Sn. 2+ Pb 2+ Co 2+ and / or Zn 2+ .

29. The semiconductor device according to claim 17, wherein, X is one or more halide anions selected from chlorides, bromides, iodides, and fluorides, and in the AMX3 structure, each halogen is the same or different.

30. The semiconductor device according to claim 29, wherein, The halogen anion is a bromide ion or includes bromide ions.

31. The semiconductor device according to claim 1, wherein, The second charge transport layer is an organic semiconductor material.

32. The semiconductor device according to claim 1, wherein, The second charge transport layer is an electron transport material, which includes TiO2; ZnO; SnO2; ZrO2; SrTiO3; or WO3, or PCBM: polystyrene; PCBM: PMMA; PEHT; or polyethyleneimine (PEI); PCBM.

33. The semiconductor device according to claim 1, wherein, The second charge transport layer is an electron transport inorganic semiconductor material selected from the group consisting of: titanium dioxide (TiO2), zinc oxide (ZnO), zinc magnesium oxide (MgZnO), and aluminum-doped zinc oxide (AZO).

34. The semiconductor device according to claim 1, wherein, The second electrode is formed of a transparent conductive material.

35. The semiconductor device according to claim 34, wherein, The second electrode is selected from: indium tin oxide (ITO), fluorine-doped tin oxide (FTO), indium zinc oxide, graphene, carbon nanotubes, silver nanowires and / or metals with a thickness up to 150 nm.

36. The semiconductor device of claim 1, comprising a first insulating layer.

37. The semiconductor device of claim 1, comprising a second insulating layer.

38. The semiconductor device according to claim 36 or 37, wherein, The insulating layer is formed of an insulating polymer selected from the group consisting of poly(ethyleneimine) (PEI), ethoxylated polyethyleneimine (PEIE), polystyrene (PS), polymethyl methacrylate (PMMA), phenylethyl ammonium iodide (PEAI), guanidine iodide (GuI), guanidine bromide (GuBr), n-butyl ammonium iodide (BAI), n-butyl ammonium bromide (n-BABr), and ethylenediamine diiodide (EDAI2).

39. The semiconductor device according to claim 36 or 37, wherein, The insulating layer is formed of an oxide or nitride selected from the group consisting of aluminum oxide, silicon dioxide, silicon nitride, zinc oxide modified with aluminum oxide, nickel oxide, or magnesium oxide.

40. The semiconductor device according to claim 36 or 37, wherein, The insulating layer has a thickness of less than 30 nm.

41. The semiconductor device according to claim 36 or 37, wherein, The insulating layer is deposited by atomic layer deposition, spin coating, or thermal evaporation.

42. The semiconductor device according to claim 1, wherein, One or more metal salts with electron-accepting properties are present at one or more interfaces between the layers of the semiconductor device.

43. The semiconductor device according to claim 1, wherein, One or more metal salts with electron-accepting properties are present at the interface between the first charge transport layer and the layer in the semiconductor device adjacent to the first charge transport layer.

44. The semiconductor device according to claim 1, wherein, One or more metal salts with electron-accepting properties are present at the interface between the first electrode and the layer in the semiconductor device adjacent to the first electrode.

45. The semiconductor device according to claim 1, wherein, One or more metal salts with electron-accepting properties are present at the interface between the first electrode and the first charge transport layer.

46. ​​The semiconductor device according to claim 2, wherein, One or more metal salts with electron-accepting properties are present at the interface between the first electrode and the interlayer.

47. The semiconductor device according to any one of claims 42 to 46, wherein, The metal salt can be used to improve interfacial contact between layers of the semiconductor device.

48. The semiconductor device according to any one of claims 42 to 46, wherein, The metal salt is a lithium metal salt.

49. The semiconductor device according to any one of claims 42 to 46, wherein, The metal salt is a cobalt metal salt.

50. The semiconductor device according to any one of claims 42 to 46, wherein, The metal salt is a copper metal salt.

51. The semiconductor device according to any one of claims 42 to 46, wherein, The metal salt is a silver metal salt.

52. The semiconductor device according to any one of claims 42 to 46, wherein, The metal salt is an iron metal salt.

53. The semiconductor device according to claim 48, wherein, The metal salt is lithium bis(trifluoromethane)sulfonylimide (LiTFSI) salt.

54. A semiconductor device, comprising: The first nanoplate electrode includes graphene or graphite nanoplates; A first charge transport layer, wherein the first charge transport layer is doped with 0.1% to 3% graphene or graphite nanoplates; an insulating layer; and a perovskite active layer.

55. A method of manufacturing a semiconductor device, the semiconductor device comprising a first electrode made of a rechargeable material and an adjacent charge transport layer, the method comprising doping the adjacent charge transport layer with 0.1% to 3% of the same rechargeable material in the first electrode, wherein the rechargeable material is graphene or graphite.

56. The method of claim 55, further comprising applying one or more metal salts as described in claim 45 or 46 to the surface of the first electrode.

57. A solar cell comprising a semiconductor device according to any one of claims 1 to 56.

58. A light-emitting device comprising a semiconductor device according to any one of claims 1 to 56.

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