Capacitance measuring device and capacitance measuring method

Abstract

A capacitance measuring device and capacitance measuring method are configured to batch test the capacitance parameters of chips. The capacitance measuring device includes: a measurement circuit board, including: a test station configured to install the chip to be tested; and a reference capacitor, wherein a first end of the reference capacitor is electrically connected to a first pin of the chip to be tested installed at the test station at a first node, a second end of the reference capacitor is configured to receive a first measurement signal, and a second pin of the chip to be tested installed at the test station is configured to receive a second measurement signal; and an automatic tester is electrically connected to the measurement circuit board and configured to provide the first measurement signal and the second measurement signal, and determine the capacitance parameters of the chip to be tested based on the signal at the first node, wherein the first measurement signal and the second measurement signal are both sine signals or cosine signals, and the phase difference between the first measurement signal and the second measurement signal is (2n+1)π, where n is an integer.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit testing, and in particular to a capacitance measuring device and a capacitance measuring method, and more particularly to a capacitance measuring device and a capacitance measuring method for measuring capacitance parameters of batch chips. Background Art

[0002] A capacitor, often referred to as a capacitor and typically denoted by the letter C, is a component that stores electrical energy. The unit of capacitance C is farad, denoted by the letter "F," or "F." A capacitor presents a low impedance to AC signals, acting as a path, but a high impedance to DC signals, acting as a disconnect. Capacitors are widely used in circuit systems, such as chips. During chip testing, the capacitance parameters of many chips also need to be measured. Summary of the Invention

[0003] Some embodiments of the present disclosure provide a capacitance measuring device configured to batch test capacitance parameters of chips, the capacitance measuring device comprising:

[0004] Measurement board, including:

[0005] A test station configured to install the chip to be tested; and

[0006] a reference capacitor, wherein a first end of the reference capacitor is electrically connected to a first pin of a chip under test installed at the test station at a first node, a second end of the reference capacitor is configured to receive a first measurement signal, and a second pin of the chip under test installed at the test station is configured to receive a second measurement signal, and

[0007] an automatic tester, electrically connected to the measurement circuit board, configured to provide the first measurement signal and the second measurement signal, and determine the capacitance parameter of the chip to be tested based on the signal at the first node,

[0008] The first measurement signal and the second measurement signal are both sine signals or cosine signals, and the phase difference between the first measurement signal and the second measurement signal is (2n+1)π, where n is an integer.

[0009] In some embodiments, the measurement circuit board further comprises:

[0010] an amplifier circuit, electrically connected to the first node, configured to receive a signal from the first node and output an amplified signal,

[0011] The automatic testing machine is electrically connected to the measuring circuit board and is configured to receive and detect the amplified signal and determine the capacitance parameter of the chip to be tested based on the amplified signal.

[0012] In some embodiments, the amplitude of at least one of the first measurement signal and the second measurement signal is adjustable, and the capacitance parameter of the chip under test installed at the test station is determined by adjusting the amplitude of at least one of the first measurement signal and the second measurement signal until the amplified signal is less than or equal to a first threshold. The capacitance parameter C of the chip under test is determined by the following formula:

[0013] C=C ref V2 / V1

[0014] Among them, C ref represents the capacitance parameter of the reference capacitor, V1 represents the amplitude of the first measurement signal, and V2 represents the amplitude of the second measurement signal.

[0015] In some embodiments, the amplification circuit includes an operational amplifier, which includes a non-inverting input terminal, a reverse input terminal, and an output terminal. The non-inverting input terminal is electrically connected to the first node, the reverse input terminal is electrically connected to a reference voltage via a first resistor, and the output terminal is electrically connected to the reverse input terminal via a second resistor.

[0016] In some embodiments, the amplification circuit includes an operational amplifier, which includes a non-inverting input terminal, a reverse input terminal, and an output terminal. The non-inverting input terminal is electrically connected to a reference voltage, the reverse input terminal is electrically connected to the first node via a third resistor, and the output terminal is electrically connected to the reverse input terminal via a fourth resistor.

[0017] In some embodiments, the capacitance measuring device further comprises:

[0018] A robot is configured to install the chip to be tested on the test station or remove it from the test station.

[0019] In some embodiments, the reference capacitor is an adjustable capacitor.

[0020] In some embodiments, the number of the test stations is 1 or more.

[0021] Some embodiments of the present disclosure provide a capacitance measurement method, using the capacitance measurement device described in the preceding claims, the capacitance measurement method comprising:

[0022] Using the automatic testing machine to simultaneously provide a first measurement signal and a second measurement signal to the reference capacitor and the chip to be tested installed at the testing station, respectively;

[0023] adjusting the amplitude of at least one of the first measurement signal and the second measurement signal until the signal at the first node is substantially zero; and

[0024] The capacitance parameter of the chip to be tested is determined based on the capacitance parameter of the reference capacitor, the amplitudes of the first measurement signal and the second measurement signal.

[0025] In some embodiments, before using the automatic tester to simultaneously provide the first measurement signal and the second measurement signal to the reference capacitor and the chip under test installed at the test station, respectively, the capacitance measurement method further includes:

[0026] The chip to be tested is installed on the testing station by using a robot.

[0027] Compared with the related art, the above solution of the embodiment of the present disclosure has at least the following beneficial effects:

[0028] Using an automatic tester and a specially designed measurement circuit board to batch test the capacitance parameters of chips can conveniently and accurately measure the capacitance parameters of chips and improve batch testing efficiency.

[0029] An amplifier circuit is provided on the measurement circuit board to improve measurement accuracy.

[0030] A robot is used to install and remove the chip to be tested at the test station to improve test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0032] Figure 1 A schematic structural diagram of a wafer provided in some embodiments of the present disclosure;

[0033] Figure 2 A circuit diagram of a test circuit on a measurement circuit board provided for some embodiments of the present disclosure;

[0034] Figure 3 A circuit diagram of a test circuit on a measurement circuit board provided for some embodiments of the present disclosure;

[0035] Figure 4 A circuit diagram of a test circuit on a measurement circuit board provided for some embodiments of the present disclosure;

[0036] Figure 5 A circuit diagram of a test circuit on a measurement circuit board provided for some embodiments of the present disclosure;

[0037] Figure 6A schematic structural diagram of a measurement circuit board provided in some embodiments of the present disclosure;

[0038] Figure 7 A flowchart of a capacitance measurement method provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0039] To make the objectives, technical solutions, and advantages of the present disclosure more clear, the present disclosure will be further described in detail below with reference to the accompanying drawings. It is apparent that the embodiments described are only a portion of the embodiments of the present disclosure, rather than all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present disclosure without creative effort are intended to fall within the scope of protection of the present disclosure.

[0040] The terms used in the embodiments of the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. The singular forms "a," "an," "the," and "the" used in the embodiments of the present disclosure and the appended claims are also intended to include plural forms, and unless the context clearly indicates otherwise, "a plurality" generally includes at least two.

[0041] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0042] It should be understood that although the terms first, second, third, etc. may be used to describe in the embodiments of the present disclosure, these should not be limited to these terms. These terms are only used to distinguish. For example, the first can also be referred to as the second, and similarly, the second can also be referred to as the first without departing from the scope of the embodiments of the present disclosure.

[0043] It should also be noted that the terms "include," "comprises," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a product or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such product or device. In the absence of further limitations, an element defined by the phrase "comprising a" does not exclude the presence of other identical elements in the product or device comprising the element.

[0044] In the related art, a multimeter, an LCR tester or a network analyzer is usually used to measure the capacitance parameters of the chip. Specifically, when using a multimeter or an LCR tester to measure the capacitance parameters of the chip, turn the multimeter function rotary switch to the capacitance (C) measurement position or set the LCR tester to capacitance (C) measurement, and select the appropriate range. Connect the pins of the corresponding capacitor of the chip to be tested to the multimeter or LCR tester, and then directly read the capacitance value on the screen. When using a network analyzer to measure the capacitance parameters of the chip, first connect the pins of the corresponding capacitor of the chip to be tested to the network analyzer, then calibrate the measurement path, and use the two-port test method to measure the S parameters of the corresponding capacitor of the chip to be tested. Through the S parameters, the capacitance value is calculated.

[0045] The above methods all require manual operation by the operator, which is not conducive to batch testing of chips. In addition, since there may be human factors deviation when the operator performs the capacitance test, such as loose connection between the chip pins and the measuring instrument, the above measurement methods have low test efficiency and poor measurement accuracy.

[0046] In order to overcome the above problems, the present disclosure provides a capacitance measuring device configured to batch test the capacitance parameters of chips, the capacitance measuring device comprising: a measurement circuit board, comprising: a test station configured to install the chip to be tested; and a reference capacitor, the first end of the reference capacitor being electrically connected to the first pin of the chip to be tested installed at the test station at a first node, the second end of the reference capacitor being configured to receive a first measurement signal, the second pin of the chip to be tested installed at the test station being configured to receive a second measurement signal, and an automatic tester being electrically connected to the measurement circuit board, configured to provide the first measurement signal and the second measurement signal and determine the capacitance parameters of the chip to be tested based on the signal at the first node, wherein the first measurement signal and the second measurement signal are both sine signals or cosine signals, and the phase difference between the first measurement signal and the second measurement signal is (2n+1)π, where n is an integer.

[0047] The present disclosure adopts an automatic testing machine and a specially designed measuring circuit board to batch test the capacitance parameters of chips, which can conveniently and accurately measure the capacitance parameters of chips and improve the efficiency of batch testing.

[0048] Optional embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0049] Figure 1 A schematic diagram of the structure of a capacitance measuring device provided in some embodiments of the present disclosure is shown. Figure 2 A circuit diagram of a test circuit on a measurement circuit board provided for some embodiments of the present disclosure.

[0050] like Figure 1 and Figure 2As shown, some embodiments of the present disclosure provide a capacitance measuring device configured to batch test capacitance parameters of chips. The capacitance measuring device 100 includes an automatic tester 10 and a measurement circuit board 20 disposed on the automatic tester 10 .

[0051] Test system 100 includes an automatic test equipment (ATE) 10, such as an integrated circuit (IC) automatic tester. The ATE is used to test the performance and functionality of integrated circuits, such as chips. Multiple connectors are provided on the top surface of the ATE for connecting to a test circuit board 20 and providing tester resources, namely, various signals, to the test circuit board.

[0052] The measuring circuit board 20 is arranged on the top surface of the automatic test machine 10 and is connected to the automatic test machine. It is used to receive resources from the automatic test machine to test the integrated circuit to be tested, such as a chip. The measuring circuit board 20 is, for example, a PCB board. In some embodiments, the automatic test machine 10 may further include a reinforcing plate 40 to support and fix the measuring circuit board 20, so that the overall strength of the measuring circuit board 20 is enhanced and it is not easy to deform. Figure 1 As shown, the reinforcement board 40 is located between the measurement circuit board 20 and the automatic tester 10 when performing integrated circuit testing.

[0053] A test station 22 is provided on a side of the measurement circuit board 20 away from the automatic test machine 10 . The test station 22 includes, for example, a fixture for fixing and connecting the chip to be tested 30 . The fixture has an interface for connecting the chip to be tested 30 .

[0054] The test circuit board 20 includes a substrate 21 and a test station 22 disposed on the substrate. The test station 22 is, for example, disposed on a side of the substrate 21 away from the automatic tester 10. The test station 21 is used to mount a chip under test 30. When the chip under test 30 is loaded into the test station 21, the chip under test 30 is connected to the test circuit on the test circuit board 20. In some embodiments, the test circuit can be disposed on a side of the test circuit board 20 that is closer to the automatic tester 10.

[0055] The test circuit includes a reference capacitor C refThe first end of the reference capacitor is connected to the first end of the equivalent capacitor C of the chip under test 30 installed in the test station 22 at a first node, that is, the first end of the reference capacitor is electrically connected to the first pin of the chip under test 30 installed in the test station at a first node A, and the second end of the reference capacitor is configured to receive a first measurement signal IS1. The second end of the equivalent capacitor C of the chip under test 30 installed in the test station 22, that is, the second pin of the chip under test 30 installed in the test station, is configured to receive a second measurement signal IS2. The first measurement signal IS1 and the second measurement signal IS2 are both sine signals or cosine signals, and the phase difference between the first measurement signal IS1 and the second measurement signal IS2 is (2n+1)π, where n is an integer.

[0056] The automatic tester 10 is electrically connected to the measurement circuit board 20 and is configured to provide the first measurement signal IS1 and the second measurement signal IS2 and determine the capacitance parameter C of the chip under test 30 based on the signal at the first node A. In the present disclosure, C represents both the equivalent capacitance of the chip under test 30 installed in the test station 22 and the capacitance parameter of the chip under test 30 installed in the test station 22. C ref It represents both the reference capacitance and the capacitance parameter of the reference capacitance.

[0057] The capacitance parameters of the chip are batch tested using the automatic test machine and the specially designed measurement circuit board as described above, which can conveniently and accurately measure the capacitance parameters of the chip and improve the efficiency of batch testing. Specifically, the first measurement signal IS1 and the second measurement signal IS2 are both sinusoidal signals or cosine signals, and the phase difference between the two is, for example, π. The first measurement signal IS1 and the second measurement signal IS2 have the same period and opposite signs. And the amplitude of at least one of the first measurement signal IS1 and the second measurement signal IS2 is adjustable. By adjusting the amplitude of at least one of the first measurement signal IS1 and the second measurement signal IS2 so that the signal at the first node A is substantially 0, the capacitance parameter C of the chip to be tested 30 can be determined. The capacitance parameter C of the chip to be tested is determined by the following formula:

[0058] C=C ref V2 / V1

[0059] Among them, C ref represents the capacitance parameter of the reference capacitor, V1 represents the amplitude of the first measurement signal, and V2 represents the amplitude of the second measurement signal, where C ref It is known that V1 and V2 are determined by the automatic test machine 10 and are also known.

[0060] Figure 3 A circuit diagram of a test circuit on a measurement circuit board provided in some embodiments of the present disclosure. Figure 2The test circuits on the measurement circuit board shown in FIG are substantially the same, except that the measurement circuit board 20 further includes an amplifier circuit 23. The amplifier circuit 23 is electrically connected to the first node A and configured to receive and amplify the signal at the first node A to output an amplified signal AS. In these embodiments, the automatic tester 10 is electrically connected to the measurement circuit board 20 and configured to receive and detect the amplified signal AS and determine the capacitance parameter C of the chip under test 30 based on the amplified signal AS.

[0061] exist Figure 2 In the test circuit shown, directly measuring whether the signal at the first node A is substantially zero may not be very accurate. In actual testing, the measured amplitude of the signal at the first node A may usually be less than or equal to a predetermined value, such as 100mV, and then the signal at the first node A is deemed to be substantially zero.

[0062] And in Figure 3 In the test circuit shown, an amplifier circuit is added to amplify the signal at the first node A, for example, by amplifying it 100 times. Using the amplified signal AS to perform detection can further improve measurement accuracy. Specifically, the amplitude of at least one of the first measurement signal IS1 and the second measurement signal IS2 is adjustable. By adjusting the amplitude of at least one of the first measurement signal IS1 and the second measurement signal IS2 until the amplified signal AS is less than or equal to a first threshold, the capacitance parameter of the chip under test 30 installed in the test station can be determined.

[0063] In actual testing, the signal at first node A is typically considered to be substantially zero when the measured amplitude of the amplified signal AS is less than or equal to a predetermined value, namely, a first threshold value M, for example, 100 mV. In this case, the amplitude of the signal at first node A is M / n, where n is the amplification factor of the amplifier circuit and M is the first threshold value. For example, if the first threshold value M is 100 mV and the amplification factor of the amplifier circuit is 100, the maximum amplitude of the signal at first node A is 1 mV. Using these embodiments, the signal at first node A is closer to zero, resulting in higher test accuracy.

[0064] In some embodiments, the amplitudes of the first measurement signal IS1 and the second measurement signal IS2 input at the start of measurement may be the same or different. The amplitude of one of the first measurement signal IS1 and the second measurement signal IS2 may be adjustable, while the amplitude of the other may be fixed, or both amplitudes may be adjustable.

[0065] For example, at the beginning of the measurement, the first measurement signal IS1 and the second measurement signal IS2 have the same amplitude but opposite signs, are both sine signals or cosine signals, and have a phase difference of π. Then, the signal or amplified signal AS at the first node A is monitored in real time. For example, the amplitude of the first measurement signal IS1 is fixed, and the amplitude of the second measurement signal IS2 is adjustable. The amplitude of the second measurement signal IS2 is gradually adjusted, for example, by increasing or decreasing, until the amplitude of the amplified signal AS is less than or equal to the first threshold M. At this time, it can be determined that the signal at the first node A is substantially 0, and the amplitude of the second measurement signal IS2 is recorded at this time. The capacitance parameter C of the chip under test 30 is determined using the aforementioned calculation formula, that is,

[0066] C=C ref V2 / V1

[0067] Among them, C ref represents the capacitance parameter of the reference capacitor, V1 represents the amplitude of the first measurement signal, and V2 represents the amplitude of the second measurement signal.

[0068] Figure 4 A circuit diagram of a test circuit on a measurement circuit board provided in some embodiments of the present disclosure. Figure 4 As shown, the amplifier circuit 23 includes an operational amplifier Amp, which includes a non-inverting input terminal, a reverse input terminal, and an output terminal. The non-inverting input terminal is electrically connected to the first node A, the reverse input terminal is electrically connected to a reference voltage, such as a ground voltage, such as 0V, via a first resistor R1, and the output terminal is electrically connected to the reverse input terminal via a second resistor R2. Figure 4 In the test circuit shown, the amplified signal AS and the value of the signal S at the first node A have the following relationship:

[0069] AS=S·(R1+R2) / R1

[0070] Here, R1 represents both the first resistor and the resistance value of the first resistor, and R2 represents both the second resistor and the resistance value of the second resistor.

[0071] By properly setting the resistance values ​​of the first resistor R1 and the second resistor R2, the amplification factor n of the amplifier circuit 23 can be determined. In some embodiments, n is, for example, greater than or equal to 50, such as 100, 200, etc. This setting allows for more precise adjustment of the amplitude of at least one of the first measurement signal IS1 and the second measurement signal IS2 so that the amplitude of the signal S at the first node A is substantially zero, thereby achieving accurate measurement of the capacitance parameter C of the chip under test 30.

[0072] Figure 5A circuit diagram of a test circuit on a measurement circuit board provided in some embodiments of the present disclosure. Figure 5 As shown, the amplifier circuit 23 includes an operational amplifier Amp, which includes a non-inverting input terminal, a reverse input terminal, and an output terminal. The non-inverting input terminal is electrically connected to a reference voltage, such as a ground voltage, such as 0V, the reverse input terminal is electrically connected to the first node A via a third resistor R3, and the output terminal is electrically connected to the reverse input terminal via a fourth resistor R4. Figure 5 In the test circuit shown, the amplified signal AS and the value of the signal S at the first node A have the following relationship:

[0073] AS=-S·R4 / R3

[0074] Here, R3 represents both the third resistor and the resistance value of the third resistor, and R4 represents both the fourth resistor and the resistance value of the fourth resistor.

[0075] By properly setting the resistance values ​​of the third resistor R3 and the fourth resistor R4, the amplification factor n of the amplifier circuit 23 can be determined. In some embodiments, n is, for example, greater than or equal to 50, such as 100, 200, etc. This setting allows for more precise adjustment of the amplitude of at least one of the first measurement signal IS1 and the second measurement signal IS2 so that the amplitude of the signal S at the first node A is substantially zero, thereby achieving accurate measurement of the capacitance parameter C of the chip under test 30.

[0076] In some implementations, the capacitance measurement device further includes a manipulator configured to install or remove the chip under test 30 to or from the test station 22. This arrangement enables automated loading of the chip under test 30 and automated capacitance parameter testing. This avoids operator error caused by manual operation, achieves standardized testing, and improves testing efficiency.

[0077] In some embodiments, the amplifier circuit 23 may also adopt other amplifier circuits as long as it can amplify the signal at the first node A.

[0078] In some embodiments, the capacitance parameter C of the reference capacitor is ref It is known that for batch measurement chips, the reference capacitance C ref The selection can be determined based on the capacitance parameters calibrated for the batch of chips. For example, the reference capacitance C ref The reference capacitor C can be selected to be of the same magnitude as the capacitance parameter calibrated for the batch of chips. For example, if the capacitance parameter calibrated for the batch of chips is 80mF, a reference capacitor with a capacitance parameter of 100mF can be selected. In some embodiments, the reference capacitor C refThe capacitance parameters may be the same as those calibrated for the batch of chips. In this case, the amplitudes of the first measurement signal IS1 and the second measurement signal IS2 initially given may be the same.

[0079] In some embodiments, the reference capacitor is an adjustable capacitor. In this way, the same measurement circuit board can be applied to the capacitance parameter measurement of chips of different models. The problem of needing to replace the measurement circuit board for chips of different models is avoided. For example, in the process of testing chips of different models using the same measurement circuit board, when the capacitance parameters of the chip of the first model are tested, the adjustable capacitor is adjusted to a first reference capacitance value according to the capacitance parameters calibrated for the chip of the first model. When the capacitance parameters of the chip of the second model are tested, the adjustable capacitor is adjusted to a second reference capacitance value according to the capacitance parameters calibrated for the chip of the second model.

[0080] Figure 6 This is a schematic diagram of the structure of the measurement circuit board provided in some embodiments of the present disclosure. Figure 6 As shown, the measuring circuit board 20 includes a substrate 21 and a test station 22 arranged on the substrate, and the number of the test station is one or more. Figure 6 As shown, there are, for example, four test stations 22, and the measurement circuit board 20 also includes one or more test circuits, for example, four sets, corresponding to the above-mentioned test stations. This arrangement allows multiple chips to be tested for capacitance parameters simultaneously, further improving test efficiency. In some embodiments, the test circuits and the test stations can be respectively arranged on both sides of the substrate 21, so that the layout on the substrate 21 is more reasonable, for example, more test stations can be set.

[0081] Figure 7 A flow chart of a capacitance measurement method provided in some embodiments of the present disclosure, such as Figure 7 As shown, some embodiments of the present disclosure provide a capacitance measurement method, using the capacitance measurement device 100 described in the above embodiments, the capacitance measurement method includes the following steps:

[0082] S71: Using the automatic testing machine to simultaneously provide a first measurement signal and a second measurement signal to the reference capacitor and the chip to be tested installed at the testing station, respectively.

[0083] Specifically, the automatic test machine is used to simultaneously provide the first measurement signal IS1 and the second measurement signal IS2 to the test circuit, that is, to the reference capacitor C refThe chip under test 30 mounted at the test station 22 provides a first measurement signal IS1 and a second measurement signal IS2, respectively. Both the first measurement signal IS1 and the second measurement signal IS2 are sine or cosine signals, and the phase difference between the first measurement signal IS1 and the second measurement signal IS2 is (2n+1)π, where n is an integer. The amplitudes of the two signals may be equal or unequal, and their signs may be opposite.

[0084] S73: Adjust the amplitude of at least one of the first measurement signal and the second measurement signal until the signal at the first node is substantially zero.

[0085] The signal at the first node A is monitored in real time, and the amplitude of at least one of the first measurement signal IS1 and the second measurement signal IS2 is adjusted until the signal S at the first node A is substantially zero. In some embodiments, the test circuit includes an amplifier circuit that can amplify the signal S at the first node A to obtain an amplified signal AS. In this case, the amplified signal output by the amplifier circuit can be monitored in real time, and the amplitude of at least one of the first measurement signal IS1 and the second measurement signal IS2 can be adjusted until the amplified signal AS is substantially zero.

[0086] S75: Determine the capacitance parameter of the chip to be tested based on the capacitance parameter of the reference capacitor, the amplitude of the first measurement signal, and the amplitude of the second measurement signal.

[0087] The automatic tester 10 provides the measurement result of the capacitance parameter of the chip under test. The capacitance parameter C of the chip under test is determined by the following formula:

[0088] C=C ref V2 / V1

[0089] Among them, C ref represents the capacitance parameter of the reference capacitor, V1 represents the amplitude of the first measurement signal, and V2 represents the amplitude of the second measurement signal, where C ref It is known that V1 and V2 are determined by the automatic test machine 10 and are also known.

[0090] In some embodiments, as Figure 7 As shown, before using the automatic tester to simultaneously provide the first measurement signal and the second measurement signal to the reference capacitor and the chip to be tested installed at the test station, the capacitance measurement method further includes:

[0091] S70: Using a robot arm to install the chip to be tested on the testing station.

[0092] There are multiple test stations 22 on the measurement circuit board 20. A robotic arm can be used to simultaneously load multiple chips 30 to be tested into the test stations 22 to perform capacitance parameter tests on the multiple chips 30 to be tested simultaneously, thereby improving test efficiency.

[0093] In some embodiments, after using the automatic tester to simultaneously provide the first measurement signal and the second measurement signal to the reference capacitor and the chip under test installed at the test station, respectively, the capacitance measurement method further includes:

[0094] S77: Using a robot arm to remove the tested chip from the testing station.

[0095] There are multiple test stations 22 on the measurement circuit board 20 , and a robotic arm can be used to simultaneously remove multiple tested chips 30 from the test stations 22 .

[0096] In some embodiments, steps S70 - S77 are executed in a loop to complete the testing of chip capacitor parameters in batches.

[0097] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of the boxes in the block diagram and / or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0098] Finally, it should be noted that the various embodiments in this specification are described by way of example. Each embodiment focuses on the differences from other embodiments, and reference can be made to the common and similar parts between the various embodiments. For the systems or devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For relevant details, refer to the description of the methods.

[0099] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A capacitance measuring device configured to batch test capacitance parameters of chips, characterized in that: The capacitance measuring device comprises: Measurement circuit board, including: a test station configured to mount a chip to be tested; and a reference capacitor, wherein a first end of the reference capacitor is electrically connected to a first pin of a chip under test installed at the test station at a first node, a second end of the reference capacitor is configured to receive a first measurement signal, and a second pin of the chip under test installed at the test station is configured to receive a second measurement signal, and an automatic tester, electrically connected to the measurement circuit board, configured to provide the first measurement signal and the second measurement signal, and determine the capacitance parameter of the chip to be tested based on the signal at the first node, The first measurement signal and the second measurement signal are both sine signals or cosine signals, and the phase difference between the first measurement signal and the second measurement signal is (2n+1)π, where n is an integer, and the amplitude of at least one of the first measurement signal and the second measurement signal is adjustable.

2. The capacitance measuring device according to claim 1, wherein: The measurement circuit board also includes: an amplifier circuit, electrically connected to the first node, configured to receive a signal from the first node and output an amplified signal, The automatic testing machine is electrically connected to the measuring circuit board and is configured to receive and detect the amplified signal and determine the capacitance parameter of the chip to be tested based on the amplified signal.

3. The capacitance measuring device according to claim 2, wherein: The capacitance parameter of the chip under test mounted on the test station is determined by adjusting the amplitude of at least one of the first measurement signal and the second measurement signal until the amplified signal is less than or equal to a first threshold. The capacitance parameter C of the chip under test is determined by the following formula: in, represents the capacitance parameter of the reference capacitor, represents the amplitude of the first measurement signal, Indicates the amplitude of the second measurement signal.

4. The capacitance measuring device according to claim 2 or 3, wherein: The amplifier circuit includes an operational amplifier, which includes a non-inverting input terminal, a reverse input terminal and an output terminal. The non-inverting input terminal is electrically connected to the first node, the reverse input terminal is electrically connected to a reference voltage via a first resistor, and the output terminal is electrically connected to the reverse input terminal via a second resistor.

5. The capacitance measuring device according to claim 2 or 3, wherein: The amplifier circuit includes an operational amplifier, which includes a non-inverting input terminal, a reverse input terminal and an output terminal. The non-inverting input terminal is electrically connected to a reference voltage, the reverse input terminal is electrically connected to a first node via a third resistor, and the output terminal is electrically connected to the reverse input terminal via a fourth resistor.

6. The capacitance measuring device according to any one of claims 1 to 3, wherein: The capacitance measuring device further comprises: A robot is configured to install the chip to be tested on the test station or remove it from the test station.

7. The capacitance measuring device according to any one of claims 1 to 3, wherein: The reference capacitor is an adjustable capacitor.

8. The capacitance measuring device according to any one of claims 1 to 3, wherein: The number of the test stations is one or more.

9. A capacitance measurement method, using the capacitance measurement device according to any one of claims 1 to 8, the capacitance measurement method comprising: Using the automatic testing machine to simultaneously provide a first measurement signal and a second measurement signal to the reference capacitor and the chip to be tested installed at the testing station, respectively; adjusting the amplitude of at least one of the first measurement signal and the second measurement signal until the signal at the first node is substantially zero; as well as The capacitance parameter of the chip to be tested is determined based on the capacitance parameter of the reference capacitor, the amplitudes of the first measurement signal and the second measurement signal.

10. The capacitance measurement method according to claim 9, further comprising: before using the automatic tester to simultaneously provide the first measurement signal and the second measurement signal to the reference capacitor and the chip under test installed at the test station, respectively; The chip to be tested is installed on the testing station by using a robot.

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