Progressive MEMS double-layer solenoid inductor coil and integrated manufacturing method thereof

Abstract

A progressive MEMS double-layer solenoid inductor and an integrated preparation method thereof, comprising an inner and outer double-layer coil and a substrate; the present invention expands a single-layer MEMS solenoid inductor into a double-layer, thereby expanding the dimension of the MEMS inductor, further improving its space utilization, and achieving a breakthrough in improving the inductance value and the quality factor; compared with the traditional C-type winding method, the progressive winding suppresses its capacitance effect at high frequencies, thereby further improving its resonant frequency; a pure MEMS preparation method is used to reduce the production cost of a single-chip coil, and a MEMS process method is used to make it compatible with IC technology, thereby making it have better IC compatibility in packaging applications; compared with a glass substrate, the use of semiconductor material as its substrate significantly enhances its heat dissipation effect, and for MEMS power devices, the problem of heat accumulation is well solved by integration with a micro-semiconductor heat sink.

Description

Technical Field

[0001] The invention relates to a design of an electronic component, and in particular to a progressive MEMS double-layer solenoid inductor coil and an integrated preparation method thereof. Background Art

[0002] Nuclear magnetic resonance (NMR) technology is a non-destructive testing technology that uses an external magnetic field to detect the difference in the nuclear signals at different positions of the sample to analyze the content and distribution of a specified substance in the sample. With the increasing requirements for sensitivity and accuracy, the use of traditional winding coils has gradually failed to meet existing requirements due to inherent defects such as winding errors and the inability to control the distance between windings. In addition, as the requirements for miniaturization and integration of electromagnetic devices with inductor windings as core components, such as fluxgate sensors, micro pumps, micro motors, micro energy harvesters, micro transformers, micro isolators, etc., are increasing, the demand for smaller inductor coils with higher quality factors and less heat generation is increasing, and the design of new MEMS coils is imminent.

[0003] MEMS coils processed using micro-electro-mechanical system (MEMS) technology, optical lithography technology, deep reactive ion etching (DRIE) technology, silicon direct bonding (SDB) technology and other MEMS technologies can overcome the inherent defects of winding errors of hand-wound coils.

[0004] Chinese patent application number CN202011454522.0 proposes a MEMS three-axis energy harvester based on the principle of electromagnetic induction and designed with a MEMS planar rectangular inductor coil. It adopts a planar folded inductor arrangement and uses it as a core device for converting vibration energy into electrical energy. It is characterized by the use of several coils that intersect and swirl vertically and horizontally. All coil windings are in the same plane, and there is a connecting wire extending from the plane into the bottom surface in the middle to connect the inner and outer circles of the coil. The use of a planar rectangular or circular MEMS inductor coil is a commonly used MEMS coil at present, with a simple process and low cost.

[0005] Chinese patent application number CN201410335299.6 proposes a probe based on the integration of gallium solenoid coil and glass microfluidic channel and its preparation method. The coil used in the invention has a glass substrate mainly composed of an upper coil slot, a number of middle through holes, and a lower coil slot. The layers of substrate are aligned and assembled by a bonding process, and the metal winding is cast from gallium with a lower melting point. This type of solenoid coil can well control the spacing between different turns of the coil, and has an improved inductance value compared to a planar coil.

[0006] However, the prior art has the following defects:

[0007] 1) The main disadvantage of a planar rectangular or circular coil designed with a planar concept is that it has severe magnetic leakage and it is difficult to deploy a magnetic core to increase the magnetic flux in the coil during use. Although its manufacturing process is simple, it is difficult to achieve good results in applications such as NMR technology, micro fluxgate sensors, and micromotors that require relatively high magnetic properties.

[0008] 2) Although the three-dimensional coil with solenoid design solves part of the magnetic leakage problem, its design concept is that it is difficult to make a traditional winding coil multi-layer structure, which limits the increase of its inductance value per unit volume. If you want to increase its inductance value, you must change the width and number of turns of the single-turn coil, which increases the volume of the coil and makes it impossible to achieve a higher inductance density. The development of double-layer and multi-layer coil technology is the general trend.

[0009] 3) Using low melting point metal as the body of the coil and using liquid metal casting method makes its current carrying capacity not too high. In the design of core inductance of power MEMS devices such as micro transformers, micro motors, micro isolators, etc., heat generation must be considered. The thermal effect of current will melt metals with low melting points such as gallium and aluminum, making the coil ineffective. The solution using glass substrate also further limits the temperature at which it can be cast due to the melting point of glass. If the method of electroplating metal is used, the above shortcomings can be well solved. Summary of the invention

[0010] The purpose of the present invention is to provide a double-layer solenoid coil which is easy to integrate and process by using MEMS technology, double-layer winding and through-hole electroplating technology and a preparation scheme thereof.

[0011] In order to solve the deficiencies in the prior art and achieve the above-mentioned purpose, the present invention discloses a progressive MEMS double-layer solenoid inductor coil, a preparation method and an inductor element thereof, and the technical scheme thereof is as follows:

[0012] The progressive MEMS double-layer solenoid inductor coil includes an inner and outer double-layer coil and a substrate, and is characterized in that the inner and outer two-layer substrates are used as the support of the progressive double-layer coil. The progressive double-layer coil adopts a cross-progressive method in the arrangement of the coil wire, that is, the two adjacent turns of the coil body are respectively located on the inner and outer substrates. The upper and lower parts of the outer coil body are connected through the outer through-holes made by the MEMS process located on all substrates; the upper and lower parts of the inner coil body are connected through the inner through-holes made by the MEMS process located on the inner upper and lower substrates; the adjacent turns of the inner and outer coils are electrically connected through the grooves made by the MEMS process and located on the inner and outer lower substrates and are parallel to each other; the coil body is made by a multi-step through-hole plating (TSV) process. The electrical connection between the coil and the outside is realized through two pads located on the outer substrate, and at the same time, the soft magnetic core is made by MEMS technology inside the inner substrate, and the soft magnetic core is wrapped by the double-layer coil body.

[0013] The present invention also discloses a method for preparing a progressive MEMS double-layer solenoid inductor coil, comprising the progressive MEMS double-layer solenoid inductor double-layer coil as claimed in any one of claims 1 to 3, characterized in that the method comprises the following steps:

[0014] Step 1, making the inner layer upper and lower substrates;

[0015] Step 2, making the magnetic core;

[0016] Step 3, bonding the first and second wafers;

[0017] Step 4, electroplating thinning of the inner coil;

[0018] Step 5, making the outer upper and lower substrates;

[0019] Step 6: Thinning the outer coil by electroplating.

[0020] In addition, the present invention also discloses an inductor element, which is characterized by comprising a double-layer coil prepared by the above-mentioned method for preparing the MEMS double-layer solenoid inductor coil.

[0021] Beneficial Effects

[0022] Expanding the existing single-layer MEMS solenoid inductor coil to a double-layer greatly expands the dimension of the MEMS inductor coil, further improves its space utilization, and makes new breakthroughs in improving inductance value and quality factor.

[0023] Compared with the traditional C-type winding method, the progressive winding can suppress the capacitance effect at high frequencies, so that its resonant frequency can be further increased, so that it can be used in some RF MEMS applications, such as high-frequency transformers, NFC coils, etc. Compared with the Z-type winding, it can achieve a higher resonant frequency under the same volume of component winding, so it has higher performance at higher frequencies. Compared with the traditional progressive winding method of winding coils, it is difficult to ensure that adjacent turns of the coil are accurately distributed in the inner and outer layers, and the use of MEMS technology can solve the above problems well.

[0024] The use of pure MEMS preparation methods can improve processing efficiency and reduce the production cost of single-chip coils. At the same time, the use of MEMS process methods can make it compatible with IC technology, so that it has better IC compatibility in packaging applications. Compared with glass substrates, the use of semiconductor materials as substrates will significantly enhance the heat dissipation effect. For MEMS power devices, the problem of heat accumulation can be well solved by integrating with micro-semiconductor heat sinks. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a schematic diagram of a Z-shaped double-layer coil substrate of the present invention;

[0026] Figure 2 Schematic diagram of the Z-shaped double-layer coil of the present invention

[0027] Figure 3 The present invention uses a double-layer coil pump body as a whole;

[0028] Figure 4 A top view of a micro pump using a double-layer coil according to the present invention;

[0029] Figure 5 The magnetic circuit layout diagram of the gear-type micro pump using the double-layer coil of the present invention;

[0030] Figure 6 Schematic diagram of the second wafer after step 1 process 13);

[0031] Figure 7 Step 5: Schematic diagram of the whole wafer after process 3);

[0032] Figure 8 Step 5: Schematic diagram of the whole wafer after process 4);

[0033] Fig. 9 Schematic diagram of the whole wafer after step 5 process 8). DETAILED DESCRIPTION

[0034] The progressive MEMS double-layer solenoid inductor coil includes an inner and outer double-layer coil and a substrate, and is characterized in that the inner and outer two-layer substrates are used as the support of the progressive double-layer coil. The progressive double-layer coil adopts a cross-progressive method in the arrangement of the coil wire, that is, the two adjacent turns of the coil body are respectively located on the inner and outer substrates. The upper and lower parts of the outer coil body are connected through the outer through-holes made by the MEMS process located on all substrates; the upper and lower parts of the inner coil body are connected through the inner through-holes made by the MEMS process located on the inner upper and lower substrates; the adjacent turns of the inner and outer coils are electrically connected through the grooves made by the MEMS process and located on the inner and outer lower substrates and are parallel to each other; the coil body is made by a multi-step through-hole plating (TSV) process. The electrical connection between the coil and the outside is realized through two pads located on the outer substrate, and at the same time, the soft magnetic core is made by MEMS technology inside the inner substrate, and the soft magnetic core is wrapped by the double-layer coil body.

[0035] The double-layer coil of the present invention is composed of two layers of inner and outer coils. Its characteristic substrate is as follows Figure 1 As shown, there are four layers of substrates, which are respectively an outer layer lower substrate (10), an inner layer lower substrate (20), an inner layer upper substrate (30), and an outer layer upper substrate (40) from bottom to top. The outer layer upper coil slot (41) located on the outer layer upper substrate is connected to the outer layer lower coil slot (12) located on the outer layer lower substrate (10) through the through hole (42) located on the outer layer upper substrate (40), the outer layer through hole (32) located on the inner layer upper substrate (30), the outer layer through hole (24) located on the inner layer lower substrate (20), and the through hole (11) located on the outer layer lower substrate (10). The inner layer upper coil slot (31) located on the inner layer upper substrate (30) is connected to the inner layer lower coil slot (23) located on the inner layer lower substrate (20) through the inner layer through hole (34) located on the inner layer upper substrate (30) and the inner layer through hole (22) located on the inner layer lower substrate (20). The upper magnetic core slot (33) located on the inner layer upper substrate (39) and the lower magnetic core slot (21) located on the inner layer lower substrate (20) are opposite to each other, and together form the magnetic core slot of the double-layer coil. The outer layer lower substrate (10), the inner layer lower substrate (20), the inner layer upper substrate (30), and the outer layer upper substrate (40) correspond to each other in position on the through hole. The double-layer coil is alternately inside and outside, and together form the inner and outer windings.

[0036] After the coil is processed, Figure 2 As shown, it consists of two layers of windings, the outer winding starting point is connected to the inner winding end point to achieve a progressive winding method, which has a better effect on improving the quality factor. The voltage difference between the inner and outer adjacent winding coils is small, and the capacitance effect loss is smaller under high frequency conditions, which is more suitable for high frequency applications.

[0037] Next, the preparation method of the MEMS double-layer solenoid inductor coil of the present invention is introduced, and the specific steps include:

[0038] Step 1, making the inner layer upper and lower substrates;

[0039] 1) using Piranha solution to clean the first and second wafers of semiconductor materials including but not limited to silicon materials;

[0040] 2) performing thermal oxidation treatment on the first and second wafers, wherein the thermal oxidation thickness is determined according to the thickness of the wafers, and forming an oxide layer of a certain thickness on the surface of the wafers;

[0041] 3) coating a layer of adhesion promoter on the surfaces of the first and second wafers;

[0042] 4) Spray or spin-coat a layer of photoresist on the upper surface of the first and second wafers, the photoresist type is a thin glue with a coating thickness of about 2 microns; place the first and second wafers in a nitrogen oven for pre-baking for a suitable time; spray or spin-coat a layer of photoresist on the lower surface of the first and second wafers, the photoresist type is the same as the upper surface; place the first and second wafers in a nitrogen oven for pre-baking for a suitable time;

[0043] 5) exposing a plurality of parallel inner upper coil groove shapes on the upper surface of the first wafer; exposing the upper magnetic core and inner and outer through-hole shapes on the lower surface of the first wafer; placing the first wafer in a developer of a corresponding photoresist type for development; placing the first wafer in a nitrogen oven for post-baking for a suitable time;

[0044] 6) exposing the lower magnetic core and the inner and outer through-hole shapes on the upper surface of the second wafer; exposing the shape of a plurality of parallel inner lower coil grooves on the lower surface of the second wafer; placing the second wafer in a developer of a corresponding photoresist type for development; placing the second wafer in a nitrogen oven for post-baking for a suitable time;

[0045] 7) placing the first and second wafers in a substrate material oxide selective etchant to etch the oxide layer exposed after development in 5) and 6) to the substrate layer;

[0046] 8) Cleaning the first and second wafers with Piranha solution; coating the surfaces of the first and second wafers with a layer of adhesion promoter;

[0047] 9) Spray or spin-coat a layer of photoresist on the upper surface of the first and second wafers, the photoresist type is a thick photoresist with a coating thickness of about 10 microns; place the first and second wafers in a nitrogen oven for pre-baking for a suitable time; spray or spin-coat a layer of photoresist on the lower surface of the first and second wafers, the photoresist type is the same as the upper surface; place the first and second wafers in a nitrogen oven for pre-baking for a suitable time;

[0048] 10) exposing the shapes of inner and outer through holes on the upper surface of the first wafer; exposing the shapes of the upper magnetic core and the inner and outer through holes on the lower surface of the first wafer; placing the first wafer in a developer of a corresponding photoresist type for development; placing the first wafer in a nitrogen oven for post-baking for a suitable time;

[0049] 11) exposing the lower magnetic core and the inner and outer through-hole shapes on the upper surface of the second wafer; exposing the inner and outer through-hole shapes on the lower surface of the second wafer; placing the second wafer in a developer of a corresponding photoresist type for development; placing the second wafer in a nitrogen oven for post-baking for a suitable time;

[0050] 12) Dry-etching the first wafer; first, etching the upper magnetic core groove and the inner and outer through-hole grooves on the back of the wafer; then etching the inner and outer through-hole grooves from the front until they are completely etched through; cleaning the first wafer with Piranha solution; finally, etching a plurality of parallel inner layer upper coil grooves on the front; completing the production of the inner layer upper substrate;

[0051] 13) Dry-etch the second wafer; first, etch the lower magnetic core groove and the inner and outer through-hole grooves on the front side of the wafer; then, etch the inner and outer through-holes from the back side until they are completely etched through; clean the second wafer with Piranha solution; finally, etch several parallel inner layer lower coil grooves on the back side; and complete the production of the inner layer lower substrate.

[0052] Step 2: Making the magnetic core

[0053] 1) Cleaning the first and second wafers prepared in step 1 with Piranha solution respectively;

[0054] 2) patterning a titanium or gold metal layer at the magnetic core groove on the reverse side of the first wafer; continuing to sputter or chemically plate at the patterned position to obtain a layer of iron or nickel metal layer;

[0055] 3) electroplating an iron-nickel alloy or an iron-cobalt alloy at the magnetic core groove position on the back side of the first wafer to a certain height;

[0056] 4) patterning a titanium or gold metal layer at the magnetic core groove on the front side of the second wafer; continuing to sputter or chemically plate at the patterned position to obtain a layer of iron or nickel metal layer;

[0057] 5) electroplating an iron-nickel alloy or an iron-cobalt alloy at the magnetic core groove position on the front side of the second wafer to a certain height;

[0058] 6) Patterning and coating a layer of acid-resistant coating on the electroplated magnetic core grooves of the first and second wafers.

[0059] Step 3: Bonding of the first and second wafers

[0060] 1) Cleaning the first and second wafers after step 2 with Piranha solution respectively;

[0061] 2) placing the first and second wafers in a tube furnace environment exceeding the gasification temperature of the acid-resistant coating to eliminate the acid-resistant coating;

[0062] 3) placing the first and second wafers in a substrate material oxide selective etchant to etch all remaining substrate oxides;

[0063] 4) placing the lower surface of the first wafer and the upper surface of the second wafer opposite to each other, performing low-temperature silicon-silicon bonding to form a whole wafer;

[0064] 5) The entire wafer is subjected to thermal oxidation treatment.

[0065] Step 4: Electroplating thinning of the inner coil

[0066] 1) sputtering a titanium or gold metal layer on the back surface of the entire wafer obtained in step 3, and then sputtering or chemically plating a copper metal layer on the back surface of the entire wafer;

[0067] 2) Electroplating metal copper from the back of the wafer to fill the coil slot on the inner lower substrate, and electroplating the inner and outer through holes to the plane position below the coil slot on the inner upper substrate;

[0068] 3) sputtering a titanium or gold metal layer on the entire front side of the wafer that has been electroplated with copper, and then sputtering or chemically plating a copper metal layer on the entire front side of the wafer;

[0069] 4) Electroplating metal copper from the front side of the wafer to fill the inner coil slot and connect it with the coil slot on the inner lower substrate through the inner through hole.

[0070] 5) Use a chemical mechanical polisher (CMP) to thin the copper metal to the height of the substrate thermal oxide layer, and perform CMP polishing on the front and back substrate surfaces.

[0071] Step 5: Preparation of the outer upper and lower substrates

[0072] 1) depositing a layer of insulating film on the entire surface of the wafer polished in step 4;

[0073] 2) coating a layer of adhesion promoter on the front and back surfaces of the wafer;

[0074] 3) Spin-coat a layer of photoresist on the upper surface of the entire wafer; place the entire wafer in a nitrogen oven for pre-baking; spin-coat a layer of photoresist on the lower surface of the entire wafer, with the photoresist type and spin-coating parameters being the same as on the upper surface; place the first and second wafers in a nitrogen oven for pre-baking

[0075] 4) photolithography the upper and lower surfaces of the entire wafer to form the shape of the outer through-holes; placing the entire wafer in a developer for development; and placing the entire wafer in a nitrogen oven for post-baking;

[0076] 5) Spin-coat a layer of photoresist on the entire front side of the wafer; soften and bake on a hot plate;

[0077] 6) Spin-coat a layer of photoresist on the entire back side of the wafer; soften and bake on a hot plate;

[0078] 7) Use weak light intensity to expose the outer coil groove on the front of the wafer as a whole; adjust the light intensity to expose the outer through hole on the front of the wafer as a whole;

[0079] 8) Use weak light intensity to expose the outer lower coil groove on the entire back side of the wafer; adjust the light intensity to expose the outer through hole on the entire back side of the wafer; place the wafer on a hot plate for post-baking, and place it in a developer for development, and finally place the wafer on a hot plate for hardening and baking; the outer substrate is obtained.

[0080] Step 6: Electroplating and thinning of the outer coil

[0081] 1) sputtering a titanium or gold metal layer on the lower surface of the outer layer lower substrate of the entire wafer obtained in step 5, and then sputtering or chemically plating a copper metal layer on the lower surface of the outer layer lower substrate;

[0082] 2) electroplating the outer layer lower coil groove from the lower surface of the inner layer lower substrate to the height of the outer layer lower substrate;

[0083] 3) sputtering a titanium or gold metal layer on the upper surface of the outer upper substrate of the entire wafer, and then sputtering or chemically plating a copper metal layer on the upper surface of the outer upper substrate;

[0084] 4) electroplating the outer layer lower coil groove from the upper surface of the outer layer upper substrate to the height of the outer layer upper substrate;

[0085] 5) using a chemical mechanical polisher (CMP) to thin the copper metal to the height of the substrate, and performing CMP polishing on the upper and lower substrate surfaces;

[0086] 6) Use a dicing machine to separate the double-layer coils to complete the preparation of the double-layer coil.

[0087] Example 1

[0088] Specific embodiment of Z-type silicon-based MEMS double-layer coil

[0089] When using silicon as the base substrate, two 4-inch 800μm thick ultra-high resistance zone melting silicon single crystal (FZ-Silicon) wafers are used, and their resistivity is greater than 1000Ω·cm. When electroplated copper is used as the winding, the inner turns of the coils are all in the silicon-based substrate. If low-resistance silicon is used, the coils between different turns will be directly connected through the silicon substrate, causing the entire inner coil to short-circuit and lose the spiral electrical connection function of the inductor itself. The use of high-resistance silicon wafers can better avoid this problem. The thermal oxidation performed after bonding the two layers of substrate in Example Step 3 also plays the same role. The high-resistance silicon surface that has been exposed by dry etching is oxidized again to produce an oxide layer to further protect the insulation of the inner turns of the coils connected through the substrate. The specific implementation steps will be introduced next. The device mainly consists of six steps.

[0090] Step 1, making the inner layer upper and lower substrates;

[0091] 1) Use Piranha solution to clean the first and second wafers of 4 inches in size and 800 μm in thickness, which are made of ultra-high resistance zone melt silicon single crystal (FZ-Silicon). The specific ratio of Piranha is concentrated sulfuric acid (95%) and concentrated hydrogen peroxide solution (30%) in a volume ratio of 3:1. Remove organic and metal impurities on the surface of the silicon wafer and reduce the problem of uneven oxide layer thickness in the next step of thermal oxidation of the silicon wafer;

[0092] 2) The first and second wafers are subjected to thermal oxidation treatment, and the thermal oxidation thickness is 2 μm, which ensures that a certain thickness of silicon dioxide oxide layer remains on the surface after the inner coil slot is etched in the subsequent dry process, thereby ensuring that the overall flat silicon surface can be guaranteed in the subsequent bonding process;

[0093] 3) Coating a layer of adhesion promoter composed of hexamethyldisilazane (HMDS) vapor on the surface of the first and second wafers to improve the adhesion of the photoresist in the next step of coating. The specific coating parameters are a chamber temperature of 150° C. and a chamber pressure of 20800 mTorr;

[0094] 4) Spin coating a layer of photoresist on the upper surface of the first and second wafers, the photoresist type is Shipley1813 G2Series, the spin coating parameters are a rotation speed of 2000rpm, a time of 30s, and a target photoresist coating thickness of 2μm; place the first and second wafers in a nitrogen oven for pre-baking, the specific parameters are an oven temperature of 115°C, a pre-baking time of 5min, so that the photoresist surface is partially solidified to ensure that the upper surface photoresist will not fall off on the vacuum chuck of the spin glue machine when the lower surface is coated; Spin coating a layer of photoresist on the lower surface of the first and second wafers, the photoresist type and spin coating parameters are the same as the upper surface; Place the first and second wafers in a nitrogen oven for pre-baking, the specific parameters are an oven temperature of 115°C, and a pre-baking time of 30min, further partially solidify the photoresist, and ensure its stable optical performance during photolithography;

[0095] 5) Photolithography is performed on the upper surface of the first wafer to form a plurality of parallel inner upper coil grooves and outer through-hole shapes; the lower surface of the first wafer is exposed to form the upper magnetic core and the inner and outer through-hole shapes; the photolithography parameters are wavelength 365nm, light intensity 10mJ / cm 2 / s, and the exposure time is 3s. The first wafer is placed in NMD-W 2.38% developer for development, and the development time is 2min; the first wafer is placed in a nitrogen oven for post-baking, and the specific parameters are oven temperature 115°C and post-baking time 15min;

[0096] 6) Photolithography the lower magnetic core and the inner and outer through-hole shapes on the upper surface of the second wafer; Photolithography the shape of a plurality of parallel inner lower coil slots on the lower surface of the second wafer; Place the second wafer in NMD-W 2.38% developer for development, and the development time is 2 minutes; Place the second wafer in a nitrogen oven for post-baking, and the specific parameters are oven temperature of 115° C. and post-baking time of 15 minutes;

[0097] 7) placing the first and second wafers in a buffered oxide etchant (BOE), specifically a mixture of 49% HF aqueous solution: 40% NH4F aqueous solution = 1:6 (volume ratio), etching time 30 minutes, etching the oxide layer exposed after development in 5) and 6) to the substrate layer, and using silicon dioxide as a mask during the subsequent coil slot etching;

[0098] 8) Cleaning the first and second wafers with Piranha solution to remove the S1813 photoresist coated on the front and back surfaces of the wafers in the previous step; coating the first and second wafers with a layer of adhesion promoter composed of hexamethyldisilazane (HMDS) vapor, with the coating parameters being the same as those described in step 3);

[0099] 9) Spin-coat a layer of photoresist on the upper surface of the first and second wafers, the photoresist type is AZ P4620, and the spin-coating parameters are a speed of 2000 rpm and a time of 50 s; place the first and second wafers in a nitrogen oven for pre-baking, the specific parameters are an oven temperature of 95° C., and a pre-baking time of 10 min; spin-coat a layer of photoresist on the lower surface of the first and second wafers, and the photoresist type and spin-coating parameters are the same as the upper surface; place the first and second wafers in a nitrogen oven for pre-baking, the specific parameters are an oven temperature of 95° C., and a pre-baking time of 60 min;

[0100] 10) The upper surface of the first wafer is photoetched to form the inner and outer through-hole shapes; the lower surface of the first wafer is photoetched to form the upper magnetic core and the inner and outer through-hole shapes. The photolithography parameters are wavelength 365nm and light intensity 10mJ / cm 2 / s, exposure time is 9s; the first wafer is placed in a developer prepared by mixing AZ 400K and ultrapure water in a ratio of 1:3 for development, and the development time is 2min; the first wafer is placed in a nitrogen oven for post-baking, and the specific parameters are oven temperature of 95°C and post-baking time of 30min;

[0101] 11) exposing the lower magnetic core and the inner and outer through-hole shapes on the upper surface of the second wafer; exposing the inner and outer through-hole shapes on the lower surface of the second wafer, the photolithography parameters are the same as those described in 10); placing the second wafer in a developer prepared by mixing AZ 400K and ultrapure water in a ratio of 1:3 for development, the development time is 2 minutes; placing the second wafer in a nitrogen oven for post-baking, the post-baking parameters are the same as those described in 10);

[0102] 12) Dry etching the first wafer; first, dry-etch the upper magnetic core groove and the inner and outer through-hole grooves to a depth of 450 μm on the back of the wafer. The dry etching is performed using an inductively coupled plasma dry etcher (ICP). The etching parameters are that the gas excitation electric field power is 600 W. During the etching stage, sulfur hexafluoride SF6 (flow rate is 130 sccm) and oxygen O2 (flow rate is 13 sccm) are excited into plasma and then accelerated by an electric field (power is 25 W) to bombard the surface of the silicon wafer. Silicon is etched through physical and chemical reactions. This process The process lasts for 8s; in the deposition protection stage, octafluorocyclobutane C4F8 (flow rate of 85sccm) is excited into plasma and adheres to the etching sidewall by gravity to protect the silicon sidewall, thereby achieving high vertical ratio etching. This process lasts for 5s, and the etching process and the deposition process are carried out alternately; the chamber temperature is maintained at 40°C, the silicon wafer substrate stage temperature is controlled at 25°C, and helium (He) is used on the back of the silicon wafer stage for silicon wafer cooling, and its working pressure is 9800mTorr; the reaction of sulfur hexafluoride SF6 plasma during the etching process is expressed as follows

[0103] SF6+e - →S x Fy + +S x F y - +F - +e - (1)

[0104] When the generated fluorine plasma bombards the silicon surface, it reacts with silicon as shown in the following formula:

[0105] Si+F - →SiF x ↑ (2)

[0106] The generated gas is pumped out of the reaction chamber by a turbomolecular pump, thereby achieving silicon etching. The plasma reaction of octafluorocyclobutane C4F8 during the deposition process is expressed as follows:

[0107] C4F8+e - →CF x + +CF x - +F - +e - (3)

[0108] The generated negative plasma is deposited on the silicon surface and sidewalls to form a polymer passivation film. The reaction process is shown in the following formula:

[0109] CF x - →nCF2 (4)

[0110] The passivation film reacts under the bombardment of fluorine plasma generated by SF6 in the next cycle to produce gas, which is then drawn out of the reaction chamber.

[0111] nCF2+F - →CF x - →CF2↑ (5)

[0112] During the etching process, the electric field acceleration makes it easier for the plasma to bombard the silicon bottom surface, thereby protecting the polymer passivation film deposited on the side wall and achieving graphic etching with a depth-to-width ratio greater than 10:1.

[0113] When the target depth of the core groove is 445μm, the deposition protection process is cancelled and only the process gas ratio in the etching stage (i.e., sulfur hexafluoride SF6 (flow rate of 130sccm) and oxygen O2 (flow rate of 13sccm)) is used. When the depth reaches 450μm, a bottom fillet can be generated. This improves the strength of the core groove cavity during the bonding and thinning process, and prevents cracks generated during the subsequent bonding and thinning process from extending from the bottom of the substrate to the entire device, thereby causing the device to be scrapped.

[0114] Then, the inner and outer through holes are etched from the front side until they are completely through. The first wafer is cleaned with Piranha solution to remove the residual photoresist on the surface of the wafer. Finally, the oxide layer is used as a mask to etch several parallel inner layer upper coil grooves on the front side, with a specific etching depth of 200 μm. The inner layer upper substrate is fabricated.

[0115] 13) Dry-etch the second wafer; first, etch the lower magnetic core groove and the inner and outer through-hole grooves on the front side of the wafer, with the same process parameters as described in 12); then, etch the inner and outer through-holes from the back side until they are completely etched through; use Piranha solution to clean the photoresist on the second wafer; finally, etch several parallel inner layer lower coil grooves on the back side, with a specific etching depth of 200 μm; and complete the production of the inner layer lower substrate. The second wafer after the process is completed is as follows Figure 6 shown.

[0116] Step 2: Making the magnetic core

[0117] 1) Cleaning the first and second wafers produced in step 1 with Piranha solution to remove organic and metal impurities that may be generated in the previous steps;

[0118] 2) patterning a titanium metal layer at the magnetic core groove on the reverse side of the first wafer, with a specific sputtering thickness of 100 nm; and continuing to sputter a nickel metal layer at the above patterned position, with a specific thickness of 100 nm;

[0119] 3) electroplating iron-nickel alloy at the magnetic core groove position on the back side of the first wafer to a depth of 445 μm;

[0120] 4) patterning a titanium metal layer at the magnetic core groove on the front side of the second wafer, with a specific sputtering thickness of 100 nm; and continuing to sputter a nickel metal layer at the above patterned position, with a specific thickness of 100 nm;

[0121] 5) electroplating iron-nickel alloy at the magnetic core groove position on the front side of the second wafer to a height of 445 μm;

[0122] 6) A layer of acid-resistant coating is patterned on the electroplated magnetic core grooves of the first and second wafers. The specific parameters are that the coating is Teflon (polytetrafluoroethylene) coating with a coating thickness of 5 μm.

[0123] Step 3: Bonding of the first and second wafers

[0124] 1) Cleaning the first and second wafers after step 2 with Piranha solution respectively;

[0125] 2) Place the first and second wafers in a tube furnace at 450°C to remove the Teflon coating;

[0126] 3) placing the first and second wafers in a silicon dioxide selective etchant, specifically using a 49% HF aqueous solution and ultrapure water in a ratio of 1:5, to etch all remaining substrate oxides and activate the wafer surfaces to make them easier to bond with each other during pre-bonding;

[0127] 4) Place the lower surface of the first wafer opposite to the upper surface of the second wafer, align them using the preset alignment marks, and then perform low-temperature silicon-silicon bonding. The specific process parameters are: first pre-bonding, pre-bonding the wafers under a force of 1500N, a temperature of 300°C, and a high vacuum environment, and then annealing them in an annealing furnace at 200 degrees Celsius for 10 hours. The wafer is formed as a whole;

[0128] 5) The entire wafer is subjected to thermal oxidation treatment with a thermal oxidation thickness of 1 μm to ensure the insulation between the turns of the coil after electroplating;

[0129] Step 4: Electroplating thinning of the inner coil

[0130] 1) sputtering a titanium metal layer on the back surface of the entire wafer obtained in step 3, with a specific thickness of 100 nm, and then sputtering a copper metal layer on the back surface of the entire wafer, with a specific thickness of 100 nm;

[0131] 2) Electroplating metal copper from the back of the wafer to fill the coil slot on the inner lower substrate, and electroplating the inner and outer through holes to the plane position below the coil slot on the inner upper substrate;

[0132] 3) sputtering a titanium metal layer on the front surface of the wafer that has been electroplated with copper, with a specific thickness of 100 nm, and then sputtering or chemically plating a copper metal layer on the front surface of the wafer, with a specific thickness of 100 nm;

[0133] 4) Electroplating metal copper from the front side of the wafer to fill the inner coil slot and connect it with the coil slot on the inner lower substrate through the inner through hole.

[0134] 5) Use a chemical mechanical polisher (CMP) to thin the copper metal to the height of the thermal oxide layer of the silicon substrate, and perform CMP polishing on the front and back substrate surfaces.

[0135] Step 5: Preparation of the outer upper and lower substrates

[0136] 1) A layer of silicon dioxide film with a specific thickness of 180 nm is deposited on the entire surface of the wafer polished in step 4 using plasma enhanced chemical vapor deposition (PECVD) to achieve better insulation of the inner and outer coils.

[0137] 2) coating a layer of adhesion promoter on the front and back surfaces of the wafer;

[0138] 3) Spin-coat a layer of photoresist on the upper surface of the entire wafer. The photoresist type is Shipley1813 G2 Series. The spin-coating parameters are a rotation speed of 2000 rpm, a time of 30 s, and a target photoresist coating thickness of 2 μm. Place the entire wafer in a nitrogen oven for pre-baking. The specific parameters are an oven temperature of 115°C and a pre-baking time of 5 minutes to partially solidify the photoresist surface and ensure that the photoresist on the upper surface will not fall off on the vacuum chuck of the spin-bonding machine when the lower surface is coated with glue. Spin-coat a layer of photoresist on the lower surface of the entire wafer. The photoresist type and spin-coating parameters are the same as the upper surface. Place the first and second wafers in a nitrogen oven for pre-baking. The specific parameters are an oven temperature of 115°C and a pre-baking time of 30 minutes to further partially solidify the photoresist and ensure its stable optical performance during photolithography. After the process is completed, the entire wafer is as follows Figure 7 shown.

[0139] 4) The upper and lower surfaces of the wafer are photolithographically etched into the outer through-hole shape; the photolithography parameters are wavelength 365nm, light intensity 10mJ / cm 2 / s, exposure time is 3s. The first wafer is placed in NMD-W2.38% developer for development, and the development time is 2min. The first wafer is placed in a nitrogen oven for post-baking, and the specific parameters are oven temperature 115°C and post-baking time 15min. The entire wafer is placed in a buffered oxide etchant (BOE), and the specific ratio is a mixture of 49% HF aqueous solution: 40% NH4F aqueous solution = 1:6 (volume ratio), and the etching time is 30min. The oxide layer exposed after etching development is etched to the surface of the outer through hole. After the process is completed, the entire wafer is as follows Figure 8 shown.

[0140] 5) Spin-coat a layer of SU-82100 photoresist on the entire front side of the wafer, with a specific thickness of 20 μm and a spinning speed of 1500 rpm; soften and bake on a hot plate at 95°C for 30 minutes;

[0141] 6) Spin-coat a layer of SU-82100 photoresist on the back surface of the wafer, with a specific thickness of 20 μm and a spin speed of 1500 rpm; soften and bake on a hot plate at 95° C. for 30 minutes;

[0142] 7) Use weak light intensity to expose the outer coil groove on the front of the wafer as a whole; adjust the light intensity to expose the outer through hole on the front of the wafer as a whole; the exposure parameter is light intensity 10mJ / cm 2 / s, exposure time is 28s;

[0143] 8) Use weak light intensity to expose the outer layer lower coil groove on the back of the entire wafer; adjust the light intensity to expose the outer layer through hole on the back of the entire wafer; place the wafer on a 95°C hot plate for post-baking, and place it in SU-82000 developer for 17 minutes, and finally place the wafer on a 200°C hot plate for 20 minutes of hardening baking; the outer layer substrate is obtained. After the process is completed, the entire wafer is as follows Fig. 9 shown.

[0144] Step 6: Electroplating and thinning of the outer coil

[0145] 1) sputtering a titanium metal layer on the lower surface of the outer lower substrate of the entire wafer obtained in step 5, with a specific thickness of 100 nm, and then sputtering a copper metal layer on the lower surface of the outer lower substrate, with a specific thickness of 100 nm;

[0146] 2) electroplating the outer layer lower coil groove from the lower surface of the inner layer lower substrate to the height of the outer layer lower substrate;

[0147] 3) sputtering a titanium or gold metal layer on the upper surface of the outer upper substrate of the entire wafer, and then sputtering or chemically plating a copper metal layer on the upper surface of the outer upper substrate;

[0148] 4) electroplating the outer layer lower coil groove from the upper surface of the outer layer upper substrate to the height of the outer layer upper substrate;

[0149] 5) Use a chemical mechanical polisher (CMP) to thin the copper metal to the substrate height, and perform CMP polishing on the upper and lower substrate surfaces.

[0150] Use a dicing machine to separate the double-layer coils to complete the preparation of the double-layer coils.

[0151] Example 2, flexible substrate double-layer coil

[0152] When used as a flexible substrate double-layer coil, the double-layer coil processed through 6 steps mentioned in the present invention is completely digested with different substrate selection etchants according to different substrate materials to obtain the coil body and the magnetic core body. It is placed in a special mold, poured with a flexible substrate (such as PDMS), and the mold is separated from the flexible substrate to obtain a flexible substrate coil. It can be used in the core of electromagnetic devices in human implants, such as blood supply pumps, drug supply pumps and other applications.

[0153] Embodiment 3, gear-synchronized valve-type electromagnetic micropump using a progressive double-layer coil

[0154] When the progressive double-layer coil is used as a core component in a gear-synchronized valve-type electromagnetic micropump, it is arranged symmetrically on the upper and lower sides of the flow channel to drive the permanent magnet in the flow channel to reciprocate.

[0155] Its specific feature is that the pump body is made of deep silicon etching, which can make it easy to integrate with the structure of the microfluidic chip, thereby reducing the on-chip driving source of the traditional microfluidic chip and improving the efficiency of microfluidic experiments.

[0156] Its structural features include an inlet (1); an inlet gear synchronous valve (2); a flow channel (3), in which there is a rectifying protrusion module; a chrome-plated NdFeB permanent magnet (4) magnetized along its thickness direction as a fluid driving component, and its position in the flow channel is called a driving cavity; an outlet gear synchronous valve (5); and an inlet. The progressive double-layer coil (7) is placed on the glass cover plate directly above the permanent magnet driving cavity and on the silicon surface on the back of the driving cavity. Its specific structure is as follows: Figure 3 , 4 Shown

[0157] The soft magnetic material (8) in the upper and lower double-layer coils and the permanent magnet in the flow channel form a unique magnetic circuit of the micro pump. When the double-layer coils are energized, the interaction between the energized wires and the permanent magnets causes the permanent magnets to reciprocate in the driving cavity under the action of bidirectional pulse current. Figure 4 shown.

[0158] When the permanent magnet moves toward the outlet, the fluid moves toward the outlet to open the outlet valve, and the use of the gear structure can synchronize the opening of the left and right valves, thereby balancing the flow of the left and right flow channels, thus solving the problem of uncontrollable valve body movement when a single valve is used. Similarly, when the permanent magnet moves toward the outlet, under the guidance of the fluid, the inlet valve is also opened to replenish the fluid at the inlet into the drive chamber.

[0159] When the permanent magnet moves toward the inlet, the fluid moves toward the inlet, and the inlet and outlet valves are closed. This design can greatly reduce backflow and make the micro pump have better anti-back pressure capability.

[0160] After solving many problems of the existing traditional winding coils, this magnetic circuit can significantly reduce the thrust fluctuation of the permanent magnet throughout the entire stroke compared with the existing traditional attraction-repulsion magnetic circuit design mode, and can significantly reduce the thickness of the micropump, making it easier to integrate with the existing microfluidic chip. The advantage of using a progressive double-layer coil is that the number of turns increases due to the improvement in space utilization efficiency, which leads to an increase in inductance. Ultimately, it is reflected in the improvement of magnetic circuit efficiency, giving it greater potential in the direction of low power consumption.

[0161] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions only describe the principles of the present invention. The present invention may be subject to various changes and improvements without departing from the spirit and scope of the present invention. These changes and improvements fall within the scope of the present invention. The scope of protection claimed by the present invention is defined by the attached claims and their equivalents.

Claims

1. A progressive MEMS double-layer solenoid inductor coil, comprising an inner and outer double-layer coil and a substrate, wherein the substrate is divided into four layers: from bottom to top, an outer lower substrate, an inner lower substrate, an inner upper substrate, and an outer upper substrate; the characteristics are: The inner and outer two-layer substrates are used as the support for the progressive double-layer coil; the progressive double-layer coil adopts a cross-progressive method in the arrangement of the coil wire, that is, the coil bodies of two adjacent turns are respectively located on the inner and outer substrates; the upper and lower parts of the outer coil body are connected through the outer through-holes made by the MEMS process located on all substrates; the upper and lower parts of the inner coil body are connected through the inner through-holes made by the MEMS process located on the inner upper and lower substrates; the inner and outer coils of adjacent turns are electrically connected through the grooves made by the MEMS process and located on the inner and outer lower substrates and are parallel to each other; the coil body is made by a multi-step through-hole electroplating process; the coil is electrically connected to the outside This is achieved by two pads located on the outer substrate, while a soft magnetic core is made of MEMS technology inside the inner substrate, and the soft magnetic core is wrapped by a double-layer coil body; the MEMS double-layer solenoid inductor coil is a MEMS double-layer solenoid inductor double-layer coil with a silicon base or a flexible substrate as the main basic substrate; the entity of the coil is composed of inner and outer two layers of windings, and the starting point of the outer winding is connected to the end point of the inner winding to realize a progressive winding method; the capacitance effect of the progressive winding at high frequency will be suppressed, so that its resonant frequency is increased, and a higher resonant frequency can be achieved under the same volume of component winding, thereby having performance at higher frequencies.

2. The progressive MEMS double-layer solenoid inductor according to claim 1, characterized in that: The outer layer upper coil slot located on the outer layer upper substrate is connected to the outer layer lower coil slot on the outer layer lower substrate through the through hole located on the outer layer upper substrate, the outer layer through hole located on the inner layer upper substrate, the outer layer through hole located on the inner layer lower substrate, and the through hole located on the outer layer lower substrate; the inner layer upper coil slot located on the inner layer upper substrate is connected to the inner layer lower coil slot on the inner layer lower substrate through the inner layer through hole located on the inner layer upper substrate and the inner layer through hole located on the inner layer lower substrate; the upper magnetic core slot located on the inner layer upper substrate is opposite to the lower magnetic core slot located on the inner layer lower substrate, and together constitutes the magnetic core slot of the double-layer coil; the above-mentioned outer layer lower substrate, inner layer lower substrate, inner layer upper substrate, and outer layer upper substrate correspond to each other in position on the through hole; the double-layer coil alternates inside and outside and moves forward gradually, and together constitutes the inner and outer windings.

3. A method for preparing a progressive MEMS double-layer solenoid inductor coil, comprising the progressive MEMS double-layer solenoid inductor coil according to any one of claims 1 to 2, characterized in that: The steps include: Step 1, making the inner layer upper and lower substrates; Step 2, making the magnetic core; Step 3, bonding the first and second wafers; Step 4, the inner coil is electroplated and thinned; Step 5, making the outer upper and lower substrates; Step 6: Thinning the outer coil by electroplating.

4. The method for preparing the progressive MEMS double-layer solenoid inductor according to claim 3, characterized in that: The production of the magnetic core in step 2 includes the following contents: 1) Cleaning the first and second wafers prepared in step 1 with Piranha solution respectively; 2) patterning a titanium or gold metal layer at the magnetic core groove on the reverse side of the first wafer; continuing to sputter or chemically plate at the patterned position to obtain a layer of iron or nickel metal layer; 3) electroplating an iron-nickel alloy or an iron-cobalt alloy at the magnetic core groove position on the back side of the first wafer to a certain height; 4) patterning a titanium or gold metal layer at the magnetic core groove on the front side of the second wafer; continuing to sputter or chemically plate at the patterned position to obtain a layer of iron or nickel metal layer; 5) Electroplating iron-nickel alloy or iron-cobalt alloy at the magnetic core groove position on the front side of the second wafer to a certain height.

5. The method for preparing the progressive MEMS double-layer solenoid inductor according to claim 4, characterized in that: The preparation of the substrate in step 5 includes the following contents: 1) depositing a layer of insulating film on the entire surface of the wafer polished in step 4; 2) coating a layer of adhesion promoter on the front and back surfaces of the wafer; 3) Spin-coating a layer of photoresist on the upper surface of the entire wafer; placing the entire wafer in a nitrogen oven for pre-baking; spin-coating a layer of photoresist on the lower surface of the entire wafer, the photoresist type and spin-coating parameters are the same as the upper surface; placing the entire wafer in a nitrogen oven for pre-baking; 4) photolithography the upper and lower surfaces of the entire wafer to form the shape of the outer through hole; placing the entire wafer in a developer for development; placing the entire wafer in a nitrogen oven for post-baking; placing the entire wafer in a substrate oxide layer selective etchant to etch the oxide layer exposed after development to the surface of the outer through hole; 5) Spin-coat a layer of photoresist on the entire front side of the wafer; soften and bake on a hot plate; 6) Spin-coat a layer of photoresist on the entire back side of the wafer; soften and bake on a hot plate; 7) Use weak light intensity to expose the outer coil groove on the front of the wafer as a whole; adjust the light intensity to expose the outer through hole on the front of the wafer as a whole; 8) Use weak light intensity to expose the outer lower coil groove on the entire back side of the wafer; adjust the light intensity to expose the outer through hole on the entire back side of the wafer; place the wafer on a hot plate for post-baking, and place it in a developer for development, and finally place the wafer on a hot plate for hardening and baking; the outer substrate is obtained.

6. The method for preparing the progressive MEMS double-layer solenoid inductor according to claim 5, characterized in that: The step 6 includes the following contents: 1) sputtering a titanium or gold metal layer on the lower surface of the outer layer lower substrate of the entire wafer obtained in step 5, and then sputtering or chemically plating a copper metal layer on the lower surface of the outer layer lower substrate; 2) electroplating the outer layer lower coil groove from the lower surface of the inner layer lower substrate to the height of the outer layer lower substrate; 3) sputtering a titanium or gold metal layer on the upper surface of the outer upper substrate of the entire wafer, and then sputtering or chemically plating a copper metal layer on the upper surface of the outer upper substrate; 4) electroplating the outer layer lower coil groove from the upper surface of the outer layer upper substrate to the height of the outer layer upper substrate; 5) using a chemical mechanical polisher (CMP) to thin the copper metal to the height of the substrate, and performing CMP polishing on the upper and lower substrate surfaces; 6) Use a dicing machine to separate the double-layer coils to complete the preparation of the double-layer coil.

7. The method for preparing the progressive MEMS double-layer solenoid inductor according to claim 6, characterized in that: The step 3 includes the following contents: 1) Cleaning the first and second wafers after step 2 with Piranha solution respectively; 2) placing the first and second wafers in a tube furnace environment exceeding the gasification temperature of the acid-resistant coating to eliminate the acid-resistant coating; 3) placing the first and second wafers in a substrate material oxide selective etchant to etch all remaining substrate oxides; 4) Placing the lower surface of the first wafer and the upper surface of the second wafer opposite to each other, performing low-temperature silicon-silicon bonding to form a whole wafer.

8. Inductive element, characterized by: A double-layer coil prepared by the method for preparing a progressive MEMS double-layer solenoid inductor coil as described in any one of claims 3-7.

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