Single photon avalanche diode including capacitive effect passivation structure

Abstract

One aspect of the invention relates to a single photon avalanche diode comprising a capacitive effect passivation structure, the single photon avalanche diode comprising:-a semiconductor substrate doped with a first conductivity type and having a first face and a second face opposite the first face; -a peripheral isolation structure defining an active region of the semiconductor substrate, the peripheral isolation structure extending in the semiconductor substrate from the first side to the second side; a semiconductor region doped with a second conductivity type opposite to the first conductivity type, the semiconductor region extending from the first face to the second face in the active region of the semiconductor substrate; and-a capacitive effect passivation structure disposed within the first trench, the first trench extending in the semiconductor region, the capacitive effect passivation structure extending to contact the semiconductor region and configured to form a first charge accumulation layer in the semiconductor region at an interface with the first trench.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefits of a French patent application with application number FR2313040, filed on November 24, 2023, the entire content of which is incorporated herein by reference. Technical field

[0003] The technical field of the present invention is the technical field of single - photon avalanche diodes (also known as SPADs). Background art

[0004] A single - photon avalanche diode (SPAD) is a photodiode that includes a PN - junction photodiode reverse - biased to a voltage above its breakdown voltage. When there is no charge in the depletion region (also known as the space - charge region) of the PN - junction, the photodiode is in a metastable, non - conducting state. When a charge generated by the absorption of a photon is injected into the depletion region, if the speed of propagation of the charge in the depletion region is high enough, i.e., if the electric field in the depletion region is strong enough, the photodiode enters avalanche. Thus, a single photon can generate a measurable electrical signal in a very short time period.

[0005] SPADs have high detection sensitivity and extremely short response times, making them excellent candidates for time - of - flight measurements in telemetry, face recognition, and light detection and ranging (LiDAR) applications. They can detect very low - intensity radiation and can also be used for single - photon detection and photon counting.

[0006] The PN - junction is typically formed between a substrate doped with a first conductivity type and a local region (in the substrate) doped with a second conductivity type opposite to the first conductivity type. One problem that occurs in SPADs with a horizontal PN - junction (i.e., parallel to the front and back of the substrate) is the collection of photo - generated charges deep in the substrate at a certain distance from the avalanche region of the photodiode (i.e., a part of the depletion region where the electric field is strong enough to trigger an avalanche by a single charge). In fact, beyond a certain distance from the PN - junction, the electric field generated by the reverse - bias of the PN - junction is canceled or strongly attenuated, and this electric field can no longer drive the photo - generated charges towards the avalanche region. Then, only random diffusion in the substrate has the possibility of driving the photo - generated charges towards the avalanche region, where the probability that the photo - generated charges never reach the avalanche region or reach the avalanche region with a significant time delay is non - negligible. This problem occurs especially when it is necessary to collect photo - generated charges under the influence of high - wavelength radiation (e.g., radiation in silicon with wavelengths between 750 and 1200 nanometers (nm)).

[0007] Figure 1 It is a cross-sectional schematic diagram of the SPAD type photodiode 1 described in the international application WO2018 / 050996A1.

[0008] The photodiode 1 includes a substrate 10 made of P-type doped silicon and a local region 11 made of N-type doped silicon. The local region 11 extends through the substrate 10 in a direction substantially perpendicular (i.e., substantially perpendicular to the upper surface 10a of the substrate 10). The local region 11 is, for example, in the form of a tube with a substantially vertical central axis. The substrate 10 and the local region 11 form the anode and cathode of the photodiode 1 respectively. The avalanche region of the photodiode 1 is located at the PN junction formed between the side surfaces of the substrate 10 and the local region 11. This avalanche region extends into the substrate 10 in a substantially vertical direction. This configuration enables effective collection of the photo-generated charges deep in the substrate 10.

[0009] The photodiode 1 further includes:

[0010] - A P-type lightly doped layer 12 (P - doping), which has a doping level lower than that of the substrate 10, and the P-type lightly doped layer 12 covers the lower surface 10b of the substrate 10;

[0011] - A P-type doped support layer 13, which has a doping level higher than that of the P-type lightly doped layer 12, and the P-type doped support layer 13 covers the P-type lightly doped layer 12; and

[0012] - An N-type lightly doped region 14 (N - doping), which has a doping level lower than that of the local region 11, and the N-type lightly doped region 14 laterally surrounds the upper part 11a of the local region 11.

[0013] The P-type lightly doped layer 12 and the N-type lightly doped region 14 (due to their lower doping levels) reduce the electric fields at the upper and lower parts of the PN junction, and thus reduce the risk of inadvertently triggering an avalanche due to the charges generated by silicon surface defects.

[0014] The local region 11 is formed by etching a trench 15 from the upper surface 10a of the substrate 10. The trench 15 passes through the N-type lightly doped region 14, the substrate 10, and stops in the P-type lightly doped layer 12, and then the trench 15 is filled with N-type doped polysilicon.

[0015] However, the surface defining the trench 15 has many defects caused by etching, and these defects generate dark current in the presence of an electric field.

[0016] In addition, Patent US11387379B2 describes an avalanche photodetector for single-photon detection, the detection principle of which is not based on a PN junction. Such a photodetector should not suffer from the drawbacks of PN-junction SPADs, such as high dark current caused by silicon defects.

[0017] Figure 2 is a cross-sectional schematic view of the avalanche photodetector 2 described in this patent. The photodetector 2 includes a P-type doped semiconductor substrate 20 and a peripheral structure 21 called Capacitive Deep Trench Isolation (CDTI). The peripheral structure 21 extends through the semiconductor substrate 20 and surrounds the active region of the semiconductor substrate 20 for photon absorption. The CDTI peripheral structure 21 forms a vertical gate structure. The vertical gate structure is formed by etching a trench 22 in the substrate 20, coating the sidewalls of the trench 22 with a layer of insulating material 210 (such as thermal oxide), and then filling the remaining part of the trench 22 with a conductive material 211 (such as polysilicon).

[0018] The CDTI peripheral structure 21 enables the formation of an electron accumulation layer in the P-type doped semiconductor substrate 20 at the interface with the insulating material layer 210. In other words, it enables the formation of a doped inversion layer as in the channel region of a metal-oxide-semiconductor (MOS) transistor. This inversion layer generates an electric field E that attracts (photo-generated by the absorption of photons hv) electrons towards the interface between the insulating material layer 210 and the semiconductor substrate 20. These electrons collide with the atoms of the semiconductor substrate 20, thereby releasing other electrons and causing an avalanche effect.

[0019] The electron accumulation layer or the doped inversion layer is equivalent to a thin N-type highly doped layer. The electric field E near the interface is in fact very high and abrupt, so that it causes the appearance of a band-to-band parasitic tunneling current. However, this parasitic tunneling current greatly increases the dark current of the photodetector. Summary of the Invention

[0020] Therefore, there is a need to provide a device with low dark current for detecting single photons.

[0021] According to one aspect of the present invention, this need tends to be met by providing a single-photon avalanche diode, which includes:

[0022] - A semiconductor substrate, which is doped with a first conductivity type and has a first surface and a second surface opposite to the first surface;

[0023] - A semiconductor region doped with a second conductivity type opposite to the first conductivity type, the semiconductor region extending from a first surface to a second surface in a semiconductor substrate; and

[0024] - A capacitive effect passivation structure disposed in a first trench extending from the first surface to the second surface in the semiconductor substrate, the capacitive effect passivation structure extending into contact with the semiconductor region, and the capacitive effect passivation structure being configured to form a first charge accumulation layer at the junction of the semiconductor region with the first trench.

[0025] The first charge accumulation layer formed in the semiconductor region enables passivation of surface defects generated by etching the first trench and elimination of any electric field at the junction with the first trench. Thus, these defects do not generate dark current.

[0026] Preferably, the capacitive effect passivation structure includes a first dielectric layer and a first charged layer, the first charged layer being separated from the semiconductor region by the first dielectric layer.

[0027] Alternatively, the capacitive effect passivation structure includes a first dielectric layer and an electrode, the electrode being separated from the semiconductor region by the first dielectric layer.

[0028] In the first and second embodiments, the diode further includes a peripheral isolation structure defining an active region of the semiconductor substrate, the peripheral isolation structure extending from the first surface to the second surface in the semiconductor substrate.

[0029] Advantageously, the peripheral isolation structure is disposed in a second trench, and the peripheral isolation structure is configured to form a second charge accumulation layer at the junction of the semiconductor substrate with the second trench.

[0030] The peripheral isolation structure preferably includes a second dielectric layer and a second charged layer, the second charged layer being separated from the active region of the semiconductor substrate by the second dielectric layer.

[0031] The single-photon avalanche diode may further include an opaque material layer separated from the active region of the semiconductor substrate by the second charged layer and the second dielectric layer.

[0032] In a third embodiment, the capacitive effect passivation structure surrounds the semiconductor region, which in turn surrounds the active region of the semiconductor substrate.

[0033] According to an improvement of the third embodiment, the capacitive effect passivation structure includes an opaque material layer.

[0034] In addition to the characteristics discussed in the preceding paragraphs, the diode according to the first aspect of the present invention may have one or more complementary characteristics from the following characteristics, which may be considered individually or in any technically feasible combination:

[0035] - The semiconductor region surrounds the passivation structure by a capacitive effect;

[0036] - The diode further includes a contact region of the semiconductor region;

[0037] - The contact region is disposed on the capacitive effect passivation structure located in the first trench;

[0038] - The contact region extends in the semiconductor region;

[0039] - The diode further includes a contact pad electrically connected to the semiconductor region through the contact region;

[0040] - The diode further includes a first electric field reducing layer disposed on the first surface of the semiconductor substrate; and

[0041] - The diode further includes a second electric field reducing layer disposed on the second surface of the semiconductor substrate.

[0042] The second aspect of the present invention relates to a method for manufacturing a single photon avalanche diode, the method comprising the following steps:

[0043] - Etching a first trench in a semiconductor substrate, the semiconductor substrate being doped with a first conductivity type and having a first surface and a second surface opposite to the first surface, the first trench extending from the first surface to the second surface;

[0044] - Forming a doped semiconductor region of a second conductivity type opposite to the first conductivity type, the semiconductor region being partially defined by the first trench and extending from the first surface to the second surface in the semiconductor substrate; and

[0045] - Forming a capacitive effect passivation structure in the first trench, the capacitive effect passivation structure being configured to form a first charge accumulation layer at the junction of the semiconductor region and the first trench.

[0046] In one embodiment, forming the semiconductor region includes the following sub-steps:

[0047] - Epitaxially forming a doped semiconductor layer on the side surface of the first trench, the doped semiconductor layer including doped impurities; and

[0048] - Performing diffusion annealing to laterally diffuse the doped impurities from the doped semiconductor layer into the semiconductor substrate.

[0049] In an alternative embodiment, the semiconductor region is formed by vapor phase diffusion doping from the side surface of the first trench. Description of the Drawings

[0050] For purposes of illustration and not limitation, other features and advantages of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, which include:

[0051] - Figure 1 (As described above) schematically shows a single photon avalanche diode according to the prior art;

[0052] - Figure 2 (As described above) schematically shows an avalanche photodetector according to the prior art;

[0053] - Figure 3 is a cross-sectional schematic view of a single photon avalanche diode according to a first embodiment of the present invention;

[0054] - Figure 4 schematically shows the behavior of the diode Figure 3 under reverse bias;

[0055] - Figure 5 is a cross-sectional schematic view of a single photon avalanche diode according to a second embodiment of the present invention;

[0056] - Figure 6 is a cross-sectional schematic view of a single photon avalanche diode according to a third embodiment of the present invention;

[0057] - Figure 7 is a partial top view schematic of a photodetector including a plurality of single photon avalanche diodes;

[0058] - Figures 8A to 8I represents steps of a method for manufacturing a single photon avalanche diode according to Figure 3 ;

[0059] For clarity, like reference numerals are used to identify like or similar elements in all of the drawings. Detailed Description

[0060] In the following description, the terms "front", "rear", "upper", "lower", "top", "bottom", "horizontal", "vertical", "lateral", etc., which are used to define the position or orientation of certain elements, refer to the orientation in Figures 3 to 6 and Figures 8A to 8I . In addition, unless otherwise specified, the terms "approximately", "substantially", and "in the order of" mean within 5%, or within 5 degrees when they relate to an absolute angle or angular orientation, or a relative angle or angular orientation.

[0061] Figure 3 、 Figure 5 and Figure 6Cross-sectional schematic diagrams represent different embodiments of the single-photon avalanche diode 3. The single-photon avalanche diode 3 can be generally referred to as "diode 3", "SPAD 3" or "photodiode 3".

[0062] In a common aspect of all these embodiments, the diode 3 includes:

[0063] - A semiconductor substrate 30, which is doped with a first conductivity type and has a first surface 30a and a second surface 30b opposite to the first surface 30a;

[0064] - A semiconductor region 31, which is doped with a second conductivity type opposite to the first conductivity type, and the semiconductor region 31 extends from the first surface 30a to the second surface 30b in the semiconductor substrate 30;

[0065] - A capacitive effect passivation structure 32, and the capacitive effect passivation structure 32 extends to contact the semiconductor region 31.

[0066] The semiconductor substrate 30 (simply described as "substrate 30" hereinafter) and the semiconductor region 31 are preferably formed of the same semiconductor material (such as silicon).

[0067] The first surface 30a and the second surface 30b of the substrate 30 extend along substantially parallel planes. The first surface 30a (in the orientation of the figure) corresponds to the front or upper surface of the substrate 30, while the second surface 30b corresponds to the back or lower surface of the substrate 30. The thickness of the substrate 30 can be between 1 micrometer (μm) and 25 μm, preferably between 5 μm and 20 μm.

[0068] The semiconductor region 31 preferably extends in a direction substantially perpendicular to the first surface 30a. Advantageously, the semiconductor region 31 passes through the substrate 30 (in other words, the semiconductor region 31 extends over the entire thickness of the substrate 30).

[0069] The semiconductor region 31 is a so-called "local" region because the semiconductor region 31 only occupies a part of the volume of the substrate 30. The semiconductor region 31 has a side surface 31c, and at least a part of the side surface 31c contacts the substrate 30, so as to obtain a PN junction extending deep into the substrate. The PN junction preferably extends in a direction substantially perpendicular to the first surface 30a.

[0070] When the substrate 30 is P-type doped and the semiconductor region 31 is N-type doped, the substrate 30 and the semiconductor region 31 form the anode and cathode of the diode 3 respectively. On the contrary, when the substrate 30 is N-type doped and the semiconductor region 31 is P-type doped, the substrate 30 and the semiconductor region 31 form the cathode and anode of the diode 3 respectively.

[0071] The diode 3 includes a depletion region that extends laterally on both sides of the PN junction, and this depletion region is also referred to as the space charge region. Avalanche of the diode 3 occurs in the so-called active part of this depletion region.

[0072] The capacitive effect passivation structure 32 (simply described as "passivation structure 32" hereinafter) is disposed within the first trench 33, and the first trench 33 partially defines the semiconductor region 31 and extends within the semiconductor region 31. As will be subsequently referred to Figure 8C and Figure 8D as described, the first trench 33 is used to form the semiconductor region 31.

[0073] The passivation structure 32 extends to contact the semiconductor region 31, preferably extending along a direction substantially perpendicular to the first surface 30a of the substrate. Advantageously, the passivation structure 32 passes through the substrate 30 (in other words, the passivation structure 32 extends beyond the entire thickness of the substrate 30).

[0074] As will be described hereinafter in connection with Figure 4 as described, the capacitive effect passivation structure 32 is configured to form a first charge accumulation layer at the junction with the first trench 33 in the semiconductor region 31.

[0075] In the illustrated embodiment, the diode 3 further includes a first electric field reducing layer 34 disposed on the first surface 30a of the substrate 30 (in other words, on the front surface) and / or a second electric field reducing layer 35 disposed on the second surface 30b of the substrate 30 (on the back surface). Each of the first electric field reducing layer 34 and the second electric field reducing layer 35 is formed of an N-type doped semiconductor material or a P-type doped semiconductor material, and the first electric field reducing layer 34 and the second electric field reducing layer 35 have a doping impurity concentration (donor type or acceptor type respectively) lower than that of the substrate 30. The semiconductor material is preferably silicon.

[0076] Preferably, the first electric field reducing layer 34 (on the front) has the same conduction type (i.e., the first conduction type) as the substrate 30, and the second electric field reducing layer 35 (on the back) has the opposite conduction type (i.e., the second conduction type).

[0077] Each of the first electric field reducing layer 34 and the second electric field reducing layer 35 may have a thickness between 50 nm and 1 μm, for example equal to 1 μm.

[0078] The semiconductor region 31 may extend from the upper surface of the first electric field reducing layer 34, through the first electric field reducing layer 34 and the substrate 30, and terminate on the upper surface of the second electric field reducing layer 35 or within the second electric field reducing layer 35.

[0079] Similarly, the first trench 33 may extend from the upper surface of the first electric field reducing layer 34, through the first electric field reducing layer 34 and the substrate 30, and terminate on or within the upper surface of the second electric field reducing layer 35.

[0080] The diode 3 further includes at least one first contact pad 361 and at least one second contact pad 362. The first contact pad 361 is electrically connected to the substrate 30, and the second contact pad 362 is electrically connected to the semiconductor region 31. These contact pads 361 and 362 enable an electric potential to be applied to the substrate 30 and the conductive region 31, thereby biasing the PN junction of the diode 3. For example, the contact pads 361 and 362 are made of metal (in which case they are referred to as contact metallisations).

[0081] As Figures 3 to 5 shown in the cross-sectional schematic view of, the diode 3 may include several first contact pads 361, which are distributed in such a way as to equalize the electric potential applied to the substrate 30 and to equalize the collection of charge carriers. In contrast, the diode 3 may include only one second contact pad 362 (the extent of the semiconductor region 31 is much smaller than that of the substrate 30).

[0082] Each first contact pad 361 is preferably disposed on and in contact with the upper surface of the first electric field reducing layer 34.

[0083] For each first contact pad 361, a first substrate contact region 371 may extend from the upper surface of the first electric field reducing layer 34 towards the substrate 30 so as to minimize the contact resistance (between the first contact pad 361 and the substrate 30). The first substrate contact region 371 is preferably made of doped semiconductor material of the same conductivity type as the substrate 30 but having a higher doping impurity concentration. Then, the first contact pad 361 is electrically connected to the substrate 30 through the first contact region 371. The first contact pad 361 is advantageously disposed on and in contact with the first contact region 371.

[0084] The second contact pad 362 is preferably located at the same horizontal height as one or more first contact pads 361, that is, at the horizontal height of the upper surface of the first electric field reducing layer 34 (which coincides here with the upper surface of the semiconductor region 31). Advantageously, a second contact region 372 for contacting the semiconductor region is provided to reduce the contact resistance (between the second contact pad 362 and the semiconductor region 31), and the second contact region 372 is preferably made of doped semiconductor material doped with the same conductivity type as the semiconductor region 31 but having a higher doping impurity concentration. Then, the second contact pad 362 is electrically connected to the semiconductor region 31 through the second contact region 372. The second contact pad 362 is advantageously disposed on and in contact with the second contact region 372.

[0085] According to an embodiment of the diode 3, the position of the second contact region 372 is different (and thus the position of the second contact pad 362 is different). In Figure 3 the embodiment, the second contact region 372 is located on the passivation structure 32 in the first trench 33. Thus, the second contact region 372 and the passivation structure 32 are aligned with each other. That is, the second contact region 372 does not extend laterally beyond the passivation structure 32. Thus, the second contact region 372 contacts the semiconductor region 31 only through its side surfaces. In Figure 5 and Figure 6 the embodiment, the second contact region 372 extends in the semiconductor region 31. Then, the second contact region 372 contacts the semiconductor region 31 through its side surfaces as well as its lower surface.

[0086] The first contact region 371 and the second contact region 372 are preferably made of (doped) silicon.

[0087] In the absence of the first electric field reducing layer 34, the first contact pad 361 and the second contact pad are disposed on the front surface 30a of the substrate 30 (instead of the upper surface of the first electric field reducing layer 34).

[0088] In operation, the cathode of the diode 3 is biased to a positive potential V+, and the anode of the photodiode (through the contact pads 361 and 362) is biased to a negative potential V− such that the cathode-anode voltage of the diode is greater than the avalanche voltage (in absolute value). Thus, when the diode 3 is reverse-biased, an electric field appears at the PN junction.

[0089] In the following, the operation of the diode 3 is described in connection with Figure 4 The figure shows the Figure 3 diode under reverse bias, but the described operation is common to all embodiments.

[0090] In Figure 4In the figure, the dashed lines indicate equipotential lines in the structure when the diode 3 is reverse-biased. In this example, the substrate 30 is P-type doped and forms the anode, while the semiconductor region 31 is N-doped and forms the cathode. The closer the equipotential lines are to each other, the stronger the electric field.

[0091] It can be clearly seen from the figure that since the doping levels (i.e., the concentrations of doped impurities) of the first electric field reducing layer 34 and the second electric field reducing layer 35 are lower than that of the substrate 30, the equipotential lines are less restricted at the upper part (at the junction between the first electric field reducing layer 34 and the upper part of the semiconductor region 31) and the lower part (at the junction between the second electric field reducing layer 35 and the lower part of the semiconductor region 31) of the PN junction than at the central part (at the junction between the substrate 30 and the central part of the semiconductor region 31) of the PN junction. Therefore, the electric fields generated at the upper and lower parts of the PN junction are not as strong as the electric field generated at the central part of the PN junction.

[0092] The doping impurity concentrations of the substrate 30, the semiconductor region 31, and the first and second electric field reducing layers 34 and 35, as well as the bias voltage of the diode, are preferably selected such that the electric field at the central part of the PN junction is strong enough (e.g., greater than 300 kV / cm over a distance of 100 nm to 500 nm along the direction perpendicular to the PN junction) so that avalanche is triggered by a single photo-generated charge; and such that the electric fields at the upper and lower parts of the PN junction are weak enough (e.g., less than 300 kV / cm) so that avalanche cannot be triggered by a single photo-generated charge. As an example, the breakdown voltage (or avalanche voltage) of the diode is between 10 volts (V) and 50 V (absolute value), and the reverse bias voltage of the photodiode is 0.5 to 10 V (absolute value) higher than its breakdown voltage. The concentration of doped impurities in the substrate 30 is, for example, between 5×10 -3 to 7×10 17 cm -3 (or between 5×10 16 cm -3 and 7×10 17 cm -3 . The concentration of doped impurities in the semiconductor region 31 is, for example, between 10 17 cm -3 and 10 19 cm -3 . The concentration of doped impurities in the first and second electric field reducing layers 34 and 35 is, for example, less than 5×10 16 cm -3 (or 5×10 16 cm -3 ). -3 )

[0093] The first electric field reducing layer 34 and the second electric field reducing layer 35 reduce the risk of inadvertently triggering an avalanche at the ends of the PN junction, which risk is associated with edge effects (such as the presence of surface defects in the semiconductor material). However, these layers are optional because other solutions can be provided to control the risk of inadvertently triggering an avalanche due to edge effects, such as by changing the shape of the upper and lower ends of the semiconductor region 31, or by reducing the doping level of the semiconductor region 31 at its upper and lower ends.

[0094] The passivation structure 32 is used to passivate the defects caused by etching the first trench 33 by forming a first charge accumulation layer at the junction of the semiconductor region 31 with the first trench 33. These charges have a polarity corresponding to the conduction type of the semiconductor region 31, i.e., the second conduction type. Thus, this is a true accumulation layer, rather than an inversion layer as in avalanche photodetectors of the prior art. In Figure 4 the example shown, the semiconductor region 31 is N-type doped, so the accumulated charges are electrons.

[0095] The charges come from surface contacts. The accumulation layer provides good electrical continuity between the contact and the rest of the semiconductor region 31 to ensure static and dynamic balance during the avalanche phase.

[0096] The defects are rendered inactive and the electric field at the level height of the first trench 33 is reduced. Thus, the dark current of the diode 3 is reduced with respect to a diode without a capacitive effect passivation structure (such as Figure 1 the diode).

[0097] The first trench 33 has a bottom side surface and a peripheral side surface. Here, the bottom of the first trench 33 is formed by the second electric field reducing layer 35. The peripheral side surface of the first trench 33 is at least partially formed by the semiconductor region 31.

[0098] The semiconductor region 31 and the first trench 33 can be arranged such that the peripheral side surface of the first trench 33 consists entirely of the semiconductor region 31.

[0099] Thus, by means of the first charge accumulation layer, at least partially passivate the peripheral side surface of the first trench 33. In addition to reducing the dark current, this passivation also brings the PN junction closer to the first trench 33 (without the risk of activating defects), and thus, more generally, reduces the lateral size of the diode 3. This reduction in the size of the diode 3 is particularly significant for forming a photodetector including a diode array.

[0100] As Figure 5 and Figure 6 shown in the embodiments of, the passivation structure 32 can occupy the entirety of the first trench 33; or as in Figure 3In the embodiment, the passivation structure 32 is only part of the first trench 33 (where the second contact region 372 occupies the upper part of the first trench 33).

[0101] The passivation structure 32 can adopt different configurations.

[0102] In Figure 3 the embodiment, the passivation structure 32 includes a first dielectric layer 321 and a first charged layer 322 separated from the semiconductor region 31 by the first dielectric layer 321.

[0103] The first dielectric layer 321 covers the peripheral side surface of the first trench 33, and the first dielectric layer 321 advantageously covers the bottom of the first trench 33. The first dielectric layer 321 is preferably formed of an oxide (such as silicon dioxide (SiO 2 )).

[0104] The first charged layer 322 contains charges having a polarity opposite to the required charge polarity in the semiconductor region 31. The first charged layer 322 is preferably formed of a dielectric material. For example, the dielectric material is silicon nitride (Si 3 N 4 ) in the case of a positively charged layer, and is aluminum oxide (Al 2 O 3 ) or tantalum pentoxide (Ta 2 O 5 ) in the case of a negatively charged layer. The charge surface density of the first charged layer 322 at the junction with the first dielectric layer 321 is preferably greater than 10 12 cm -2 .

[0105] The first charged layer 322 advantageously occupies the remaining part of the first trench 33. Therefore, the first charged layer 322 constitutes the core of the passivation structure 32, and the first dielectric layer 321 constitutes the outer shell of the passivation structure 32.

[0106] One advantage of this embodiment is that the passivation structure 32 does not need to be in electrical contact with the front of the substrate 30, but instead allows the formation of the second contact pad 362 and the second contact region 372 (see Figure 3 ). Then, the diode 3 can have a symmetric configuration with respect to the passivation structure 32. The second contact region 372 formed in the first trench 33 limits the contact area on the useful surface of the diode 3, which tends to avoid electric field peaks and thus inadvertently trigger avalanche on this surface.

[0107] In Figure 5In the embodiment, the passivation structure 32 includes the first dielectric layer 321 described above and an electrode 322' separated from the semiconductor region 31 by the first dielectric layer 321 in the manner of a MOS (metal oxide semiconductor) gate structure. The electrode 322' is a conductive layer made of, for example, doped polysilicon or metal. Similar to Figure 3 the embodiment in, the first dielectric layer 321 and the electrode 322' can form the outer shell and the core of the passivation structure 32, respectively.

[0108] During the operation of the diode 3, a voltage (in addition to the bias voltage of the PN junction) is applied between the electrode 322' and the semiconductor region 31 to form a first charge accumulation layer. To this end, the diode 3 includes a third contact pad 363 electrically connected to the electrode 322' of the passivation structure 32. The third contact pad 363 is preferably disposed on and in contact with the upper surface of the electrode 322'. Advantageously, the third contact pad 363 is at the same level as the first contact pad 361 and the second contact pad 362.

[0109] Similar to Figure 3 and Figure 5 the common aspect of the embodiment in, the semiconductor region 31 is in an annular shape (or tubular), and the passivation structure 32 occupies the space within the annulus. That is, the semiconductor region 31 surrounds the passivation structure 32. Therefore, the inner surface of the semiconductor region 31 in contact with the passivation structure 32 is peripheral. The annulus formed by the semiconductor region 31 preferably has a rectangular cross-section in the cross-section of the figure and a central axis substantially perpendicular to the first surface 30a.

[0110] In addition, the semiconductor region 31 and the passivation structure 32 themselves are surrounded by the so-called active region 30' of the substrate 30. Therefore, the side surface 31c of the semiconductor region 31 that is outside and in contact with the active region 30' of the substrate 30 is peripheral. The active region 30' of the substrate 30 is used for photon absorption.

[0111] The semiconductor region 31 and the passivation structure 32 are advantageously disposed at the center of the active region 30' of the substrate 30.

[0112] In addition, the diode 3 advantageously includes a peripheral isolation structure 38 that defines the active region 30' of the substrate 30. The peripheral isolation structure 38 preferably extends in the substrate 30 from the first surface 30a to the second surface 30b in a direction substantially perpendicular to the first surface 30a. Advantageously, the peripheral isolation structure 38 penetrates the substrate 30.

[0113] As shown in the figure, the peripheral isolation structure 38 can also extend through the first electric field reducing layer 34 and / or the second electric field reducing layer 35.

[0114] The peripheral isolation structure 38 is advantageously provided in the second trench 39 and is configured to form a second charge accumulation layer in the substrate 30 at the junction with the second trench 39 by capacitive effect. Thus, for the purpose of electrical and / or optical insulation of the diode 3, defects generated by etching the second trench 39 are passivated. In Figure 4 the example shown, the substrate 30 is P-type doped, so the accumulated charge is holes.

[0115] Such a peripheral isolation structure 38 may be referred to as a capacitive deep trench isolation (CDTI) structure.

[0116] Similar to the passivation structure 32, the peripheral isolation structure 38 may include:

[0117] - a second dielectric layer 381 (preferably an oxide such as SiO 2 etc.); and

[0118] - a second charged layer 382 (preferably a dielectric such as Si 3 N 4 , Al 2 O 3 or Ta 2 O 5 etc.) or (metallic or doped polysilicon)

[0119] a second electrode 382', the second charged layer 382 or the second electrode 382' being separated from the active region 30' of the substrate 30 by the second dielectric layer 381.

[0120] The second trench 39 has an annular shape (to surround the active region 30' and the semiconductor region 31). The second dielectric layer 381 covers the peripheral side surface of the second trench 39 formed by the active region 30' of the substrate 30. The second charged layer or the second electrode occupies all or part of the remaining portion of the second trench 39.

[0121] The peripheral isolation structure 38 may further include an opaque material layer 383, which is separated from the active region 30' by the second charged layer 382 or the second electrode 382' and the second dielectric layer 381. Such an opaque material layer 383, preferably made of metal, enables the peripheral isolation structure 38 to be rendered opaque, thus preventing photons emitted in the avalanche region of the diode 3 from propagating to one or more adjacent diodes 3 and triggering avalanches therein. Thus, the peripheral isolation structure 38 is configured to reduce optical crosstalk in addition to limiting charge leakage (electrical insulation). The opaque material layer represents a layer having a transmission factor of less than 20% for wavelengths between 400 nm and 1100 nm.

[0122] Alternatively, the peripheral isolation structure 38 can be a deep trench isolation structure or a DTI structure, which in fact does not have the function of passivating the side of the diode 3 through the capacitive effect and restricting optical crosstalk.

[0123] Figure 6 Fig. shows an embodiment of the diode 3, in which both the capacitive effect passivation structure 32 (disposed in the first trench 33) and the semiconductor region 31 are annular (or tubular) in shape. The passivation structure 32 surrounds the semiconductor region 31, and the semiconductor region 31 in turn surrounds the active region 30' of the substrate 30. In other words, the passivation structure 32 is not located at the center of the diode 3, but at the periphery of the diode 3. Therefore, the passivation structure 32 is described as a peripheral structure.

[0124] Similar to the Figure 3 embodiment, the peripheral passivation structure 32 can include a first dielectric layer 321 and a first charged layer 322 (the first charged layer 322 is separated from the semiconductor region 31 by the first dielectric layer 321). Advantageously, the peripheral passivation structure 32 further includes an opaque material layer 323, which is separated from the semiconductor region 31 by the first charged layer 322 and the first dielectric layer 321 to reduce optical crosstalk with one or more adjacent diodes.

[0125] Alternatively, the peripheral passivation structure 32 can include a first dielectric layer 321 and a first electrode 322', as shown in the Figure 5 embodiment. Then, the optical crosstalk between adjacent diodes is reduced by forming the first electrode 322' with an opaque (conductive) material (such as metal).

[0126] In both cases, the peripheral passivation structure 32 then realizes the electrical insulation function of the peripheral isolation structure 38 described in Figure 3 and Figure 5 and advantageously restricts the optical crosstalk function (in the presence of the opaque material layer).

[0127] The advantage of this embodiment is that only one (annular) trench needs to be formed instead of two.

[0128] The diode 3 can here include only a single first contact pad 361, which is preferably electrically connected to the substrate 30 through the first contact region 371. The first contact pad 361 is advantageously located at the center of the upper surface of the diode 3 (the upper surface of the first electric field reducing layer 34 or the upper surface of the active part of the substrate 30).

[0129] According to any of the above-described embodiments, several diodes 3 can be combined in an array in a photodetector. Each diode 3 then forms a pixel of the array, called a SPAD pixel. Different diodes 3 share the same substrate 30. Each diode 3 includes an active region 30' of the substrate 30, a semiconductor region 31 in contact with the active region 30' (thus forming a PN junction), and a capacitive effect passivation structure 32. The active region 30' of the substrate 30 is defined by Figure 3 and Figure 5 the peripheral isolation structure 38, or is defined by Figure 6 the peripheral passivation structure 32. Two adjacent pixels (in a row or a column of the array) can share a part of the opaque material layers 323, 383 that perform the function of an optical insulator.

[0130] Figure 7 An example of a photodetector including an array of multiple diodes 3 or SPAD pixels (here 4) is shown in a top view. In this example, the diodes 3 adopt the configuration described in combination with Figure 3 . The active region 30' is preferably square in a top view, and the active region 30' is, for example, between 2 μm and 6 μm on the side. Each diode 3 includes four first semiconductor regions 371 (and four first contact pads) located at the four corners of the active region 30' in order to balance the electric field and charge collection.

[0131] In addition to the array of diodes 3, the photodetector can further include a circuit for biasing the diodes 3 (biasing the diodes 3 to a voltage higher than their avalanche voltage), a readout circuit configured to detect the avalanche of one or more diodes 3 (thus detecting the voltage pulses output from the diodes), and a quenching circuit (the function of which is to interrupt the avalanche of one or more diodes once the avalanche of one or more diodes is triggered). Since the above-described diode embodiments are compatible with the auxiliary circuits of known SPAD photodetectors, these auxiliary circuits are not shown in the drawings and are not described in detail.

[0132] For the diodes 3 according to Figure 3 or Figure 5 , the readout circuit and the quenching circuit are advantageously electrically connected to the second contact pad 362 of each diode 3 (or electrically connected to the second contact region 372), and thus electrically connected to the semiconductor region 31. Since the surface area of the semiconductor region 31 is smaller compared to other electrodes or doped regions of the diode, the semiconductor region 31 constitutes an electrode with the lowest capacitance. For the diodes 3 according to Figure 6 , the readout circuit and the quenching circuit are advantageously electrically connected to the first contact pad 361 of each diode 3 (or the first contact region 371).

[0133] The auxiliary circuit of the photodetector can be integrated in an integrated circuit in complementary metal oxide semiconductor (CMOS) technology. This integrated circuit is advantageously bonded to the array of diodes 3, preferably bonded to the array of diodes 3 on the front of the substrate 30 (for back-illumination of the diodes).

[0134] A method of manufacturing the diode 3 will now be described. Figures 8A to 8I Schematically represents the steps S1 to S9 of a preferred embodiment of the method of manufacturing the diode 3 enabling Figure 3 to be obtained.

[0135] Figure 8A Step S1 of etching the first trench 33 in the substrate 30 through the etching mask 80 is shown. The first trench 33 has a diameter, for example, between 250 nm and 1 μm and a depth between 5 μm and 25 μm. The etching mask 80 is preferably a hard mask (e.g., made of oxide).

[0136] The first trench 33 is preferably etched from the upper surface of a stack including a first electric field reducing layer 34, the substrate 30, and a second electric field reducing layer 35 (not shown). This stack may also include a support layer / substrate (not shown) from which the other layers 34, 30, 35 have been formed (e.g., by epitaxy). The first trench 33 passes through the first electric field reducing layer 34, the substrate 30 and terminates at or in the second electric field reducing layer 35.

[0137] Figure 8B and Figure 8C Steps S2 and S3 in

[0138] relate to the formation of the semiconductor region 31 from the first trench 33. Figure 8B In 19 cm -3 (or 5×10 19 cm -3 ) to avoid obtaining too strong an electric field in the PN junction.

[0139] Then, inFigure 8C In step S3, diffusion annealing is performed to laterally diffuse the doped impurities from the doped semiconductor layer 81 into the substrate 30, thereby obtaining the semiconductor region 31. Preferably, the doped impurities are diffused over a distance d between 100 nm and 1 μm, which is measured from the peripheral side surface of the first trench 33.

[0140] Therefore, when the doped semiconductor layer 81 covers the entire peripheral side surface of the first trench 33, the semiconductor region 31 is in an annular form surrounding the first trench 33 (the ring has a cross-section with a width l = d between 100 nm and 1 μm).

[0141] The diffusion annealing is preferably performed at a temperature between 800 degrees Celsius (°C) and 1100 °C, and the duration of the diffusion annealing can be between 10 seconds (s) and 90 minutes (min).

[0142] The diffusion annealing has the following effects: enabling smooth doping of the semiconductor region 31 to weaken the electric field (thereby avoiding interband tunneling) and moving the depletion region of the PN junction away from the etching region of the first trench 33.

[0143] In an alternative embodiment of steps S2 and S3, the semiconductor region 31 is formed by vapor-phase diffusion doping from the side surface of the first trench 33.

[0144] Figure 8D Optional step S4 of the manufacturing method is shown. In step S4, an additional doped semiconductor layer 82 (referred to as a junction layer) is formed at the junction between the semiconductor region 31 and the first trench 33 to enhance the passivation of defects caused by etching the first trench 33 (the passivation is achieved by means of a first charge accumulation layer formed by the passivation structure 32). The thickness of the additional doped conductive layer 82 is, for example, between 25 nm and 200 nm. The concentration of the doped impurities in the additional doped conductive layer 82 is advantageously greater than or equal to 5×10 18 cm -3 (or 5×10 18 cm -3 ).

[0145] Figure 8E and Figure 8F Steps S5 and S6 are related to the formation of the capacitive effect passivation structure 32.

[0146] In Figure 8E step S5, a first dielectric layer 321 is formed on at least a portion of the peripheral side surface of the first trench 33 and preferably on the entire peripheral side surface of the first trench 33. The first dielectric layer 321 is preferably formed by thermal oxidation of the material of the semiconductor region 31. The thickness of the first dielectric layer 32 is, for example, between 1 nm and 5 nm.

[0147] Then, in S6 (see Figure 8F ), the remaining portion (core) of the first trench 33 is filled with a charged material to form the first charged layer 322. The technique used can be Atomic Layer Deposition (ALD), which is a conformal deposition technique.

[0148] After removing the etch mask 80, the passivation structure 32 is complete and can be used as such. Then, the method subsequently includes the step of forming a second contact region 372 in the semiconductor region 31.

[0149] However, by forming the second contact region 372 in the first trench 33, the integration can be further advanced to minimize the surface area occupied by the diode.

[0150] Therefore Figures 8G to 8I Steps S7 to S9 in

[0151] After the step S6 of filling the first trench 33 with a charged material, the method includes step S7 represented by Figure 8G , and step S7 includes etching the upper part (which is called "notch") of the first charged layer 322. The etched portion of the first charged layer 322 can have a thickness between 50 nm and 200 nm. The etching of the first charged layer 322 is preferably selective with respect to the first dielectric layer 321.

[0152] Then, in S8 (see Figure 8H ), the first dielectric layer 321 is etched in the upper part of the first trench 33 until the side surface (part) of the semiconductor region 31 is exposed. The etching of the first dielectric layer 321 is preferably selective with respect to the semiconductor region 31. Advantageously, the hard mask 80 (both the first dielectric layer 321 and the hard mask 80 can especially be made of an oxide (such as SiO 2 )) is removed simultaneously.

[0153] Finally, in S9 (see Figure 8I ), (as the charged material is evacuated) a doped semiconductor material (such as doped polysilicon) is deposited into the upper part of the first trench 33, thereby filling the first trench 33 and forming the second contact region 372. The doped semiconductor material can be deposited so as to form a planar surface having an upper surface of the stack (or, in the case of the absence of the first electric field reducing layer 34, the upper surface of the substrate). Alternatively, the deposition can form an excess thickness on the upper surface of the stack, in which case a planarization operation (such as by chemical mechanical polishing) is performed to obtain a planar surface having an upper surface of the stack.

[0154] It can be manufactured by replacing the charged material with a conductive material (e.g., metal, doped polysilicon) in step S6 of Figure 8F to form the electrode 322' and omitting the subsequent steps S7 to S9. As an alternative, the method will include, for example, the step of forming a second contact region 372 in the semiconductor region 31 by implanting doped impurities. Figure 5 The semiconductor region 31 and the capacitive effect passivation structure 32 (obtained by any method according to the above method) together form a structure called a Diffused Capacitive Deep Trench (DCDT).

[0155] The method of manufacturing the diode 3 according to

[0156] or Figure 3 also includes the step of forming a peripheral isolation structure 38 that defines the active region 30' of the substrate 30. The peripheral isolation structure 38 can be formed in a manner similar to the capacitive effect passivation structure 32 by etching a second trench 39 in the substrate 30 (and the first electric field reducing layer 34, if applicable), and then filling the second trench 39 continuously with the following layers: Figure 5 - A second dielectric layer 381;

[0157] - A second charged layer 382 or a second electrode 382'; and advantageously

[0158] - A layer of opaque material 383.

[0159] The peripheral isolation structure 38 is preferably formed after the capacitive effect passivation structure 32 (i.e., after step S6 of

[0160] ). This relaxes the restrictions on forming the peripheral isolation structure 38, and the peripheral isolation structure 38 does not have to withstand the high thermal budget required for forming the capacitive effect passivation structure 32. In particular, this allows the use of a metal opaque layer in the peripheral isolation structure 38. Figure 8F The first contact region 371 and the second contact region 372 are preferably formed as late as possible in the manufacturing method (but before the so-called metallization step of forming the contact pads), i.e., after forming the capacitive effect passivation structure 32 and the peripheral isolation structure 38. This limits the thermal budget embodied in these regions and limits the diffusion of the doped impurities in these regions.

[0161] ​

Claims

1. A single photon avalanche diode (3), comprising: - a semiconductor substrate (30) doped with a first conductivity type and having a first face (30a) and a second face (30b) opposite to the first face (30a); - a peripheral isolation structure (38), the peripheral isolation structure (38) defining an active area (30') of the semiconductor substrate (30), the peripheral isolation structure (38) extending from the first surface (30a) to the second surface (30b) in the semiconductor substrate (30); - a semiconductor region (31) doped with a second conductivity type opposite to the first conductivity type, the semiconductor region (31) extending from the first face (30a) to the second face (30b) in the active area of ​​the semiconductor substrate (30); and - a capacitive effect passivation structure (32), wherein the capacitive effect passivation structure (32) is arranged in a first trench (33), wherein the first trench (33) extends in the semiconductor region (31), the capacitive effect passivation structure (32) extends in contact with the semiconductor region (31), and the capacitive effect passivation structure (32) is configured to form a first charge accumulation layer in the semiconductor region (31) at a junction with the first trench (33).

2. The diode (3) according to claim 1, wherein The capacitance effect passivation structure (32) comprises a first dielectric layer (321) and a first charged layer (322), wherein the first charged layer (322) is separated from the semiconductor region (31) by the first dielectric layer (321).

3. The diode (3) according to claim 1, wherein: The capacitance effect passivation structure (32) comprises a first dielectric layer (321) and an electrode (322'), wherein the electrode (322') is separated from the semiconductor region (31) by the first dielectric layer (321).

4. The diode (3) according to claim 1, wherein: The peripheral isolation structure (38) is disposed in the second trench (39), and the peripheral isolation structure (38) is configured to form a second charge accumulation layer in the semiconductor substrate (30) at an interface with the second trench (39).

5. The diode (3) according to claim 4, wherein: The peripheral isolation structure (38) comprises a second dielectric layer (381) and a second charged layer (382), wherein the second charged layer (382) is separated from the active region (30') of the semiconductor substrate (30) by the second dielectric layer (381).

6. The diode (3) according to claim 5, wherein: The peripheral isolation structure (38) further comprises an opaque material layer (383), wherein the opaque material layer (383) is separated from the active region (30') of the semiconductor substrate (30) by the second charged layer (382) and the second dielectric layer (381).

7. The diode (3) according to any one of claims 1 to 6, wherein: The semiconductor region (31) surrounds the capacitive effect passivation structure (32).

8. The diode (3) according to any one of claims 1 to 7, further comprising a contact region (372) of the semiconductor region (31), wherein the contact region (372) is arranged on the capacitive effect passivation structure (32) located in the first trench (33).

9. A method for manufacturing a single photon avalanche diode (3), comprising the following steps: - etching a first trench (33) in a semiconductor substrate (30) doped with a first conductivity type and having a first face (30a) and a second face (30b) opposite to the first face, the first trench extending from the first face to the second face; - after etching the first trench (33), forming a semiconductor region (31), the semiconductor region (31) being doped with a second conductivity type opposite to the first conductivity type, the semiconductor region (31) being formed from the first trench, being partially defined by the first trench (33), and extending from the first face (30a) to the second face (30b) in the semiconductor substrate (30); - forming a capacitive effect passivation structure (32) in the first trench (33), the capacitive effect passivation structure (32) being configured to form a first charge accumulation layer in the semiconductor region (31) at a junction with the first trench (33); and - forming a peripheral isolation structure (38) which defines an active area (30') of the semiconductor substrate (30), the peripheral isolation structure (38) extending from the first face (30a) to the second face (30b) in the semiconductor substrate (30).

10. The method according to claim 9, wherein: Forming the semiconductor region (31) comprises the following sub-steps: - epitaxially forming a doped semiconductor layer (81) on the side surface of the first trench (33), wherein the doped semiconductor layer (81) includes doped impurities; and - performing diffusion annealing to laterally diffuse the doping impurities from the doped semiconductor layer (81) into the semiconductor substrate (30).

11. The method according to claim 9, wherein: The semiconductor region (31) is formed from the side surface of the first trench (33) by vapor phase diffusion doping.

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