Three-dimensional memory, methods of making the same, and memory systems having the same

Abstract

The application provides a three-dimensional memory, a manufacturing method thereof, and a storage system with the same. The three-dimensional memory comprises a first substrate with a gate stack structure on a surface, the gate stack structure comprising a plurality of control gate structures arranged at intervals in a direction away from the first substrate; a plurality of contact units penetrating into the gate stack structure in a direction close to the first substrate and arranged in a first direction, each contact unit penetrating into control gate structures at different layers, and each contact unit comprising a plurality of contacts distributed in a second direction, the contacts in adjacent contact units being at least partially staggered. The application not only saves the area required for arranging the contact holes, but also expands the process window of the contact holes for arranging the contacts, reduces the process difficulty of the contact holes, thereby reducing the contact hole defects and the residual photoresist caused by the manufacturing difficulty of the contact holes, and improving the device performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a three-dimensional memory, a method for manufacturing the same, and a storage system having the same. Background Technology

[0002] In existing technologies, the main function of flash memory is to retain stored information for a long time without power. It has advantages such as high integration, fast access speed, and ease of erasure and rewriting, and is therefore widely used in electronic products. In order to further improve the bit density of flash memory while reducing bit cost, 3D NAND memory has been proposed.

[0003] Currently, 3D NAND memories typically employ a vertically stacked multi-layer data storage cell structure to achieve a stacked 3D NAND memory architecture. This stacked 3D NAND memory structure generally includes alternating layers of control gate structures and isolation layers, as well as a channel structure running through these layers. However, other circuits, such as decoders, page buffers, and latches, are logic circuits formed using CMOS devices, whose fabrication processes cannot be integrated with 3D NAND devices. Currently, different processes are used to form the 3D NAND memory array and the logic circuits, and then bonding the two together using bonding technology.

[0004] To achieve bonding between 3D NAND devices and CMOS devices, a dielectric layer is typically applied to the stacked structure, forming contact holes that penetrate to each control gate structure. Conductive material is then filled into these contact holes to bring out word lines. As storage density continues to increase, wafer utilization becomes more efficient, leading to smaller photolithography windows in the contact hole fabrication process. This increases the difficulty of contact hole fabrication and can even result in defects or photoresist residue that can negatively impact device performance. Summary of the Invention

[0005] The main objective of this application is to provide a three-dimensional memory, its manufacturing method, and a memory system having the same, in order to solve the problem that the manufacturing process of contact holes in the memory can easily affect the device performance.

[0006] To achieve the above objectives, according to one aspect of this application, a three-dimensional memory is provided, comprising: a first substrate having a gate stack structure on its surface, the gate stack structure including a multilayer control gate structure spaced apart along a direction away from the first substrate; a plurality of contact units extending into the gate stack structure along a direction close to the first substrate and arranged along a first direction, each contact unit extending into a control gate structure located in a different layer, each contact unit including a plurality of contacts distributed along a second direction, the contacts in adjacent contact units being at least partially staggered.

[0007] Furthermore, the contact portions in adjacent contact portion units are all staggered.

[0008] Furthermore, adjacent contact units are arranged at equal intervals along the first direction.

[0009] Furthermore, in the same contact unit, adjacent contact portions are spaced at equal intervals.

[0010] Furthermore, the shortest distance between adjacent contact parts in the same contact part unit is H1, and the shortest distance between contact parts in adjacent contact part units is H2, where H1 = H2.

[0011] Furthermore, the projections of the contact portions in the same contact portion unit onto the control gate structure have the same area.

[0012] Furthermore, each contact unit has the same number of contact parts.

[0013] Furthermore, the first direction is perpendicular to the second direction.

[0014] Furthermore, the three-dimensional memory also includes: an interlayer dielectric layer covering the side of the gate stack structure away from the first substrate, with each contact unit penetrating the interlayer dielectric layer to different control gate structures; and a plurality of gate gaps, each gate gap sequentially penetrating the interlayer dielectric layer and the gate stack structure to the first substrate, and each gate gap being spaced apart along a first direction, with at least one contact unit disposed between adjacent gate gaps.

[0015] Furthermore, each gate gap includes a plurality of first gap segments distributed along the second direction, each first gap segment being provided in correspondence with each contact portion in the adjacent contact portion unit, and the sidewall surface of each first gap segment being convex.

[0016] Furthermore, the gate stack structure includes a core memory region and a non-core memory region, and the three-dimensional memory also includes a channel structure extending through the core memory region to the first substrate.

[0017] Furthermore, the three-dimensional memory also includes: a second substrate having CMOS devices on its surface; and a bonding portion for connecting the CMOS devices to the contact portion.

[0018] According to another aspect of this application, a method for fabricating the aforementioned three-dimensional memory is provided, comprising the following steps: providing a first substrate having a stacked body on its surface, the stacked body including a sacrificial layer and an isolation layer alternately stacked in a direction away from the first substrate; forming a plurality of contact units extending into the stacked body in a direction close to the first substrate and arranged in a first direction, such that each contact unit extends into a sacrificial layer located in a different layer, each contact unit including a plurality of contact portions distributed in a second direction, and the contact portions in adjacent contact units being at least partially staggered; replacing the sacrificial layer with a control gate structure, such that the contact units make corresponding contact with the control gate structure.

[0019] Further, the step of forming the contact portion includes: forming an interlayer dielectric layer covering the stack on a first substrate; sequentially etching the interlayer dielectric layer and the stack to form a plurality of contact hole units distributed along a first direction, each contact hole unit penetrating to a different sacrificial layer, and each contact hole unit including a plurality of contact holes distributed along a second direction; forming a contact portion in the contact hole so that the contact portion is in contact with the sacrificial layer.

[0020] Furthermore, the above-mentioned fabrication method further includes the following steps: sequentially etching the interlayer dielectric layer and the stack to form a plurality of gate gaps extending through the first substrate, each gate gap being spaced apart along a first direction, and at least one contact unit being provided between adjacent gate gaps; after the step of forming the gate gaps, the sacrificial layer is replaced with a control gate structure to form a gate stack structure.

[0021] According to another aspect of this application, a storage system is also provided, including a controller and a three-dimensional memory, the three-dimensional memory being configured to store data, the controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory, the three-dimensional memory being the three-dimensional memory described above, or the three-dimensional memory being prepared by the three-dimensional memory manufacturing method described above.

[0022] The present application provides a three-dimensional memory. Since each contact unit in the three-dimensional memory extends through a control gate structure located on different layers and is arranged along a first direction, and each contact unit includes multiple contacts distributed along a second direction, with the contacts in adjacent contact units being staggered, compared to the prior art where contact holes are arranged in an array, more contact holes can be set within the same unit area, saving the area required for contact hole arrangement. Furthermore, with the same number of contact holes, the distance between the staggered contact holes is greater, expanding the process window for setting each contact hole, reducing the process difficulty of the contact holes, and thus reducing contact hole defects and photoresist residue caused by the difficulty in fabricating the contact holes, thereby improving device performance. Attached Figure Description

[0023] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0024] Figure 1 A top view of a three-dimensional memory provided in an embodiment of this application is shown.

[0025] Figure 2 A top view of another three-dimensional memory structure provided in an embodiment of this application is shown;

[0026] Figure 3 It shows Figure 1 Or, the schematic diagram of the cross-sectional structure of the three-dimensional memory in direction A provided by 2;

[0027] Figure 4 It shows Figure 1 Or, the schematic diagram of the cross-sectional structure of the three-dimensional memory in the B direction provided in option 2;

[0028] Figure 5 A flowchart illustrating a method for fabricating a three-dimensional memory according to an embodiment of this application is shown.

[0029] Figure 6 This illustration shows a schematic cross-sectional structure of the substrate after providing a first substrate with a stacked body on its surface in the fabrication method of the three-dimensional memory provided in this application embodiment;

[0030] Figure 7 It shows a formation that extends through to Figure 7 A schematic diagram of the contact holes of the stack and the substrate cross-section structure extending through the gate gap to the first substrate;

[0031] Figure 8 A kind of Figure 7 The diagram shows a top view of the substrate structure.

[0032] Figure 9 Another one is shown Figure 7 The diagram shows a top view of the substrate structure.

[0033] Figure 10 It shows Figure 8 Or, as shown in Figure 9, a schematic diagram of the cross-sectional structure of the substrate in direction A;

[0034] Figure 11 It shows in Figure 7 A schematic diagram of the cross-sectional structure of the substrate after the contact portion is formed in the contact hole;

[0035] Figure 12 It shows Figure 11The diagram shows a cross-sectional view of the substrate along direction A.

[0036] Figure 13 It shows that Figure 11 The diagram shows a cross-sectional structure of the substrate after the sacrificial layer has been replaced with a control gate structure.

[0037] Figure 14 It shows Figure 13 The diagram shows a cross-sectional view of the substrate along direction A.

[0038] Figure 15 It shows in Figure 13 A schematic diagram of the substrate cross-sectional structure after a common source electrode is formed in the gate gap;

[0039] Figure 16 It shows Figure 15 The diagram shows a cross-sectional view of the substrate along direction A.

[0040] Figure 17 A schematic diagram of the connection relationship of a storage system provided according to an embodiment of this application is shown;

[0041] Figure 18 A schematic diagram of the structure of a mobile phone provided according to an embodiment of this application is shown.

[0042] The above figures include the following reference numerals:

[0043] 10. First substrate; 20. Gate stack structure; 210. Control gate structure; 220. Isolation layer; 230. Sacrificial layer; 40. Contact unit; 400. Contact hole unit; 401. Contact; 410. Contact hole; 411. Conductive part; 421. Insulating part; 50. Gap segment; 510. Gate gap; 60. Interlayer dielectric layer; 1000. Three-dimensional memory; 2000. Controller; 3000. Host; 4000. Chip; 10000. Mobile phone; 20000. Storage system. Detailed Implementation

[0044] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0045] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0046] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0047] In some embodiments, the contact holes used to lead out word lines in a three-dimensional memory are typically distributed in a matrix, resulting in a smaller photolithography window in the process of fabricating the contact holes. This increases the difficulty of fabricating the contact holes, which in turn leads to defects in the contact holes or photoresist residue, thus affecting the device performance.

[0048] The inventors of this application have researched the above-mentioned problems and proposed a three-dimensional memory, such as... Figures 1 to 4 As shown, it includes: a first substrate 10 having a gate stack structure 20 on its surface, the gate stack structure 20 including multilayer control gate structures 210 spaced apart along a direction away from the first substrate 10; a plurality of contact units 40 extending into the gate stack structure 20 along a direction close to the first substrate 10 and arranged along a first direction, each contact unit 40 extending into the control gate structure 210 located in a different layer, each contact unit 40 including a plurality of contact portions 401 distributed along a second direction, the contact portions 401 located in adjacent contact units 40 being at least partially staggered.

[0049] Because the contacts in adjacent contact units of this three-dimensional memory are staggered, compared with the prior art where the contact holes are arranged in an array, more contact holes can be set in the same unit area, saving the area required for contact hole arrangement. Furthermore, with the same number of contact holes, the distance between adjacent staggered contact holes can be increased, thereby expanding the process window for setting each contact hole, reducing the process difficulty of contact holes, and thus reducing contact hole defects and photoresist residue caused by the difficulty in fabricating contact holes, thereby improving device performance.

[0050] The material of the first substrate 10 can be single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide and other group III-V compounds.

[0051] The aforementioned gate stack structure 20 includes a control gate structure 210 and an isolation layer 220 alternately stacked along a direction away from the first substrate 10, such as... Figure 1 As shown, those skilled in the art can reasonably set the number of layers of the control gate structure 210 and the isolation layer 220 according to actual needs. The isolation layer 220 can be SiO2, but is not limited to the above type. Those skilled in the art can also reasonably select the type of the isolation layer 220.

[0052] The control gate structure 210 described above includes a gate layer located between adjacent isolation layers 220. The gate material forming the gate structure is typically a metal, and may be selected from one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.

[0053] In an optional embodiment, the control gate structure 210 further includes a high-k dielectric layer, at least a portion of which is disposed between the gate layer and the channel structure to form a gate dielectric layer. A contact portion 401 passes through the high-k dielectric layer and contacts the gate layer. The high-k dielectric layer and the gate layer together constitute the control gate structure 210. Here, the high-k dielectric layer refers to a dielectric material with a high dielectric constant. The material forming the high-k dielectric can be selected from one or more of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, and BaSrTiO.

[0054] In some optional embodiments, the gate stack structure 20 includes a core memory region and a non-core memory region, and the contact unit 40 may be disposed in the core memory region or in both the core memory region and the non-core memory region.

[0055] The aforementioned core memory area is used to set up a channel array. The channel array may include a channel structure that extends through the first substrate 10 and corresponds one-to-one with the channel holes. The aforementioned non-core memory area may also have multiple channel structures distributed to form a pseudo-channel array, which is used to support the isolation layer when the control gate structure is replaced.

[0056] The aforementioned channel structure may include a functional layer and a channel layer covering the inner surface of the channel hole. When the channel structure to be formed is a charge trapping type channel structure, the aforementioned functional layer may include a charge blocking layer, a charge trapping layer and a tunneling layer sequentially stacked on the sidewall of the channel hole.

[0057] Those skilled in the art can make reasonable selections of the materials for the above-mentioned functional layers and channel layers. For example, the material of the charge blocking layer can be SiO2, the material of the charge trapping layer can be SiN, the material of the tunneling layer can be SiO2, and the material of the channel layer can be polycrystalline silicon.

[0058] In an optional embodiment, the channel structure may further include a dielectric filling layer disposed in the channel hole, with the channel layer and the functional layer sequentially surrounding the dielectric filling layer to form the channel structure. The dielectric material forming the dielectric filling layer may be SiO2, but is not limited to the above-mentioned type. Those skilled in the art can reasonably select the material of the dielectric filling layer, and this application does not make specific limitations.

[0059] Multiple contact units 40 extend into the non-core storage area along a direction close to the first substrate 10. Each contact unit 40 includes multiple contacts 401 distributed along a second direction. In an optional embodiment, such as... Figure 3 and Figure 4 As shown, the side of the gate stack structure 20 away from the first substrate 10 is covered with an interlayer dielectric layer 60. The interlayer dielectric layer 60 has a plurality of contact holes that penetrate to different control gate structures 210. The contact portions 401 in the contact portion unit 40 are correspondingly disposed in the contact holes and contact the control gate structure 210.

[0060] The aforementioned contact portion 401 may include a conductive portion 411 that contacts the control gate structure 210 and an insulating portion 421 located between the conductive portion 411 and the contact hole, such as Figure 3 and Figure 4 As shown. For example, the material of the insulating part 421 is SiO2, and the material forming the conductive part 411 is usually a metal, which can be selected from one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni.

[0061] In the above embodiments, the material of the interlayer dielectric layer 60 can be a conventional insulating material. For example, the interlayer dielectric layer 60 is a SiO2 layer.

[0062] In one optional embodiment, the contact portions in adjacent contact portion units 40 are staggered, such as... Figure 1 and Figure 2 As shown. The above configuration method is beneficial for expanding the process window for more or even all contact holes, thereby further reducing the processing difficulty of contact holes.

[0063] In one optional embodiment, adjacent contact units 40 are arranged at equal intervals along the first direction A, such as... Figure 1 and Figure 2 As shown. The above arrangement not only facilitates the design of the photomask in the photolithography process of the contact holes, but also enables the photolithography windows of multiple contact holes arranged adjacent to each other along the first direction A to expand uniformly. This avoids the situation where some adjacent contact holes have large photolithography windows while others have small photolithography windows, thereby reducing the difficulty of the photolithography process and further avoiding photoresist residue in the contact holes after the photolithography process.

[0064] In an optional embodiment, adjacent contact portions 401 are arranged at equal intervals within the same contact portion unit 40, such as... Figure 1 and Figure 2 As shown. The above arrangement not only facilitates the design of the photomask in the photolithography process of the contact holes, but also enables the photolithography windows of adjacent contact holes arranged along the second direction B to expand uniformly. This avoids the situation where some adjacent contact holes have large photolithography windows while others have small photolithography windows, thereby reducing the difficulty of the photolithography process and further avoiding photoresist residue in the contact holes after the photolithography process.

[0065] In one embodiment of this application, in the same contact unit 40, adjacent contact portions 401 are equally spaced, and the shortest distance between adjacent contact portions 401 is H1. In adjacent contact units 40, the shortest distance between contact portions 401 is H2, where H1 = H2. Figure 1 and Figure 2 As shown. The above arrangement not only facilitates the design of the photomask in the photolithography process of the contact holes, but also enables the photolithography windows of the contact holes adjacent to each other along the first direction A and the second direction B to be uniformly expanded. This avoids the situation where some adjacent contact holes have large photolithography windows while others have small photolithography windows, thereby reducing the difficulty of the photolithography process and further avoiding photoresist residue in the contact holes after the photolithography process.

[0066] In an optional embodiment, the projections of the contacts 401 in the same contact unit 40 onto the gate stack structure 20 have the same area, such as... Figure 1 and Figure 2 As shown. By making the projection of each contact portion 401 have the same area, it is not only convenient to design the photomask in the photolithography process of adjacent contact holes, but also possible to adjust the spacing between adjacent contact holes in the same contact portion unit 40 so that the contact holes in the same contact portion unit 40 have photolithography windows of approximately the same size, thereby helping to reduce the difficulty of the photolithography process.

[0067] In one optional embodiment, each contact unit 40 has the same number of contact portions 401. By distributing the same number of contact portions 401 in each row, it is not only convenient to design the photomask in the photolithography process of adjacent contact holes, but also beneficial to adjust the spacing between contact holes in adjacent contact units 40, so that contact holes arranged adjacently along the first direction A can simultaneously have a large photolithography window, thereby helping to reduce the difficulty of the photolithography process.

[0068] Contact units 40 are arranged along a first direction A on the side of the gate stack structure 20 away from the first substrate 10. Each contact unit 40 includes a plurality of contacts 401 distributed along a second direction B. In an optional embodiment, the first direction A is perpendicular to the second direction B, such as... Figure 1 and Figure 2 As shown. The arrangement of the contact portion 401 facilitates the design of the photomask in the photolithography process of adjacent contact holes, which helps to reduce the size of the photomask and thus facilitates the miniaturization of the device size.

[0069] In the aforementioned three-dimensional memory of this application, such as Figure 3 and Figure 4 As shown, the gate stack structure 20 may also have gate gaps 510 extending through the first substrate 10, and each gate gap 510 is spaced apart along the first direction. At least one contact unit 40 is provided between adjacent gate gaps 510. Figure 3 for Figure 1 or Figure 2 The cross-section of the structure shown along direction A. Figure 4 for Figure 1 or Figure 2 The structure shown is a cross-section along direction B. In an optional embodiment, the three-dimensional memory further includes gap segments 50 disposed in each gate gap 510. Exemplarily, the gap segments include common source electrodes.

[0070] The gate gap 510 is used to control the replacement of the gate structure 210. For example, in the process of fabricating a three-dimensional memory, the gate gap 510 penetrates the stacked sacrificial layer and spacer layer, so that the sacrificial layer can have an exposed end face, and the channel hole is located between adjacent gate gaps 510; then, starting from the exposed end face, the sacrificial layer is wet-etched with an etchant to remove the sacrificial layer, and the control gate structure 210 is formed at the position of the corresponding sacrificial layer; and a gap segment 50 is formed in the gate spacer.

[0071] In another alternative implementation, such as Figure 1 As shown, each of the above gate gaps 510 is linear and extends along the second direction B. The manufacturing process of the linear gate gaps 510 is simple and easy to implement.

[0072] In another alternative implementation, such as Figure 2As shown, each gate gap 510 comprises a plurality of gaps distributed along the second direction B. Each gate gap 510 corresponds one-to-one with each contact portion 401 in an adjacent contact portion unit 40, and the sidewall surface of each gate gap 510 is convex. The gate gap 510 can have a large distance from the adjacent contact portion 401, thus meaning that the contact hole or gate gap 510 has a larger photolithographic window, which further reduces the processing difficulty of the contact hole. For example, the cross-section of the sidewall surface of the gate gap 510 in a direction parallel to the surface of the first substrate 10 is a wavy line. The wavy line includes a plurality of arc segments corresponding one-to-one with the contact portion 401, and each arc segment bends toward the corresponding contact portion 401.

[0073] The three-dimensional memory described above in this application may further include a CMOS device disposed on a second substrate, wherein the CMOS device is electrically connected to the contact portion 401 via a bonding portion.

[0074] According to another embodiment of this application, a method for manufacturing the above-mentioned three-dimensional memory is provided, such as... Figure 5 As shown, it includes the following steps:

[0075] A first substrate is provided with a stacked body on its surface, the stacked body comprising sacrificial layers and isolation layers alternately stacked in a direction away from the first substrate;

[0076] A plurality of contact units are formed that extend into the stack along a direction close to the first substrate and are arranged along a first direction, such that each contact unit extends into a sacrificial layer located in a different layer. Each contact unit includes a plurality of contact portions distributed along a second direction, and the contact portions in adjacent contact units are at least partially staggered.

[0077] The sacrificial layer is replaced with a control gate structure so that the contact unit makes corresponding contact with the control gate structure.

[0078] By employing the above-described fabrication method, the contacts in adjacent contact units are staggered. Compared to the prior art where the contact holes are arranged in an array, more contact holes can be set within the same unit area, saving the area required for contact hole arrangement. Furthermore, with the same number of contact holes, the distance between the staggered contact holes is greater, expanding the process window for setting each contact hole, reducing the process difficulty of contact holes, and thus reducing contact hole defects and photoresist residue caused by the difficulty in fabricating contact holes, thereby improving device performance.

[0079] Exemplary embodiments of the method for fabricating a three-dimensional memory according to this application will now be described in more detail. However, these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0080] First, a first substrate 10 with a stacked body on its surface is provided, the stacked body comprising sacrificial layers 230 and insulating layers 220 alternately stacked in a direction away from the first substrate 10, such as Figure 6 As shown.

[0081] In some optional embodiments, the stacked body has a first region and a second region located at least one side of the first region, forming a plurality of channel structures (not shown in the figure) extending through the first substrate 10. The first region is used to form the core memory region in the gate stacked structure through subsequent processes, and the second region is used to form the non-core memory region in the gate stacked structure through subsequent processes. The processes may include, but are not limited to, channel fabrication processes and gate replacement processes. The channel structures in the second region constitute a pseudo-channel array, which serves to support the isolation layer 220 during subsequent control gate structure replacement.

[0082] The aforementioned stack may include multiple sacrificial layers 230 and multiple isolation layers 220 alternately stacked along a direction away from the first substrate 10. The sacrificial layers 230 and the isolation layers 220 can be formed using conventional deposition processes, such as chemical vapor deposition. Those skilled in the art can reasonably determine the number of sacrificial layers 230 and isolation layers 220 according to actual needs. The isolation layer 220 can be SiO2, and the sacrificial layer 230 can be SiN, but is not limited to these types. Those skilled in the art can also reasonably select the types of sacrificial layers 230 and isolation layers 220 according to actual needs.

[0083] In one alternative embodiment, the step of forming a channel structure extending through the first substrate 10 in the stack includes: forming a channel via extending through the first substrate 10 in the stack; sequentially depositing a functional layer and a channel layer on the sidewalls of the channel via; forming a dielectric filling layer in the channel via; and the channel layer and the functional layer sequentially surrounding the dielectric filling layer to form the channel structure.

[0084] The steps for forming the above-mentioned functional layers may include: sequentially forming a charge blocking layer, an electron trapping layer, and a tunneling layer on the sidewall of the channel hole.

[0085] Those skilled in the art can appropriately select the materials for each functional layer and the channel layer. For example, the charge blocking layer can be made of SiO2, the charge trapping layer can be made of SiN, the tunneling layer can be made of SiO2, and the channel layer can be made of polycrystalline silicon. Furthermore, those skilled in the art can use conventional deposition processes to form the aforementioned channel structure, which will not be elaborated further here.

[0086] In one alternative embodiment, the step of forming a dielectric filling layer in the trench includes: depositing a dielectric material on the stack to partially fill the trench with the dielectric material; and anisotropically etching to remove the dielectric material from the surface of the stack and the trench to form the dielectric filling layer.

[0087] The dielectric material mentioned above is typically SiO2, which can be deposited using ALD (atomic layer deposition) or chemical vapor deposition (CVD) processes. The anisotropic etching described above can be a conventional dry etching process. Those skilled in the art can reasonably select the etching gas according to the specific type of dielectric material, and this application does not impose any specific limitations.

[0088] In one alternative embodiment, multiple channel structures extending through the first substrate are formed in both the first and second regions of the stack. The channel structures in the second region form a pseudo-channel array, which serves to support the isolation layer 220 when the control gate structure is replaced.

[0089] After providing a first substrate 10 having a stacked structure on its surface, a plurality of contact units are formed extending into the stacked structure along a direction close to the first substrate 10 and arranged along a first direction, such that each contact unit extends into a sacrificial layer 230 located in a different layer. Each contact unit includes a plurality of contact portions 401 distributed along a second direction, and the contact portions 401 in adjacent contact units 40 are staggered, such as... Figures 7 to 12 As shown.

[0090] In an optional embodiment, the step of forming the contact portion 401 includes: forming an interlayer dielectric layer 60 covering the stack on a first substrate 10; sequentially etching the interlayer dielectric layer 60 and the stack to form a plurality of contact hole units 400 distributed along a first direction A, each contact hole unit 400 penetrating to different sacrificial layers 230, and each contact hole unit 400 including a plurality of contact holes 410 distributed along a second direction B, such as... Figures 7 to 10 As shown, where, Figure 6-7 for Figure 8 or Figure 9 The cross-section of the structure shown along direction B. Figure 10 for Figure 8 or Figure 9The structure shown is a cross-section along direction A; an insulating portion 421 covers the sidewall of the contact hole 410, and a conductive portion 411 is formed in the contact hole 410. The insulating portion 421 is located between the sidewall of the contact hole and the conductive portion 411 and surrounds the conductive portion 411. The conductive portion 411 and the insulating portion 421 constitute a contact portion 401 located in each contact hole 410. The contact portion 401 is in contact with the sacrificial layer 230, as shown in the figure. Figure 11 and Figure 12 As shown; multiple contact portions 401 located in multiple contact holes 410 constitute contact portion unit 40, such as Figure 1 and Figure 2 As shown.

[0091] In the above embodiment, the contact hole 410 can be formed in the interlayer dielectric layer 60 by photolithography and etching processes. For example, photoresist is applied to the surface of the interlayer dielectric layer 60, and a photomask is disposed on the side of the photoresist away from the interlayer dielectric layer 60. The photoresist is a positive photoresist, and the photomask has light-transmitting areas corresponding to the pre-formed contact hole 410. The light-transmitting areas are arranged along a first direction in the photomask, with adjacent rows of light-transmitting areas staggered. Then, the light-transmitting areas in the photomask are transferred to the photoresist through an exposure and development process, forming corresponding hollow areas in the photoresist. The interlayer dielectric layer 60 is etched through these hollow areas to transfer the hollow areas to the interlayer dielectric layer 60 and the second region to form the corresponding contact hole 410.

[0092] After forming the contact portion 401 described above, the sacrificial layer 230 is replaced with a control gate structure 210 to form a gate stack structure 20, with the contact portion unit 40 extending through the gate stack structure 20, such as... Figure 13 and Figure 14 As shown.

[0093] In an optional embodiment, after forming the contact hole 410, the interlayer dielectric layer 60 and the stack are sequentially etched to form a plurality of gate gaps 510 extending through the first substrate 10. Each gate gap 510 is spaced apart along a first direction, and at least one contact hole unit 400 is provided between adjacent gate gaps 510. Figures 8 to 12 As shown; after the step of forming the gate gap 510, the sacrificial layer 230 is replaced with the control gate structure 210 to form the gate stack structure 20, as shown. Figure 13 and Figure 14 As shown.

[0094] By forming a gate gap 510 extending through the first substrate 10 in the stack, the sacrificial layer 230 is made to have an exposed end face located in the gate gap 510. Exemplarily, the step of replacing the sacrificial layer 230 with the control gate structure 210 includes: performing wet etching on the sacrificial layer 230 with an etchant starting from the exposed end face to remove the sacrificial layer 230; and, by removing the sacrificial layer 230, a first gap extending laterally can be formed at the location where the sacrificial layer 230 is removed, and then the gate material is deposited using the first gap as a deposition channel to obtain a gate layer, wherein the deposition process can be atomic layer deposition (ALD).

[0095] The control gate structure 210 may further include a high-k dielectric layer. Before forming the gate layer, the high-k dielectric layer may be first applied to the surface of the first gap. The high-k dielectric layer and the gate layer together constitute the control gate structure 210.

[0096] In another alternative embodiment, before forming the contact holes 410, the interlayer dielectric layer 60 and the stack are sequentially etched to form a plurality of gate gaps 510 extending through the first substrate 10, with each gate gap 510 spaced apart along a first direction; after forming the contact holes 410, the sacrificial layer 230 is replaced with a control gate structure 210 to form a gate stack structure 20, with at least one contact unit 40 disposed between adjacent gate gaps 510, such as... Figure 13 and Figure 14 As shown.

[0097] It should be noted that the process sequence for forming the contact portion 401 and replacing the sacrificial layer 230 with the control gate structure 210 is not limited to the optional embodiments described above. For example, a plurality of gate gaps 510 penetrating to the first substrate 10 can be formed before forming the contact hole 410, and then the sacrificial layer 230 can be replaced with the control gate structure 210 before forming the contact hole 410 penetrating to the gate stack structure 20; alternatively, the contact hole 410 penetrating to the stack can be formed first, then a plurality of gate gaps 510 penetrating to the first substrate 10 can be formed, and the sacrificial layer 230 can be replaced with the control gate structure 210 before finally forming the contact portion 401 in the contact hole 410. This application does not impose specific limitations.

[0098] After replacing the sacrificial layer 230 with the control gate structure 210, a gap segment 50 is formed in the gate gap 510. This gap segment 50 can be formed by filling the gate gap 510 with a dielectric material. In some alternative embodiments, an insulating material is first deposited on the sidewalls of the gate gap 510, and then a conductive material is filled into the gate gap 510, whose sidewalls are covered with insulating material, to form a common source electrode, such as... Figure 15 and Figure 16As shown. The common-source control gate structures 210 are isolated by sidewall insulating layers, and the channel structure forms a common-source connection via the substrate.

[0099] According to one embodiment of this application, a storage system 20000 is also provided. Figure 17 This is an internal block diagram of a storage system 20000 according to an embodiment of this application. For example... Figure 17 As shown, the storage system 20000 may include a three-dimensional memory 1000 and a controller 2000.

[0100] The three-dimensional memory 1000 may be the same as the three-dimensional memory described in any of the above embodiments, and this application will not repeat it further.

[0101] The controller 2000 can control the three-dimensional memory 1000 via channel CH, and the three-dimensional memory 1000 can perform operations based on the control of the controller 2000 in response to requests from the host 3000. The three-dimensional memory 1000 can receive commands CMD and addresses ADDR from the controller 2000 via channel CH and access the region selected from the memory cell array in response to that address. In other words, the three-dimensional memory 1000 can perform internal operations corresponding to commands on the region selected by the address.

[0102] In some implementations, the aforementioned storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0103] This application also provides an electronic device, including the memory structure described above.

[0104] In the above embodiments of this application, the electronic device includes at least one of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device, and power bank. In this embodiment, the memory structure of this application can be used in any electronic device because the memory structure of this application reduces leakage problems caused by defects and improves product reliability; therefore, the performance of electronic devices using this memory structure is further improved. Figure 18 A schematic diagram of the structure of a mobile phone according to an embodiment of this application is shown, such as... Figure 18 As shown, the mobile phone 10000 includes a chip 4000 employing the memory structure of this application.

[0105] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0106] 1. Compared with the prior art where the contact holes of the contact parts are arranged in an array, more contact holes can be set in the same unit area, saving the area required for arranging the contact holes;

[0107] 2. Compared with the existing technology where the contact holes of the contact portion are arranged in an array, it can also make the distance between the staggered contact holes greater while having the same number of contact holes. This expands the process window for setting the contact holes of each contact portion, reduces the process difficulty of the contact holes, and thus reduces contact hole defects and photoresist residue caused by the difficulty of contact hole fabrication, thereby improving device performance.

[0108] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A three-dimensional memory, characterized in that, include: A first substrate having a gate stack structure on its surface, the gate stack structure comprising a multilayer control gate structure spaced apart along a direction away from the first substrate; Multiple contact units extend into the gate stack structure along a direction close to the first substrate and are arranged along a first direction. Each contact unit extends into the control gate structure located in a different layer. Each contact unit includes multiple contact portions distributed along a second direction. The contact portions in adjacent contact units are at least partially staggered. Multiple gate gaps are spaced apart along the first direction, and at least one contact unit is provided between adjacent gate gaps. The cross-section of the sidewall surface of the gate gap in the direction parallel to the surface of the first substrate is a wavy line. The wavy line includes multiple arc segments that correspond one-to-one with the contact portions. Each arc segment bends toward the corresponding contact portion. Each gate gap includes multiple first gap segments distributed along the second direction. Each first gap segment is provided one-to-one with each contact portion in the adjacent contact unit, and the sidewall surface of each first gap segment is convex.

2. The three-dimensional memory according to claim 1, characterized in that, The contact portions located in adjacent contact portion units are all staggered.

3. The three-dimensional memory according to claim 1, characterized in that, The adjacent contact units are arranged at equal intervals along the first direction.

4. The three-dimensional memory according to claim 1, characterized in that, In the same contact unit, adjacent contact portions are arranged at equal intervals.

5. The three-dimensional memory according to claim 4, characterized in that, The shortest distance between adjacent contact portions in the same contact portion unit is H1, and the shortest distance between contact portions in adjacent contact portion units is H2, where H1 = H2.

6. The three-dimensional memory according to any one of claims 1 to 5, characterized in that, The projections of the contact portions in the same contact portion unit onto the control gate structure have the same area.

7. The three-dimensional memory according to any one of claims 1 to 5, characterized in that, Each of the contact units has the same number of contact portions.

8. The three-dimensional memory according to any one of claims 1 to 5, characterized in that, The first direction is perpendicular to the second direction.

9. The three-dimensional memory according to any one of claims 1 to 5, characterized in that, The three-dimensional memory further includes: an interlayer dielectric layer covering the side of the gate stack structure away from the first substrate, each of the contact units penetrating the interlayer dielectric layer to a different control gate structure, and each of the gate gaps sequentially penetrating the interlayer dielectric layer and the gate stack structure to the first substrate.

10. The three-dimensional memory according to claim 9, characterized in that, The gate stack structure includes a core memory region and a non-core memory region, and the three-dimensional memory further includes: A channel structure extends through the core storage area to the first substrate.

11. The three-dimensional memory according to any one of claims 1 to 5, characterized in that, The three-dimensional memory also includes: A second substrate with CMOS devices on its surface; A bonding portion is used to connect the CMOS device to the contact portion.

12. A method for manufacturing a three-dimensional memory according to any one of claims 1 to 11, characterized in that, Includes the following steps: A first substrate having a stacked body on its surface is provided, the stacked body comprising sacrificial layers and isolation layers alternately stacked in a direction away from the first substrate; A plurality of contact units are formed that extend into the stack along a direction close to the first substrate and are arranged along a first direction, such that each contact unit extends into the sacrificial layer located in a different layer. Each contact unit includes a plurality of contact portions distributed along a second direction, and the contact portions in adjacent contact units are at least partially staggered. The interlayer dielectric layer and the stack are sequentially etched to form a plurality of gate gaps extending through the first substrate. Each gate gap is spaced apart along the first direction. At least one contact unit is provided between adjacent gate gaps. The sidewall surface of the gate gap is wavy in a direction parallel to the surface of the first substrate. The wavy line includes a plurality of arc segments corresponding to the contact portions. Each arc segment bends toward the corresponding contact portion. Each gate gap includes a plurality of first gap segments distributed along the second direction. Each first gap segment is provided in a one-to-one correspondence with each contact portion in the adjacent contact unit. The sidewall surface of each first gap segment is convex. After the step of forming the gate gap, the sacrificial layer is replaced with the control gate structure to form the gate stack structure, so that the contact unit makes corresponding contact with the control gate structure.

13. The manufacturing method according to claim 12, characterized in that, The steps for forming the contact portion include: An interlayer dielectric layer covering the stack is formed on the first substrate; The interlayer dielectric layer and the stack are sequentially etched to form a plurality of contact hole units distributed along the first direction, each contact hole unit penetrating to a different sacrificial layer, and each contact hole unit including a plurality of contact holes distributed along the second direction; The contact portion is formed in the contact hole so that the contact portion is in contact with the sacrificial layer.

14. A storage system comprising a controller and a three-dimensional memory, the three-dimensional memory being configured to store data, the controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory, characterized in that... The three-dimensional memory is any one of claims 1 to 11, or the three-dimensional memory is prepared by the method of manufacturing the three-dimensional memory according to any one of claims 12 to 13.

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