Integrated circuit device and method of manufacturing the same

Abstract

The present disclosure relates to integrated circuit devices and methods of manufacturing the same. Gate isolation techniques disclosed herein form gate isolation fins to isolate metal gates of a multi-gate device from one another prior to forming the multi-gate device, and in particular prior to forming the metal gates of the multi-gate device. An exemplary device includes a first multi-gate device having first source / drain features and a first metal gate surrounding a first channel layer, and a second multi-gate device having second source / drain features and a second metal gate surrounding a second channel layer. A gate isolation fin separating the first metal gate and the second metal gate includes a dielectric feature having a first dielectric layer (e.g., a low-k dielectric core) having a first dielectric constant, and a second dielectric layer (e.g., a high-k dielectric shell) surrounding the first dielectric layer. The second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

Description

Technical Field

[0001] This disclosure relates generally to integrated circuit devices, and more specifically to gate isolation techniques for multi-gate devices. Background Technology

[0002] The electronics industry has a growing demand for smaller and faster electronic devices capable of supporting increasingly complex and sophisticated functions. To meet these demands, the integrated circuit (IC) industry has a sustained trend towards manufacturing low-cost, high-performance, and low-power ICs. To date, these goals have been largely achieved by reducing IC size (e.g., the minimum IC feature size), thereby increasing production efficiency and reducing associated costs. However, this miniaturization also increases the complexity of IC manufacturing processes. Therefore, continued advancements in IC devices and their performance require similar progress in IC manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced to improve gate control. Multi-gate devices include a gate structure that partially or completely surrounds a channel region to provide access to the channel region at least on both sides. Exemplary multi-gate devices include fin field-effect transistors (FinFETs) and gate-all-around (GAA) transistors, such as nanowire transistors. Multi-gate devices enable large-scale miniaturization of IC technology, maintain gate control, and mitigate short-channel effects (SCE), while seamlessly integrating with conventional IC manufacturing processes. However, as multi-gate devices continue to shrink, non-self-aligned gate dicing techniques, typically used to isolate the gates of different devices (e.g., the first gate of a first GAA transistor and the second gate of a second GAA transistor) from each other, are hindering the dense packaging of IC features required for advanced IC technology nodes. Therefore, while existing multi-gate devices and the methods used to manufacture them are generally sufficient for their intended purpose, they are not entirely satisfactory in all respects. Summary of the Invention

[0004] According to one aspect of this disclosure, an integrated circuit device is provided, comprising: a first multi-gate device having: a first channel layer disposed between first source / drain features, and a first metal gate surrounding the first channel layer; a second multi-gate device having: a second channel layer disposed between second source / drain features, and a second metal gate surrounding the second channel layer; and a gate isolation fin disposed between the first metal gate and the second metal gate and separating the first metal gate and the second metal gate, wherein the gate isolation fin includes a dielectric feature having: a first dielectric layer having a first dielectric constant, and a second dielectric layer surrounding the first dielectric layer, wherein the second dielectric layer has a second dielectric constant greater than the first dielectric constant.

[0005] According to another aspect of this disclosure, an integrated circuit device is provided, comprising: an isolation feature disposed on a substrate, wherein the isolation feature is disposed between a first fin portion and a second fin portion extending from the substrate; a gate isolation fin disposed on the isolation feature, wherein the gate isolation fin includes an upper dielectric feature and a lower dielectric feature, wherein the upper dielectric feature has a low-k dielectric core surrounded by a high-k dielectric shell; a first multi-gate device having a first channel layer disposed on the first fin portion, a first metal gate surrounding the first channel layer, and a first source / drain feature, wherein the first metal gate is disposed between the first channel layer and the first fin portion; and a second multi-gate device having a second channel layer disposed on the second fin portion, a second metal gate surrounding the second channel layer, and a second source / drain feature, wherein the second metal gate is disposed between the second channel layer and the second fin portion, and wherein the gate isolation fin separates the first metal gate of the first multi-gate device from the second metal gate of the second multi-gate device.

[0006] According to another aspect of this disclosure, a method for manufacturing an integrated circuit device is provided, comprising: forming an isolation feature in a lower portion of a trench; forming a gate isolation fin on the isolation feature, wherein the gate isolation fin is formed in an upper portion of the trench, and the gate isolation fin has an upper dielectric feature and a lower dielectric feature, wherein the upper dielectric feature has a dielectric core having a first dielectric constant, the dielectric core being surrounded by a dielectric shell having a second dielectric constant, wherein the second dielectric constant is greater than the first dielectric constant; and forming a first channel layer, a first metal gate, and a first source. A first multi-gate device with a source / drain feature, wherein a first channel layer is disposed between the first source / drain features and a first metal gate surrounds the first channel layer; and a second multi-gate device having a second channel layer, a second metal gate, and a second source / drain feature, wherein the second channel layer is disposed between the second source / drain features and a second metal gate surrounds the second channel layer, and wherein the gate isolation fin is disposed between the first metal gate of the first multi-gate device and the second metal gate of the second multi-gate device, and separates the first metal gate and the second metal gate. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 This is a flowchart of a method for manufacturing a multi-gate device according to various aspects of this disclosure.

[0009] Figures 2-26 Multi-gate devices according to various aspects of this disclosure at various manufacturing stages (e.g., with) Figure 1 A partial or complete perspective view of the manufacturing stage (as described in the method).

[0010] Figure 27A yes Figure 26 A partial or complete top view of a multi-gate device, and Figures 27B-27E Based on all aspects of this disclosure Figure 27A A partial or complete cross-sectional view of a multi-gate device.

[0011] Figure 28 and Figure 29 These are partial or complete cross-sectional views of a multi-gate device according to various aspects of this disclosure. Detailed Implementation

[0012] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, spatially related terms (e.g., “lower,” “upper,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “upward,” “downward,” “top,” “bottom,” etc.) and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used to facilitate the description of the relationship between one feature and another in this disclosure. These spatially related terms are intended to cover different orientations of the device including the feature. Additionally, when describing numbers or ranges of numbers using terms such as “about,” “approximately,” etc., the terms are intended to cover numbers within a reasonable range (taking into account the variations inherent during manufacturing as understood by those skilled in the art). For example, based on known manufacturing tolerances associated with manufacturing features having characteristics associated with numbers, a number or range of numbers covers a reasonable range including the described number, such as within + / - 10% of the described number. For example, a material layer having a thickness of “about 5 nm” can cover a range from 4.5 nm to 5.5 nm. The size range is nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 10%. Furthermore, this disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for simplicity and clarity and does not in itself prescribe relationships between the various embodiments and / or configurations discussed.

[0013] An exemplary non-self-aligned gate dicing technique may involve forming a mask layer over a gate stack, wherein the mask layer covers a first portion and a second portion of the gate stack, and exposes a third portion of the gate stack via an opening formed in the mask layer. The third portion of the gate stack is disposed between the first portion and the second portion of the gate stack. An etching process is then performed to remove the exposed third portion of the gate stack (e.g., including at least one gate electrode layer and at least one gate dielectric layer), thereby forming a gate opening between the first portion and the second portion of the gate stack that separates the first portion and the second portion. A gate isolation feature, such as a dielectric layer (e.g., a silicon nitride layer), is then formed in the gate opening to provide electrical isolation between the first portion and the second portion of the gate stack, wherein the first portion of the gate stack may be disposed over a first channel layer of a first GAA device (i.e., a first active device region), and the second portion of the gate stack may be disposed over a second channel layer of a second GAA device (i.e., a second active device region).

[0014] The spacing between active device regions (e.g., the first and second channel layers) is intentionally designed to be larger than necessary to compensate for process variations that occur during non-self-aligned gate dicing techniques. For example, etch loading effects and / or other loading effects can reduce critical dimensional uniformity (CDU) on the wafer, causing the width of openings in the mask layer and / or the width of gate openings to exceed target widths at certain locations. This can lead to unintentional exposure and / or damage to the first channel layer, the second channel layer, the first portion of the gate stack, and / or the second portion of the gate stack. In another example, overlay misalignment caused by photolithography processes can cause openings in the mask layer to deviate to the left or right from their intended positions, which can also lead to unintentional exposure and / or damage to the first channel layer, the second channel layer, the first portion of the gate stack, and / or the second portion of the gate stack. The increased spacing required between active device regions to adequately compensate for such process variations hinders compact packaging of the active device regions, thereby reducing the patterning density required for advanced IC technology nodes.

[0015] Therefore, this disclosure proposes a self-aligned gate dicing (isolation) technique for multi-gate devices that allows for smaller spacing (and thus smaller cell height) between active device regions compared to the spacing required between active device regions when implementing a non-self-aligned gate dicing technique. The self-aligned gate dicing technique provides gate isolation fins disposed between a first gate of a first multi-gate device (e.g., a first transistor) and a second gate of a second multi-gate device (e.g., a second transistor), separating the first and second gates. The gate isolation fins have an upper portion and a lower portion, wherein the upper portion has a low-k dielectric core surrounded by a high-k dielectric shell. In some embodiments, the upper portion differs in the channel region and the source / drain region of the multi-gate device. For example, the height of the upper portion in the source / drain region is less than the height of the upper portion in the channel region. In another example, in the source / drain region, the high-k dielectric shell surrounds the low-k dielectric core, rather than surrounding it. In some embodiments, the lower portion includes an oxide layer (core) surrounded by a low-k dielectric layer. In some embodiments, the gate isolation fin is a first gate isolation fin, a first gate is disposed between the first and second gate isolation fins, and a second gate is disposed between the first and third gate isolation fins. The second and third gate isolation fins are similar to the first gate isolation fin in the source / drain region of a multi-gate device. For example, the second and third gate isolation fins have an upper portion and a lower portion, wherein the upper portion has a high-k dielectric shell surrounding a low-k dielectric core. The second and third gate isolation fins differ from the first gate isolation fin in the channel region of a multi-gate device. For example, the second and third gate isolation fins include a lower portion but not an upper portion. In such embodiments, a first metal gate may extend to the top surface of the second gate isolation fin, and a second metal gate may extend to the top surface of the third gate isolation fin. The disclosed gate isolation fins can improve the performance of multi-gate devices (e.g., first and second multi-gate devices). For example, it has been observed that voids tend to form in the high-k dielectric core at the top of the gate isolation fin, and these voids can provide leakage paths between the gate and source / drain contacts of, for example, multi-gate devices, degrading the performance of the multi-gate devices. As described herein, incorporating a low-k dielectric core into the top of the gate isolation fin reduces (and in some embodiments, eliminates) void formation in the gate isolation fin. Therefore, multi-gate devices with the proposed gate isolation fin can exhibit improved speed, gate-drain capacitance, and / or power efficiency compared to multi-gate devices with a high-k dielectric core at the top, and thus improve overall performance. The proposed self-aligned gate dicing technique for multi-gate devices and the resulting multi-gate devices are described in detail below.

[0016] Figure 1 This is a flowchart of a method 100 for manufacturing a multi-gate device according to various aspects of the present disclosure. In some embodiments, method 100 manufactures p-type multi-gate transistors and / or n-type multi-gate transistors. At block 110, method 100 includes forming an isolation feature, such as a shallow trench isolation structure, a deep trench isolation structure, other isolation structures, or combinations thereof, in a lower portion of a trench. In some embodiments, the trench is formed between a first active region for a first multi-gate device and a second active region for a second multi-gate device. At block 115, method 100 includes forming a gate isolation fin over the isolation feature. The gate isolation fin is formed in an upper portion of the trench. The gate isolation fin has an upper dielectric feature and a lower dielectric feature. The upper dielectric feature has a dielectric core with a first dielectric constant surrounded by a dielectric shell with a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. In some embodiments, the dielectric core comprises a low-k dielectric material, and the dielectric shell comprises a high-k dielectric material. Gate isolation fins are disposed between a first active region for a first multi-gate device and a second active region for a second multi-gate device. In some embodiments, the first and second multi-gate devices are formed after the gate isolation fins are formed. For example, a first channel layer, a first metal gate, and / or a first source / drain feature of the first multi-gate device are formed in the first active region, and a second channel layer, a second metal gate, and / or a second source / drain feature of the second multi-gate device are formed in the second active region after the gate isolation fins are formed. Additional steps may be provided before, during, and after method 100, and some of the described steps may be moved, replaced, or eliminated for additional embodiments of method 100. The following discussion illustrates various embodiments of multi-gate based integrated circuit devices that can be manufactured according to method 100.

[0017] Figures 2-26 and Figures 27A-27E The multi-gate device 200 according to various aspects of this disclosure is manufactured at various stages (e.g., with...) Figure 1This is a partial perspective view of part or all of the manufacturing stages associated with method 100. As described herein, the multi-gate device 200 includes a first transistor region 202A and a second transistor region 202B, wherein each transistor region is processed to form at least one transistor therein. In some embodiments, p-type transistors are formed in both the first transistor region 202A and the second transistor region 202B. In some embodiments, n-type transistors are formed in both the first transistor region 202A and the second transistor region 202B. In some embodiments, the p-type transistor (or n-type transistor) in the first transistor region 202A is part of a first complementary transistor (e.g., a first complementary metal-oxide-semiconductor (CMOS) transistor), and the p-type transistor (or n-type transistor) in the second transistor region 202B is part of a second complementary transistor (e.g., a second CMOS transistor). In some embodiments, an n-type transistor is formed in the first transistor region 202A (and may therefore be referred to as an n-type transistor region), and a p-type transistor is formed in the second transistor region 202B (and may therefore be referred to as a p-type transistor region). In some embodiments, the first transistor region 202A and the second transistor region 202B are part of a device region, such as a core region (also called a logic region), a memory region (e.g., a static random access memory (SRAM) region), an analog region, a peripheral region (also called an input / output (I / O) region), a dummy region, and / or other suitable regions of the device. The device region may include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), CMOS transistors, bipolar junction transistors (BJTs), laterally diffused MOS transistors (LDMOS), high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. The multi-gate device 200 may be included in a microprocessor, memory, and / or other IC devices. In some embodiments, the multi-gate device 200 is part of an IC chip, a system-on-a-chip (SoC). Figures 2-26 and Figures 27A-27E For clarity, the present disclosure has been simplified to better understand the inventive concept. Additional features may be added to the multi-gate device 200, and some features described herein may be replaced, modified, or eliminated in other embodiments of the multi-gate device 200.

[0018] Go to Figure 2A fin manufacturing process is performed to form fins extending from a substrate (wafer) 206. For example, fins 208A and 208B (also referred to as fin structures, fin elements, etc.) extend from the substrate 206 after the fin manufacturing process. Each of fins 208A and 208B includes: a substrate portion (i.e., the fin portion 206' of the substrate 206 (also referred to as a substrate extension, substrate fin portion, etched substrate portion, etc.)), a semiconductor layer stack portion disposed on the substrate portion (i.e., a semiconductor layer stack 210 including semiconductor layers 215 and 220), and a patterned layer portion disposed on the semiconductor layer stack portion (i.e., a patterned layer 225 including a pad layer 226 and a mask layer 227). Fins 208A and 208B each extend substantially parallel to each other along the y-direction, and have length in the y-direction, width in the x-direction, and height in the z-direction.

[0019] In some embodiments, the fin fabrication process includes: forming a semiconductor layer stack on a substrate 206 (e.g., depositing semiconductor layers 215 and 220 on the substrate 206), and then performing photolithography and / or etching processes to pattern the semiconductor layer stack and the substrate 206 to form fins 208A, 208B. In some embodiments, semiconductor layers 215 and 220 are epitaxially grown in an alternating and staggered configuration as depicted. For example, a first semiconductor layer 215 is epitaxially grown on the substrate 206, a first semiconductor layer 220 is epitaxially grown on the first semiconductor layer 215, a second semiconductor layer 215 is epitaxially grown on the first semiconductor layer 220, and so on, until the semiconductor layer stack 210 has the desired number of semiconductor layers 215 and 220. In such embodiments, semiconductor layers 215 and 220 may be referred to as epitaxial semiconductor layers. In some embodiments, the epitaxial growth of semiconductor layers 215 and 220 is achieved via molecular beam epitaxy (MBE), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), other suitable epitaxial growth processes, or combinations thereof. The photolithography process may include forming a resist layer on top of the semiconductor layer stack (e.g., by spin coating), performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a development process. During the exposure process, the resist layer is exposed to radiative energy (e.g., ultraviolet (UV) light, deep UV (DUV) light, or extreme UV (EUV) light), wherein, depending on the mask pattern and / or mask type (e.g., binary mask, phase-shift mask, or EUV mask), the mask blocks radiation, transmits radiation, and / or reflects radiation onto the resist layer, thereby projecting an image onto the resist layer corresponding to the mask pattern. Because the resist layer is sensitive to radiation energy, the exposed portions of the resist layer undergo chemical changes, and during the development process, the exposed (or unexposed) portions of the resist layer dissolve, depending on the properties of the resist layer and the properties of the developing solution used in the development process. After development, the patterned resist layer comprises a resist pattern corresponding to the mask. The etching process uses the patterned resist layer as an etching mask to remove portions of the semiconductor layer stack. In some embodiments, the patterned resist layer is formed on a mask layer disposed above the semiconductor layer stack, a first etching process removes portions of the mask layer to form a patterned layer 225 (i.e., a patterned hard mask layer), and a second etching process removes portions of the semiconductor layer stack to form the semiconductor layer stack 210 using the patterned layer 225 as an etching mask. The etching process may include dry etching, wet etching, other suitable etching, or combinations thereof. In some embodiments, the etching process is reactive ion etching (RIE). After the etching process, the patterned resist layer is removed, for example, by a resist stripping process or other suitable process.Alternatively, fins 208A and 208B are formed by multiple patterning processes, such as dual patterning lithography (DPL) processes (e.g., lithography-etch-lithography-etch (LELE) process, self-aligned dual patterning (SADP) process, spacer-dielectric (SID) SADP process, other dual patterning processes or combinations thereof), triple patterning processes (e.g., lithography-etch-lithography-etch-lithography-etch (LELELE) process, self-aligned triple patterning (SATP) process, other triple patterning processes or combinations thereof), other multiple patterning processes (e.g., self-aligned quadruple patterning (SAQP) process) or combinations thereof. Such processes can also provide, for example... Figure 2 The fins 208A and 208B shown have a patterned layer 225, a semiconductor layer stack 210, and a fin portion 206'. In some embodiments, directional self-assembly (DSA) technology is implemented while patterning the semiconductor layer stack 210. Furthermore, in some embodiments, the exposure process can enable maskless lithography, electron beam (e-beam) writing, and / or ion beam writing for patterning the resist layer.

[0020] In the depicted embodiments, substrate 206 comprises silicon. In some embodiments, substrate 206 comprises a basic semiconductor, such as silicon and / or germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Alternatively, substrate 206 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Substrate 206 (including fin portions 206') may include various doped regions, such as p-type doped regions (referred to as p-wells), n-type doped regions (referred to as n-wells), or combinations thereof. In one example, fin portions 206' of fins 208A, 208B include p-wells, wherein n-type transistors are formed, for example, in the first transistor region 202A and the second transistor region 202B. In another example, the fin portion 206' of fins 208A and 208B includes an n-well, wherein a p-type transistor is formed, for example, in the first transistor region 202A and the second transistor region 202B. In yet another example, the fin portion 206' of fin 208A may include a p-well and the fin portion 206' of fin 208B may include an n-well, wherein an n-type transistor is formed, for example, in the first transistor region 202A and a p-type transistor is formed in the second transistor region 202B. In yet another example, the fin portion 206' of fin 208A may include an n-well and the fin portion 206' of fin 208B may include a p-well, wherein a p-type transistor is formed, for example, in the first transistor region 202A and an n-type transistor is formed in the second transistor region 202B. The n-well includes an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. The p-well includes a p-type dopant, such as boron, indium, other p-type dopants, or combinations thereof. In some embodiments, the doped regions (including fin portions 206') in the substrate 206 comprise a combination of p-type and n-type dopants. Various doped regions can be formed directly on and / or within the substrate 206, for example, providing p-well structures, n-well structures, double-well structures, bump structures, or combinations thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes can be performed to form the various doped regions.

[0021] Each semiconductor layer stack 210 is disposed on a corresponding fin portion 206' of the substrate 206 and includes semiconductor layers 215 and 220, which are vertically stacked from the top surface of the substrate 206 in an alternating and / or staggered configuration (e.g., along the z-direction). The composition of semiconductor layer 215 differs from that of semiconductor layer 220 to achieve etch selectivity and / or different oxidation rates during subsequent processing. In some embodiments, semiconductor layer 215 has a first etch rate against an etchant, and semiconductor layer 220 has a second etch rate against an etchant, wherein the second etch rate differs from the first etch rate. In some embodiments, semiconductor layer 215 has a first oxidation rate, and semiconductor layer 220 has a second oxidation rate, wherein the second oxidation rate differs from the first oxidation rate. In the depicted embodiments, semiconductor layers 215 and 220 include different materials, component atomic percentages, component weight percentages, thicknesses, and / or properties to achieve desired etch selectivity during an etching process, such as an etching process for forming a suspended channel layer in a channel region of a multi-gate device 200. For example, in the case where semiconductor layer 215 comprises silicon-germanium and semiconductor layer 220 comprises silicon, the silicon etch rate of semiconductor layer 220 is less than the silicon-germanium etch rate of semiconductor layer 215. In some embodiments, semiconductor layer 215 and semiconductor layer 220 comprise the same material but have different component atomic percentages to achieve etch selectivity and / or different oxidation rates. For example, semiconductor layer 215 and semiconductor layer 220 may comprise silicon-germanium, wherein semiconductor layer 215 has a first silicon atomic percentage and / or a first germanium atomic percentage, and semiconductor layer 220 has a different second silicon atomic percentage and / or a different second germanium atomic percentage. This disclosure contemplates that semiconductor layer 215 and semiconductor layer 220 comprise any combination of semiconductor materials that provide desired etch selectivity, desired oxidation rate difference, and / or desired performance characteristics (e.g., materials that maximize current), including any semiconductor materials disclosed herein.

[0022] As further described below, semiconductor layer 220 or a portion thereof forms the channel region of multi-gate device 200. In the depicted embodiment, each semiconductor layer stack 210 includes three semiconductor layers 215 and three semiconductor layers 220, configured to form three pairs of semiconductor layers disposed on substrate 206, each pair having a corresponding semiconductor layer 215 and a corresponding semiconductor layer 220. After subsequent processing, such a configuration will result in multi-gate device 200 having three channels. However, this disclosure contemplates embodiments of semiconductor layer stack 210 including more or fewer semiconductor layers, depending, for example, on the number of channels required for multi-gate device 200 and / or the design requirements of multi-gate device 200. For example, semiconductor layer stack 210 may include two to ten semiconductor layers 215 and two to ten semiconductor layers 220. In a further description of the embodiments, semiconductor layer 215 has a thickness t1, and semiconductor layer 220 has a thickness t2, wherein thickness t1 and thickness t2 are selected based on fabrication and / or device performance considerations of multi-gate device 200. For example, thickness t1 can be configured to provide a desired distance (or gap) between adjacent channels of the multi-gate device 200 (e.g., between semiconductor layers 220), and thickness t2 can be configured to provide a desired thickness for the channels of the multi-gate device 200. Thicknesses t1 and t2 can be configured to optimize the performance of the multi-gate device 200. In some embodiments, semiconductor layer 220 includes n-type dopant and / or p-type dopant, depending on its corresponding transistor region. In some embodiments, semiconductor layer 220 in a first transistor region 202A may include p-type dopant, and semiconductor layer 220 in a second transistor region 202B may include n-type dopant, and vice versa.

[0023] Fin 208A is disposed between trench 230A and trench 230B, and fin 208B is disposed between trench 230A and trench 230C. Trench 230A is formed between fins 208A and fin 208B. For example, trench 230A has sidewalls formed by fins 208A, sidewalls formed by fins 208B, and a bottom formed by a substrate 206 extending between the sidewalls. (Go to...) Figure 3A liner layer 232 partially filling trenches 230A-230C is formed on the multi-gate device 200. For example, a dielectric liner 235 is formed on fins 208A, 208B and substrate 206, and a silicon liner 240 is formed on the dielectric liner 235, wherein the dielectric liner 235 and the silicon liner 240 form a liner layer 232 partially filling trenches 230A-230C. The dielectric liner 235 and the silicon liner 240 cover substrate 206 and fins 208A, 208B such that the dielectric liner 235 and the silicon liner 240 cover the sidewalls and bottom of trenches 230A-230C. In some embodiments, fabrication includes depositing a dielectric liner 235 of thickness t3 on the multi-gate device 200 by atomic layer deposition (ALD), and depositing a silicon liner 240 of thickness t4 on the dielectric liner 235 by ALD. In some embodiments, thicknesses t3 and t4 are substantially uniform across various surfaces of the multi-gate device 200. For example, thicknesses t3 and t4 along the sidewalls of trenches 230A-230C (i.e., on the sidewalls of fins 208A, 208B) are substantially the same as those along the bottom of trenches 230A-230C (i.e., on the top surface of substrate 206) and along the top surfaces of fins 208A, 208B. In some embodiments, thickness t3 is from about 0.5 nm to about 2.5 nm. In some embodiments, thickness t4 is from about 1 nm to about 4.5 nm. In some embodiments, the dielectric liner 235 and / or the silicon liner 240 are formed by: CVD, physical vapor deposition (PVD), high-density plasma CVD (HDPCVD), MOCVD, remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), sub-atmospheric vapor deposition (SAVCD), other suitable methods, or combinations thereof. In some embodiments, the dielectric liner 235 comprises an oxygen-containing dielectric material, such as a dielectric material comprising oxygen combined with silicon, carbon, and / or nitrogen, and thus may be referred to as an oxide liner. For example, the dielectric liner 235 comprises silicon oxide (e.g., SiO2), silicon oxynitride (SiON), and / or silicon carbonitride (SiOCN). In some embodiments, the dielectric liner 235 and / or the silicon liner 240 comprise n-type dopants and / or p-type dopants.

[0024] Go to Figure 4The remaining portions of trenches 230A-230C are filled with oxide layer 250. For example, deposition and planarization processes are performed to form oxide layer 250 over silicon liner 240 and fill the remaining portions of trenches 230A-230C. In some embodiments, forming oxide layer 250 includes depositing oxide material over multi-gate device 200, wherein the oxide material excessively fills trenches 230A-230C (e.g., the thickness of the oxide material is greater than the height of fins 208A, 208B), and performing a planarization process, such as chemical mechanical polishing (CMP), on the oxide material to reduce the thickness of the oxide material. In some embodiments, silicon liner 240 serves as a planarization (e.g., CMP) stop layer so that the planarization process is performed until the portion of silicon liner 240 disposed above the top surfaces of fins 208A, 208B is reached and exposed. Therefore, after the planarization process, the thickness of the oxide material is substantially equal to the sum of the heights of fins 208A and 208B, the thickness t3 of the dielectric liner 235 disposed above the top surfaces of fins 208A and 208B, and the thickness t4 of the silicon liner 240 disposed above the top surfaces of fins 208A and 208B. Thus, the planarization process removes any oxide material disposed above the top surfaces of fins 208A-208D. In some embodiments, the top surfaces of the oxide layer 250 and the silicon liner 240 are substantially planar after the planarization process. In some embodiments, the oxide material is deposited by flowable CVD (FCVD), which may include depositing a flowable oxide material (e.g., liquid) over the multi-gate device 200 and converting the flowable oxide material into a solid oxide material through an annealing process. The flowable oxide material can flow into trenches 230A-230C and conform to the exposed surfaces of the multi-gate device 200, thereby achieving void-free filling of trenches 230A-230C. In some embodiments, the flowable oxide material is a material comprising flowable silicon and oxygen, and the annealing process transforms the flowable silicon and oxygen material into a silicon and oxygen-containing layer, such as a silicon oxide layer. Therefore, the oxide layer 250 may be referred to as a silicon oxide layer. In some embodiments, the annealing process is thermal annealing, which heats the multi-gate device 200 to a temperature conducive to transforming the flowable oxide material into a solid oxide material. In some embodiments, the annealing process exposes the flowable oxide material to UV radiation. In some embodiments, the oxide material is deposited using a high aspect ratio deposition (HARP) process. In some embodiments, the oxide material is deposited using HDPCVD. In some embodiments, the annealing process is performed after a planarization process to further solidify and / or densify the oxide layer 250.

[0025] Go to Figure 5The oxide layer 250 is recessed (e.g., by an etching process) to form isolation features 255, such that fins 208A, 208B extend (protrude) from the oxide layer 250. In the depicted embodiment, the oxide layer 250 surrounds the bottom of the fins 208A, 208B, thereby providing an upper fin active region 258U (e.g., the portion of fins 208A, 208B extending from the top surface of the oxide layer 250) and a lower fin active region 258L (e.g., the portion of fins 208A, 208B surrounded by the oxide layer 250) for the fins 208A, 208B. In some embodiments, the etching process selectively removes the oxide layer 250 relative to the silicon liner 240. In other words, the etching process substantially removes the oxide layer 250 but does not remove or substantially does not remove the silicon liner 240. For example, an etchant is selected for an etching process that etches silicon oxide (i.e., oxide layer 250) at a higher rate than etching silicon (i.e., silicon liner 240) (i.e., the etchant has high etch selectivity relative to silicon oxide). The etching process is dry etching, wet etching, other suitable etching processes, or a combination thereof. In some embodiments, the etching process uses a patterned mask layer as an etching mask, wherein the patterned mask layer covers the silicon liner 240 but exposes the oxide layer 250.

[0026] After the oxide layer 250 is recessed, the lower portion of trenches 230A-230C is filled with the oxide layer 250, silicon liner 240, and dielectric liner 235, while the upper portion of trenches 230A-230C is filled with the silicon liner 240 and dielectric liner 235. The isolation feature 255 is formed by the oxide layer 250, silicon liner 240, and dielectric liner 235, wherein the oxide layer 250 is disposed on the silicon liner 240, the silicon liner 240 is disposed on the dielectric liner 235, and the dielectric liner 235 is disposed on the sidewall of the lower fin active region 258L. The oxide layer 250 may be referred to as the oxide layer, bulk dielectric, and / or bulk dielectric layer of the isolation feature 255. Isolation feature 255 electrically isolates the active device regions and / or passive device regions of the multi-gate device 200 from each other, for example, electrically isolating the first transistor region 202A and the second transistor region 202B, electrically isolating the first transistor region 202A from other active device regions and / or passive device regions, and electrically isolating the second transistor region 202B from other active device regions and / or passive device regions. Various dimensions and / or characteristics of isolation feature 255 can be used in conjunction with… Figures 2-5The associated processing is configured to implement a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a silicon local oxidation (LOCOS) structure, other suitable isolation structures, or combinations thereof. In the depicted embodiment, isolation feature 255 is an STI. In some embodiments, an etching process recesses the oxide layer 250 until a target height of the upper fin active region 258U is reached. For example, the etching process proceeds until the fin portions 206' of fins 208A, 208B are reached, such that the semiconductor layer stack 210 forms the upper fin active region 258U. In some embodiments, as shown, after the etching process, the top surface of the fin portion 206' is substantially flush with the top surface of the oxide layer 250. In some embodiments, the fin portion 206' is partially exposed by the etching process such that after the etching process, the top surface of the fin portion 206' is higher than the top surface of the oxide layer 250 relative to the top surface of the substrate 206. In some embodiments, the semiconductor layer stack 210 is partially, rather than fully, exposed by an etching process such that, after the etching process, the top surface of the fin portion 206' is lower than the top surface of the oxide layer 250 relative to the top surface of the substrate 206.

[0027] Go to Figure 6A silicon-germanium sacrificial layer 258 is formed on fins 208A and 208B. In the depicted embodiment, the silicon-germanium sacrificial layer 258 is formed on the top surface and sidewalls of the upper fin active region 258U of fins 208A and 208B, such that the silicon-germanium sacrificial layer 258 surrounds the upper fin active region 258U. In a further description of the embodiment, the upper portions of trenches 230A-230C are filled with a silicon-germanium sacrificial layer 258 of thickness t5. In some embodiments, the thickness t5 is from about 3.5 nm to about 12 nm. The thickness t5 can be selected according to the desired internal spacer thickness of the multi-gate device 200. In some embodiments, the exposed portion of the silicon liner 240 is converted into the silicon-germanium sacrificial layer 258. For example, a deposition process is performed to selectively grow a silicon-germanium layer on the exposed portion (i.e., the semiconductor surface) of the silicon liner 240, but not on the exposed portion (i.e., the dielectric surface) of the oxide layer 250, and an annealing process is performed to drive (diffuse) germanium from the silicon-germanium layer into the exposed portion of the silicon liner 240, thereby making the exposed portion of the silicon liner 240 part of the silicon-germanium layer. In some embodiments, the deposition process is an epitaxial process using CVD deposition techniques (e.g., LPCVD, VPE, and / or UHV-CVD), MBE, other suitable epitaxial growth processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors (e.g., silane precursors and germanium precursors) that interact with the composition of the silicon liner 240. In some embodiments, the silicon-germanium layer may be exposed to an oxidizing environment (e.g., oxygen), wherein silicon from the silicon-germanium layer reacts with oxygen to form a thin outer silicon oxide layer, and germanium from the silicon-germanium layer diffuses into the exposed portion of the silicon liner 240 and reacts with the silicon therein, thereby making the exposed portion of the silicon liner 240 part of the silicon-germanium layer. Such a process may be referred to as a silicon-germanium condensation process. Suitable cleaning and / or etching processes may be implemented to remove the thin silicon oxide layer. The silicon-germanium sacrificial layer 258 may also be referred to as a silicon-germanium cladding layer, a silicon-germanium cap, and / or a silicon-germanium protective layer.

[0028] Go to Figure 7The remaining portion of the upper part of trenches 230A-230C is filled with dielectric features 260, each dielectric feature 260 including a dielectric liner 262 and an oxide layer 264 disposed on the dielectric liner 262. In the depicted embodiments, the dielectric liner 262 includes a dielectric material with a dielectric constant less than about 7.0 (k ≤ 7.0). For the purposes of this disclosure, such a dielectric material is referred to as a low-k dielectric material, and the dielectric liner 262 may be referred to as a low-k dielectric liner. In some embodiments, the dielectric liner 262 includes a dielectric material with a dielectric constant of about 3.0 to 7.0. In some embodiments, the dielectric liner 262 includes a silicon-containing dielectric material, such as a dielectric material comprising silicon combined with oxygen, carbon, and / or nitrogen. For example, the dielectric liner 262 includes silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbonoxynitride, silicon carbonitride, or combinations thereof. In some embodiments, the dielectric liner 262 comprises an n-type dopant and / or a p-type dopant. For example, the dielectric liner 262 may be a boron-doped nitride liner. In some embodiments, the dielectric liner 262 comprises a dielectric material with a dielectric constant less than that of silicon dioxide (SiO2) (k ≈ 3.9), such as fluorine-doped silicon dioxide (commonly referred to as fluorosilicate glass (FSG)), carbon-doped silicon dioxide (commonly referred to as carbon-doped FSG), Black Diamond® (Applied Materials, Santa Clara, CA), degel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene-based dielectric materials (BCB), SiLK (Dow Chemical Company, Midland, Michigan), polyimide, other low-k dielectric materials, or combinations thereof. In some embodiments, the dielectric liner 262 comprises borosilicate glass (BSG), phosphosilicate glass (PSG), and / or boron-doped phosphosilicate glass (BPSG). In some embodiments, oxide layer 264 is similar to oxide layer 250. For example, oxide layer 264 includes silicon and oxygen, such as a silicon oxide layer.

[0029] In some embodiments, a dielectric feature 260 is formed on an isolation feature 255 by depositing a dielectric layer on a multi-gate device 200, wherein the dielectric layer partially fills the upper portion of trenches 230A-230C; an oxide material is deposited on the dielectric layer, wherein the oxide material fills the remaining portion of the upper portion of trenches 230A-230C; and a planarization process, such as CMP, is performed to remove the oxide material and / or dielectric layer disposed on the top surface of the silicon-germanium sacrificial layer 258. In such embodiments, the silicon-germanium sacrificial layer 258 serves as a planarization (e.g., CMP) stop layer, such that the planarization process is performed until the silicon-germanium sacrificial layer 258 is reached and exposed. The remaining portion of the oxide material and dielectric layer forms a dielectric liner 262 and an oxide layer 264, which form the dielectric feature 260, such as... Figure 7 As shown. Therefore, dielectric feature 260, silicon-germanium sacrificial layer 258, and dielectric liner 235 are combined to fill the upper portion of trenches 230A-230C, and isolation feature 255 fills the lower portion of trenches 230A-230C. In the depicted embodiment, dielectric liner 262 has a U-shaped cross-sectional profile such that dielectric liner 262 surrounds oxide layer 264. For example, dielectric liner 262 is disposed along the sidewalls and bottom of oxide layer 264 and separates oxide layer 264 from silicon-germanium sacrificial layer 258 and isolation feature 255. Dielectric liner 262 has a thickness t6. In some embodiments, thickness t6 is from about 2.5 nm to about 7 nm. In some embodiments, thickness t6 is substantially uniform on various surfaces of multi-gate device 200. For example, the thickness t6 along the upper sidewalls of trenches 230A-230C (i.e., above the sidewalls of the silicon-germanium sacrificial layer 258) is substantially the same as the thickness t6 along the bottom of the upper portion of trenches 230A-230C (i.e., above the top surface of the isolation feature 255). In some embodiments, a dielectric layer is deposited by ALD. In some embodiments, a dielectric layer is deposited by LPCVD. In some embodiments, the dielectric layer is formed by CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, APCVD, SAVCD, other suitable deposition processes, or combinations thereof. In some embodiments, oxide material is deposited by FCVD, HPCVD, HARP, CVD, other suitable deposition processes, or combinations thereof. In the depicted embodiments, oxide material is deposited by FCVD to minimize void formation within the oxide layer 264.

[0030] Go to Figure 8The dielectric feature 260 is partially removed from trenches 230A-230C. For example, the dielectric feature 260 is recessed to expose a portion of the patterned layer 225 (e.g., the top surface and sidewalls of the patterned layer 225) overlying the silicon-germanium sacrificial layer 258. After recessing, the dielectric feature 260 partially fills the upper portion of trenches 230A-230C (i.e., fills the lower portion of the upper portion of trenches 230A-230C). In some embodiments, the etching process recesses the dielectric feature 260 until the semiconductor layer stack 210 of fins 208A, 208B is reached. For example, the top surface of the semiconductor layer stack 210 (i.e., the top surface of the topmost semiconductor layer 220) is substantially planar with the top surface of the dielectric feature 260 after the etching process. In some embodiments, the etching process recesses the dielectric feature 260 below the semiconductor layer stack 210, such that the top surface of the dielectric feature 260 is lower than the top surface of the substrate 206 than the top surface of the semiconductor layer stack 210. The etching process selectively removes the dielectric liner 262 and the oxide layer 264 relative to the silicon-germanium sacrificial layer 258. In other words, the etching process substantially removes the dielectric liner 262 and the oxide layer 264, but does not remove or substantially does not remove the silicon-germanium sacrificial layer 258. For example, an etchant is selected for the etching process that etches the silicon-containing dielectric material (i.e., the dielectric liner 262 and the oxide layer 264) at a higher rate than etching silicon-germanium (i.e., the silicon-germanium sacrificial layer 258) (i.e., the etchant has high etch selectivity relative to the silicon-containing dielectric material). The etching process is dry etching, wet etching, other suitable etching processes, or a combination thereof. In some embodiments, dry etching uses an etching gas comprising CF4 and H2 to selectively etch the silicon-containing dielectric material (i.e., dielectric liner 262 and oxide layer 264) relative to silicon-germanium (i.e., silicon-germanium sacrificial layer 258). In some embodiments, dry etching uses a carrier gas to deliver the etching gas. The carrier gas includes nitrogen, argon, helium, xenon, other suitable carrier gas components, or combinations thereof. In some embodiments, the etching process includes multiple steps, such as a first etching step that recesses the oxide layer 264 using a first etchant and a second etching step that recesses the dielectric liner 262 using a second etchant. In some embodiments, the etching process uses a patterned mask layer as an etching mask, wherein the patterned mask layer covers the silicon-germanium sacrificial layer 258 but has openings therein that expose the dielectric liner 262 and oxide layer 264.

[0031] Go to Figure 9Dielectric features 270 are formed on top of dielectric features 260 to fill the remaining upper portion of trenches 230A-230C. Each dielectric feature 270 includes a dielectric liner 272 and a dielectric layer 274. The dielectric liner 272 has a U-shaped cross-sectional profile such that the dielectric liner 272 surrounds the dielectric layer 274. For example, the dielectric liner 272 is disposed along the sidewalls and bottom of the dielectric layer 274 and separates the dielectric layer 274 from the silicon-germanium sacrificial layer 258 and the dielectric feature 260. The dielectric liner 272 has a thickness t7. In some embodiments, the thickness t7 is from about 1 nm to about 6 nm. In some embodiments, the thickness t7 is substantially uniform. For example, the thickness t7 along the sidewalls of the dielectric layer 264 is substantially the same as the thickness t7 along the bottom of the dielectric layer 264. In some embodiments, the thickness t7 along the sidewalls of the dielectric layer 264 may be different from the thickness t7 along the bottom of the dielectric layer 264. In some embodiments, the thickness t7 is substantially the same as the thickness t6 of the dielectric liner 262. In some embodiments, the thickness t7 is greater than the thickness t6. In some embodiments, the thickness t7 is less than the thickness t6. In some embodiments, a dielectric feature 270 is formed on the dielectric feature 260 by depositing a first dielectric layer having a first dielectric constant over the multi-gate device 200, wherein the first dielectric layer partially fills the remaining portion above the trenches 230A-230C; a second dielectric layer having a second dielectric constant is deposited over the first dielectric layer, wherein the second dielectric layer fills the remaining portion above the trenches 230A-230C, and the second dielectric constant is less than the first dielectric constant; and a planarization process, such as CMP, is performed to remove portions of the second dielectric layer, the first dielectric layer, and / or the silicon-germanium sacrificial layer 258 disposed above the top surfaces of the fins 208A, 208B. For example, the patterning layer 225 can be used as a planarization stop layer, such that the planarization process is performed until the patterning layer 225 of the fins 208A, 208B is reached and exposed. In such embodiments, the top surfaces of dielectric feature 270 (e.g., the top surfaces of dielectric liner 272 and dielectric layer 274), the top surface of patterned layer 225, and the top surface of silicon-germanium sacrificial layer 258 can be substantially coplanar. Figure 9As shown, the remaining portions of the second dielectric layer and the first dielectric layer form the dielectric liner 272 and dielectric layer 274, respectively. In some embodiments, the first dielectric layer and / or the second dielectric layer are formed by ALD, CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, APCVD, SAVCD, other suitable deposition processes, or combinations thereof. In some embodiments, the second dielectric layer (i.e., dielectric layer 274) is formed by FCVD, wherein a flowable low-k dielectric material (e.g., liquid) is formed on the multi-gate device 200, and the flowable low-k dielectric material is converted into a solid flowable low-k dielectric material by an annealing process. The flowable low-k dielectric material can flow into the remaining upper portions of trenches 230A-230C, achieving void-free filling of the remaining upper portions of trenches 230A-230C. Reducing (and in some embodiments, preventing) voids in the dielectric feature 270 enhances the performance of the multi-gate device 200.

[0032] In the depicted embodiments, the dielectric liner 272 comprises a dielectric material with a dielectric constant greater than about 7.0 (k ≥ 7.0), and the dielectric layer 274 comprises a dielectric material having a dielectric constant less than that of the dielectric material of the dielectric liner 272, for example, less than about 7.0 (k ≤ 7.0). For the purposes of this disclosure, a dielectric material having a dielectric constant greater than about 7.0 (k ≥ 7.0) is referred to as a high-k dielectric material, such that the dielectric liner 272 may be referred to as a high-k dielectric layer, and the dielectric layer 274 may be referred to as a low-k dielectric layer. In some embodiments, the dielectric liner 272 comprises a dielectric material with a dielectric constant of about 7.0 to 30.0, and the dielectric layer 274 comprises a dielectric material with a dielectric constant of about 3.0 to 7.0. In some embodiments, the dielectric liner 272 comprises a dielectric material containing metal and oxygen (the dielectric material having a dielectric constant of, for example, from about 7.0 to about 30.0), such as a dielectric material comprising oxygen combined with hafnium, aluminum, and / or zirconium. In such embodiments, the dielectric liner 272 may also be referred to as a metal oxide layer. For example, the dielectric liner 272 comprises hafnium oxide (e.g., HfO). x ), aluminum oxide (AlO) x Zirconia (ZrO) x (or a combination thereof), where x is the number of oxygen atoms in the dielectric material of the dielectric liner 272. In some embodiments, the dielectric liner 272 comprises an n-type dopant and / or a p-type dopant. In some embodiments, the dielectric liner 272 comprises HfO2, HfSiO2, etc. x (e.g., HfSiO or HfSiO4), HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx The dielectric layer 274 comprises silicon-containing dielectric materials, such as silicon-oxygen, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonoxylate, silicon carbonitride, or combinations thereof. In some embodiments, the dielectric layer 274 comprises an n-type dopant and / or a p-type dopant. For example, the dielectric layer 274 may be a boron-doped nitride layer. In some embodiments, dielectric layer 274 comprises a dielectric material with a dielectric constant less than that of silicon dioxide, such as FSG, carbon-doped FSG, BlackDiamond® (Applied Materials, Santa Clara, California), degel, aerogel, amorphous fluorinated carbon, parylene, BCB-based dielectric materials, SiLK (Dow Chemical Company, Midland, Michigan), polyimide, other low-k dielectric materials, or combinations thereof. In some embodiments, dielectric layer 274 comprises BSG, PSG, and / or BPSG.

[0033] Dielectric features 270 and 260 are combined to provide gate isolation fins 280A and 280B over isolation feature 255. Each of gate isolation fins 280A and 280B includes a corresponding dielectric feature 270 disposed over the corresponding dielectric feature 260. In some embodiments, dielectric feature 270 is referred to as a gate isolation cap. In the depicted embodiments, gate isolation fin 280A separates and / or isolates device features and / or transistor features within a transistor region from each other. For example, in the case where a first transistor region 202A includes a first CMOS transistor and a second transistor region 202B includes a second CMOS transistor, the leftmost gate isolation fin 280A in the first transistor region 202A can separate and / or isolate the gate of the p-type transistor of the first CMOS transistor from the gate of the n-type transistor of the first CMOS transistor, while the rightmost gate isolation fin 280A in the second transistor region 202B can separate and / or isolate the gate of the p-type transistor of the second CMOS transistor from the gate of the n-type transistor of the second CMOS transistor. Gate isolation fins 280B separate and isolate device features and / or transistor features in different transistor regions from each other. For example, in the case where a first transistor region 202A includes a first transistor and a second transistor region 202B includes a second transistor, gate isolation fins 280B can separate and / or isolate the gate of the first transistor in the first transistor region 202A from the gate of the second transistor in the second transistor region 202B. Gate isolation fins 280B span a transistor interface region including the interface between the first transistor region 202A and the second transistor region 202B, a portion of the first transistor region 202A adjacent to the interface, and a portion of the second transistor region 202B adjacent to the interface. In the depicted embodiment, a silicon-germanium sacrificial layer 258 and a dielectric liner 235 are disposed between gate isolation fins 280A, 280B and fins 208A, 208B such that the sidewalls of fins 208A, 208B do not physically contact the gate isolation fins 280A, 280B. Furthermore, because trenches 230A-230C are partially filled with a silicon-germanium sacrificial layer 258, the width w1 of the gate isolation fins 280A and 280B along the x-direction is smaller than the width w2 of the isolation feature 255 along the x-direction. In some embodiments, the width w1 is about 10 nm to about 25 nm. In some embodiments, the width w2 is about 25 nm to about 50 nm. In the depicted embodiments, dielectric features 260 and 270 both have a width w2, dielectric layer 274 has a width w3, and oxide layer 264 has a width w4. In some embodiments, the width w3 is about 8 nm to about 30 nm. In some embodiments, the width w4 is about 8 nm to about 30 nm. The width w3 is greater than, less than, or substantially equal to the width w4.

[0034] Go to Figure 10 and Figure 11 The process continues to form a dielectric cap layer 276 for dielectric feature 270. The dielectric cap layer 276 comprises a dielectric material with a dielectric constant greater than that of dielectric layer 274, such that dielectric layer 274 is surrounded by a dielectric material having a higher dielectric constant. Therefore, each dielectric feature 270 has a low-k dielectric core (the corresponding dielectric layer 274) surrounded or enclosed by a high-k dielectric shell 278 (collectively referred to as the corresponding dielectric liner 272 and the corresponding dielectric cap layer 276). As further described below, this configuration of the dielectric features 270 of the gate isolation fin 280B can, for example, improve the performance of the multi-gate device 200 by reducing (and in some embodiments eliminating) leakage paths between the subsequently formed metal gate and the source / drain contacts of the subsequently formed multi-gate device 200, which may be caused by voids formed in dielectric features having only high-k dielectric material. In the depicted embodiments, the dielectric cap 276 comprises a dielectric material with a dielectric constant greater than about 7.0 (k ≥ 7.0), and may therefore be referred to as a high-k dielectric layer. In some embodiments, the dielectric cap 276 comprises a dielectric material with a dielectric constant of about 7.0 to 30.0. In some embodiments, the dielectric cap 276 comprises a dielectric material containing metal and oxygen (the dielectric material having a dielectric constant of, for example, about 7.0 to about 30.0), such as a dielectric material comprising oxygen combined with hafnium, aluminum, and / or zirconium. In such embodiments, the dielectric cap 276 may also be referred to as a metal oxide layer. For example, the dielectric cap 276 comprises HfO. x AlO x ZrO x Or a combination thereof, where x is the number of oxygen atoms in the dielectric material of the dielectric cap 276. In some embodiments, the dielectric cap 276 comprises an n-type dopant and / or a p-type dopant. In some embodiments, the dielectric cap 276 comprises HfO2, HfSiO x (e.g., HfSiO or HfSiO4), HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO xZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3, (Ba,Sr)TiO3, HfO2-Al2O3, other suitable high-k dielectric materials or combinations thereof. In the depicted embodiments, the dielectric cap 276 and the dielectric liner 272 comprise the same dielectric material, such as a dielectric material containing metal and oxygen. In some embodiments, the dielectric cap 276 and the dielectric liner 272 comprise different dielectric materials, provided that the dielectric constant of the dielectric materials of the dielectric cap 276 and the dielectric liner 272 is greater than the dielectric constant of the dielectric layer 274.

[0035] exist Figure 10In this process, the dielectric layer 274 is recessed (e.g., etched back) to a depth d, thereby forming an opening 279 having sidewalls formed by the dielectric liner 272 and a bottom formed by the top surface of the dielectric layer 274. The depth d is greater than the thickness t7. In some embodiments, the depth d is from about 3 nm to about 15 nm. In some embodiments, the etching process causes the dielectric layer 274 to be recessed. The etching process selectively removes the dielectric layer 274 relative to the dielectric liner 272. In other words, the etching process substantially removes the dielectric layer 274 but does not remove or substantially does not remove the dielectric liner 272. In some embodiments, an etchant is selected for the etching process that etches the low-k dielectric material (i.e., the dielectric layer 274) at a higher rate than etching the high-k dielectric material (i.e., the dielectric liner 272) (i.e., the etchant has high etching selectivity relative to the low-k dielectric material). In some embodiments, an etchant is selected for an etching process that etches the silicon-containing dielectric material (i.e., dielectric layer 274) at a higher rate than etching the metal- and oxygen-containing dielectric material (i.e., dielectric liner 272) (i.e., the etchant has high etching selectivity relative to the silicon-containing dielectric material). In some embodiments, the etching process also selectively removes the dielectric layer 274 relative to the patterned layer 225 of the fins 208A, 208B, the silicon-germanium sacrificial layer 258, and / or the dielectric liner 235. The etching process is dry etching, wet etching, other suitable etching processes, or a combination thereof. In some embodiments, dry etching uses an etching gas comprising HF, NF (e.g., NH4F), NH (e.g., NH3), and / or BCl (e.g., BCl3) to achieve selective etching of the silicon-containing dielectric material (i.e., dielectric layer 274) relative to the metal- and oxygen-containing dielectric material (i.e., dielectric liner 272). In some embodiments, dry etching may use a carrier gas to deliver the etching gas. The carrier gas includes nitrogen, argon, helium, xenon, other suitable carrier gas components, or combinations thereof. In some embodiments, the etching process uses a patterned mask layer as an etching mask, wherein the patterned mask layer covers fins 208A, 208B and the silicon-germanium sacrificial layer 258, but has openings therein that expose the dielectric feature 270. In some embodiments, the patterned mask layer also covers the dielectric liner 272, such that the openings in the patterned mask layer expose the dielectric layer 274 of the dielectric feature 270, but do not expose the dielectric liner 272 of the dielectric feature 270.

[0036] exist Figure 11In this embodiment, a dielectric cap layer 276 is formed over the dielectric layer 274 in the opening 279. The dielectric cap layer 276 is disposed between the sidewall portions of the dielectric liner 272. The dielectric cap layer 276 has a thickness t8 greater than the thickness t7. In some embodiments, the thickness t8 is substantially the same as the depth d. In some embodiments, the thickness t8 is from about 5 nm to about 15 nm. In some embodiments, the dielectric cap layer 276 is formed by depositing a dielectric layer having a third dielectric constant over the multi-gate device 200, wherein the dielectric layer fills the opening 279 and the third dielectric constant is greater than the second dielectric constant of the dielectric layer 274; and performing a planarization process, such as CMP, to remove the portion of the dielectric layer disposed above the top surfaces of the fins 208A, 208B. For example, a patterning layer 225 can be used as a planarization stop layer, such that a planarization process is performed until the patterning layer 225 of the fins 208A, 208B is reached and exposed. In such embodiments, the top surfaces of the dielectric feature 270 (e.g., the top surfaces of the dielectric liner 272 and the dielectric cap 276), the top surfaces of the patterned layer 225, and the top surfaces of the silicon-germanium sacrificial layer 258 can be substantially planar. In some embodiments, the dielectric layer is formed by CVD, PVD, ALD, RPCVD, PECVD, HDPCVD, FCVD, HARP, LPCVD, ALCVD, APCVD, SACVD, MOCVD, other suitable deposition processes, or combinations thereof.

[0037] Go to Figure 12An etching process is performed to remove the patterned layer 225 from the fins 208A and 208B, and to remove portions of the silicon-germanium sacrificial layer 258 disposed along the sidewalls of the patterned layer 225, thereby forming an opening 285 (formed between the dielectric features 270) that exposes the semiconductor layer stack 210 of the fins 208A and 208B. The etching process selectively removes the patterned layer 225 and the silicon-germanium sacrificial layer 258 relative to the dielectric housing 278 and the semiconductor layer 220 of the semiconductor layer stack 210. In other words, the etching process substantially removes the patterned layer 225 and the silicon-germanium sacrificial layer 258 (specifically, portions of the silicon-germanium sacrificial layer 258 disposed along the sidewalls of the patterned layer 225), but does not remove or substantially does not remove the dielectric housing 278 and the semiconductor layer 220. For example, an etchant is selected for an etching process that etches silicon nitride (i.e., patterned layer 225) and silicon germanium (i.e., silicon germanium sacrificial layer 258) at a higher rate than the metal- and oxygen-containing material (i.e., dielectric housing 278) and silicon (i.e., semiconductor layer 220) (i.e., the etchant has high etch selectivity relative to silicon nitride and silicon germanium). The etching process is dry etching, wet etching, other suitable etching processes, or a combination thereof. In some embodiments, dry etching uses a fluorine-containing etching gas to selectively etch silicon nitride (i.e., patterned layer 225) and silicon germanium (i.e., silicon germanium sacrificial layer 258) relative to the metal- and oxygen-containing dielectric material (i.e., dielectric housing 278) and silicon (i.e., semiconductor layer 220). In some embodiments, the etching process includes multiple steps, such as a first etching step selectively etching the patterned layer 225 and a second etching step selectively etching the silicon germanium sacrificial layer 258 (e.g., the first and second etching steps use different etchants). In some embodiments, the etching process uses a patterned mask layer as an etching mask, wherein the patterned mask layer covers the dielectric feature 270 but has an opening that exposes the patterned layer 225, and in some embodiments, exposes a portion of the silicon-germanium sacrificial layer 258 disposed along the sidewall of the patterned layer 225.

[0038] Go to Figure 13A dummy gate stack 290 is formed over portions of fins 208A, 208B and gate isolation fins 280A, 280B. The dummy gate stack 290 fills a portion of opening 285. The dummy gate stack 290 extends longitudinally in a direction different from (e.g., orthogonal to) the longitudinal direction of fins 208A, 208B. For example, the dummy gate stack 290 extends substantially parallel to each other along the x-direction, has a length in the x-direction, a width in the y-direction, and a height in the z-direction. The dummy gate stack 290 is disposed over the channel region (C) of the multi-gate device 200 and between the source / drain regions (S / D) of the multi-gate device 200. In the XZ plane, dummy gate stacks 290 are disposed on the top surfaces of fins 208A and 208B (specifically, the top surface of semiconductor layer stack 210), the top surfaces of dielectric features 270 of gate isolation fins 280A and 280B, and the sidewall surfaces of dielectric features 270 of gate isolation fins 280A and 280B, such that the dummy gate stacks 290 surround the dielectric features 270 of gate isolation fins 280A and 280B in the channel region of the multi-gate device 200. In the YZ plane, dummy gate stacks 290 are disposed on the top surfaces of the respective channel regions of fins 208A and 208B, such that the dummy gate stacks 290 are inserted into the respective source / drain regions of fins 208A and 208B. Each dummy gate stack 290 includes a dummy gate dielectric 292, a dummy gate electrode 294, and a hard mask 296 (including, for example, a first mask layer 297 and a second mask layer 298). The dummy gate dielectric 292 includes a dielectric material, such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or combinations thereof. In some embodiments, the dummy gate dielectric 292 includes an interface layer (e.g., including silicon oxide) and a high-k dielectric layer disposed above the interface layer. The dummy gate electrode 294 includes a suitable dummy gate material, such as polysilicon. In some embodiments, the dummy gate stack 290 includes many other layers, such as a capping layer, an interface layer, a diffusion layer, a barrier layer, or combinations thereof. The dummy gate stack 290 is formed by a deposition process, a photolithography process, an etching process, other suitable processes, or combinations thereof. For example, a first deposition process forms the dummy gate dielectric layer over the multi-gate device 200, a second deposition process forms the dummy gate electrode layer over the dummy gate dielectric layer, and a third deposition process forms a hard mask layer over the dummy gate electrode layer. Deposition processes include CVD, PVD, ALD, RPCVD, PECVD, HDPCVD, FCVD, HARP, LPCVD, ALCVD, APCVD, SACVD, MOCVD, electroplating, other suitable methods, or combinations thereof. Then, photolithographic patterning and etching processes, such as those described herein, are performed to pattern the hard mask layer, the dummy gate electrode layer, and the dummy gate dielectric layer to form a dummy gate stack 290, as... Figure 13 As shown.

[0039] Go to Figure 14 Gate spacers 299 are formed along the sidewalls of the dummy gate stack 290, thereby forming a gate structure 300 (collectively referred to as the dummy gate stack 290 and the gate spacers 299). Figure 14 In this process, portions of fins 208A and 208B in the source / drain regions of the multi-gate device 200 (i.e., the source / drain regions of fins 208A and 208B not covered by the gate structure 300) are also at least partially removed to form source / drain recesses (trenches) 305. The processing associated with forming the gate spacer 299 and / or the source / drain recesses 305 reduces the height of exposed portions of the dielectric features 270 of the gate isolation fins 280A and 280B (e.g., portions of dielectric features 270 in the source / drain regions of the multi-gate device 200) relative to unexposed portions of the dielectric features 270 of the gate isolation fins 280A and 280B (e.g., portions of dielectric features 270 in the channel regions of the multi-gate device 200). For example, dielectric feature 270 has a height h1, and the etching process used to form gate spacer 299 and / or source / drain recess 305 intentionally or unintentionally reduces the height of the exposed portion of dielectric feature 270 from height h1 to height h2. In some embodiments, height h1 is about 5 nm to about 30 nm, and height h2 is about 0 nm to about 15 nm (in other words, in some embodiments, dielectric feature 270 can be completely removed from the source / drain region of multi-gate device 200). Therefore, the portion of dielectric feature 270 disposed in the channel region of multi-gate device 200 and disposed under gate structure 300 has height h1, while the portion of dielectric feature 270 disposed in the source / drain region of multi-gate device 200 and not disposed under gate structure 300 has height h2. Furthermore, the dielectric cap layer 276 is removed from the source / drain region of the multi-gate device 200, such that the dielectric feature 270 disposed in the channel region of the multi-gate device 200 has a dielectric shell 278 surrounding the dielectric layer (core) 274, while the dielectric feature 270 disposed in the source / drain region of the multi-gate device 200 has a dielectric liner 272 surrounding the dielectric layer 274. In some embodiments, the height h1 is the distance between the topmost surface of the gate isolation fins 280A, 280B and the top surface of the topmost semiconductor layer 220 (which becomes the topmost channel layer). In such embodiments, the height h1 may be from about 6 nm to about 15 nm.

[0040] Gate spacer 299 is configured to be adjacent to dummy gate stack 290 (i.e., along its sidewalls). Gate spacer 299 is formed by any suitable process and includes a dielectric material, which may include silicon, oxygen, carbon, nitrogen, other suitable materials or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonoxynitride, and / or silicon carbonitride). For example, a dielectric layer comprising silicon and nitrogen (e.g., a silicon nitride layer) is deposited over multi-gate device 200 and etched to form gate spacer 299. In some embodiments, gate spacer 299 includes a multilayer structure, such as a first dielectric layer comprising silicon nitride and a second dielectric layer comprising silicon oxide. In some embodiments, more than one set of spacers (e.g., sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers) are formed adjacent to dummy gate stack 290. In such embodiments, the various sets of spacers may include different materials, for example, with different etch rates. For example, a silicon oxide layer can be deposited and etched to form a first set of spacer bars for gate spacers 299 adjacent to the sidewalls of the dummy gate stack 290, and a silicon nitride layer can be deposited and etched to form a second set of spacers for gate spacers 299 adjacent to the first set of spacers.

[0041] In the depicted embodiment, the etching process completely removes the semiconductor layer stack 210 in the source / drain region of the multi-gate device 200, thereby exposing the fin portion 206' in the source / drain region of the multi-gate device 200. The etching process also completely removes portions of the silicon-germanium sacrificial layer 258 and the dielectric liner 235 disposed along the sidewalls of the semiconductor layer stack 210 in the source / drain region of the multi-gate device 200. Therefore, each source / drain recess 305 has a sidewall formed by a corresponding first one of the gate isolation fins 280A, a sidewall formed by the gate isolation fin 280B, and a sidewall (or multiple sidewalls) formed by the remaining portion of the semiconductor layer stack 210, the remaining portion of the silicon-germanium sacrificial layer 258, and the remaining portion of the dielectric liner 235 disposed in the channel region of the multi-gate device 200 (specifically, disposed below the gate structure 300). Each source / drain recess 305 also has a bottom formed by the corresponding fin portion 206' and the corresponding isolation feature 255. In some embodiments, the etching process removes a portion (but not all) of the semiconductor layer stack 210, such that the source / drain recess 305 has a bottom formed by the respective semiconductor layer 215 or semiconductor layer 220. In some embodiments, the etching process further removes a portion, but not all, of the fin portion 206', such that the source / drain recess 305 extends below the top surface of the isolation feature 255. The etching process may include dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, the etching process is a multi-step etching process. For example, the etching process may replace the etchant to remove the semiconductor layer 215, semiconductor layer 220, silicon-germanium sacrificial layer 258, and / or dielectric liner 235 individually and alternately. In some embodiments, the parameters of the etching process are configured to selectively etch the semiconductor layer stack 210, wherein the gate structure 300 (i.e., the dummy gate stack 290 and gate spacer 299), gate isolation fins 280A, 280B, and / or isolation feature 255 are minimally etched (to no etching). In some embodiments, a photolithography process, such as that described herein, is performed to form a patterned mask layer covering the gate structure 300 and / or gate isolation fins 280A, 280B, and an etching process uses the patterned mask layer as an etching mask. In such embodiments, the thickness of the dielectric feature 270 is not reduced in the source / drain regions of the multi-gate device 200, such that the dielectric feature 270 has a height h1 in both the channel region and the source / drain region of the multi-gate device 200.

[0042] Go to Figure 15 and Figure 16Internal spacers 310A and 310B are formed below the gate structure 300 (specifically below the gate spacer 299) along the sidewalls of the semiconductor layers 220 and 215 below the dummy gate stack 290. Internal spacer 310A separates the semiconductor layers 220 from each other and separates the bottom semiconductor layer 220 from the fin portion 206', while internal spacer 310B separates the dielectric liner 235, the sidewalls of the semiconductor layers 220 and 215 from the gate isolation fins 280A and 280B. In the XZ plane, below the gate spacer 299, a dielectric liner 235 extends along and physically contacts the first and second sidewalls of the semiconductor layer 220 and the internal spacer 310A (where the top and bottom surfaces of the semiconductor layer 220 and the internal spacer 310A extend between the first and second sidewalls), such that the dielectric liner 235 separates the first and second sidewalls of the semiconductor layer 220 and the internal spacer 310A from the internal spacer 310B. Figure 15 In the first etching process, a first etching process is performed that selectively etches the semiconductor layer 215 exposed by the source / drain recess 305, wherein the semiconductor layer 220, fin portion 206', dielectric liner 235, isolation feature 255, gate isolation fins 280A, 280B, and gate structure 300 are minimally etched (to the point of no etching), such that gap 310A' is formed between the semiconductor layer 220 and between the fin portion 206' and the semiconductor layer 220. The first etching process further selectively etches the silicon-germanium sacrificial layer 258 exposed by the source / drain recess 305, such that gap 310B' is formed between the dielectric liner 235 and the gate isolation fins 280A, 280B. Gap 310A' and gap 310B' are located below the gate spacer 299. Therefore, semiconductor layer 220 is suspended below gate spacer 299, separated from each other by gap 310A', and separated from gate isolation fins 280A, 280B by dielectric liner 235 and gap 310B'. In some embodiments, gap 310A' and / or gap 310B' extend at least partially beneath dummy gate stack 290. A first etching process is configured to laterally etch (e.g., along the y-direction) semiconductor layer 215 and silicon-germanium sacrificial layer 258, thereby reducing the length of semiconductor layer 215 along the y-direction. The first etching process is dry etching, wet etching, other suitable etching processes, or a combination thereof.

[0043] exist Figure 16In this process, a deposition process subsequently forms a spacer layer over the gate structure 300 and the features forming the source / drain recesses 305 (e.g., semiconductor layer 215, semiconductor layer 220, fin portion 206', gate isolation fins 280A, 280B, isolation feature 255, silicon-germanium sacrificial layer 258, and / or dielectric liner 235), using methods such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, electroplating, other suitable methods, or combinations thereof. The spacer layer partially (and in some embodiments completely) fills the source / drain recesses 305, and the deposition process is configured to ensure that the spacer layer fills gaps 310A' and 310B'. A second etching process is then performed, which selectively etches the spacer layer to form internal spacers 310A and 310B filling gaps 310A' and 310B', respectively, with minimal etching (to no etching) of the semiconductor layer 220, fin portions 206', dielectric liner 235, isolation features 255, gate isolation fins 280A, 280B, and gate structure 300. The spacer layer (and thus the internal spacers 310A and 310B) comprises a material different from that of the semiconductor layer 220, the fin portions 206', the isolation features 255, the gate isolation fins 280A, 280B, and / or the gate structure 300 to achieve the desired etch selectivity during the second etching process. In some embodiments, the spacer layer comprises a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and / or silicon carbonitride). In some embodiments, the spacer layer comprises a low-k dielectric material as described herein. In some embodiments, a dopant (e.g., a p-type dopant, an n-type dopant, or a combination thereof) is introduced into the dielectric material such that the spacer layer comprises a doped dielectric material.

[0044] Go to Figure 17Epitaxial source / drain features are formed in the source / drain recess 305. For example, semiconductor material is epitaxially grown from the semiconductor layer 220 exposed by the source / drain recess 305 and the fin portion 206' of the substrate 206, thereby forming an epitaxial source / drain feature 320A in the first transistor region 202A and an epitaxial source / drain feature 320B in the second transistor region 202B. In some embodiments, since the semiconductor material may not grow from the dielectric surface during the epitaxial growth process for forming the epitaxial source / drain features 320A, 320B, an air gap 322 can be formed between the epitaxial source / drain features 320A, 320B, the gate isolation fins 280A, 280B, and the isolation feature 255. In some embodiments, as shown, the epitaxial source / drain features 320A and 320B do not completely fill the source / drain recess 305, such that the top surfaces of the epitaxial source / drain features 320A and 320B are lower than the top surfaces of the dielectric features 270 of the gate isolation fins 280A and 280B. In some embodiments, the epitaxial source / drain features 320A and 320B completely fill the source / drain recess 305, such that the top surfaces of the epitaxial source / drain features 320A and 320B are substantially flush with or higher than the top surface of the dielectric feature 270. The epitaxial process may use CVD deposition techniques (e.g., LPCVD, VPE, and / or UHV-CVD), MBE, other suitable epitaxial growth processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that interact with the composition of the fin portion 206' and / or the semiconductor layer 220. Epitaxial source / drain features 320A and 320B are doped with n-type and / or p-type dopants. In some embodiments, for an n-type transistor, epitaxial source / drain features 320A and 320B comprise silicon, which may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., Si:C epitaxial source / drain features, Si:P epitaxial source / drain features, or Si:C:P epitaxial source / drain features). In some embodiments, for a p-type transistor, epitaxial source / drain features 320A and 320B comprise silicon germanium or germanium, which may be doped with boron, other p-type dopants, or combinations thereof (e.g., Si:Ge:B epitaxial source / drain features). In some embodiments, epitaxial source / drain features 320A and 320B comprise more than one epitaxial semiconductor layer, wherein the epitaxial semiconductor layers may comprise the same or different materials and / or the same or different dopant concentrations. In some embodiments, the epitaxial source / drain features 320A, 320B include materials and / or dopants that achieve the desired tensile and / or compressive stresses in the respective channel regions of the n-type and / or p-type transistors. In some embodiments, the epitaxial source / drain features 320A, 320B are doped during deposition by adding impurities to the source material of the epitaxial process (i.e., in situ).In some embodiments, the epitaxial source / drain features 320A, 320B are doped by ion implantation following a deposition process. In some embodiments, an annealing process (e.g., rapid thermal annealing and / or laser annealing) is performed to activate the dopants in the epitaxial source / drain features 320A, 320B and / or other source / drain regions (e.g., heavily doped source / drain (HDD) regions and / or lightly doped source / drain (LDD) regions). In some embodiments, the epitaxial source / drain features 320A, 320B are formed in a separate processing sequence, for example, by masking the second transistor region 202B when forming the epitaxial source / drain feature 320A in the first transistor region 202A and by masking the first transistor region 202A when forming the epitaxial source / drain feature 320B in the second transistor region 202B.

[0045] In some embodiments, after forming epitaxial source / drain features 320A, 320B, a contact etch stop layer (CESL) 330 is formed over the multi-gate device 200, an interlayer dielectric (ILD) layer 332 is formed over the CESL 330, an ILD guard layer 334 is formed over the ILD layer 332, and CMP and / or other planarization processes are performed until the top (or top surface) of the dummy gate stack 290 is reached (exposed). The CESL 330 and ILD layer 332 are disposed over the epitaxial source / drain features 320A, 320B and gate isolation fins 280A, 280B in the source / drain regions of the multi-gate device 200, and in the depicted embodiment, the CESL 330 and ILD layer 332 fill the remaining portion of the source / drain recess 305. The CESL 330, ILD layer 332 and ILD guard layer 334 are disposed between adjacent gate structures 300. In some embodiments, CESL 330 and / or ILD layer 332 are disposed on and in solid contact with the planar surfaces of the epitaxial source / drain features 320A and 320B extending from the gate isolation fins 280A and 280B to the top surfaces (planar surfaces) of the epitaxial source / drain features 320A and 320B, while the planar surfaces of the epitaxial source / drain features 320A and 320B extending from the gate isolation fins 280A and 280B to the bottom surfaces (planar surfaces) of the epitaxial source / drain features 320A and 320B (i.e., the surfaces disposed on the fin portion 206') do not make solid contact with any dielectric material due to the air gap 322. CESL 330, ILD layer 332, and ILD protective layer 334 are formed by CVD, PVD, ALD, HDPCVD, HARP, FCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. In some embodiments, the ILD layer 332 is formed of FCVD, HARP, HDPCVD, or a combination thereof. In some embodiments, a planarization process removes the hard mask 296 of the dummy gate stack 290 to expose the underlying dummy gate electrode 294, such as a polysilicon gate electrode. The ILD layer 332 includes a dielectric material, including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, oxides formed from TEOS, PSG, BSG, BPSG, FSG, Black Diamond® (Applied Materials, Santa Clara, CA), degel, aerogel, amorphous fluorinated carbon, parylene, BCB-based dielectric materials, SiLK (Dow Chemical Company, Midland, Michigan), polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the dielectric material included in the ILD layer 332 has a dielectric constant less than that of silicon dioxide.In some embodiments, the ILD layer 332 comprises a dielectric material with a dielectric constant less than about 2.5 (i.e., an extremely low-k (ELK) dielectric material), such as SiO2 (e.g., porous silicon oxide), silicon carbide, and / or carbon-doped oxides (e.g., SiCOH-based materials (e.g., having Si-CH3 bonds)). Each of these dielectric materials is tuned / configured to exhibit a dielectric constant less than about 2.5. The ILD layer 332 may comprise a multilayer structure having multiple dielectric materials. The CESL 330 comprises a dielectric material different from that of the ILD layer 332 and different from that of the gate spacer 299, for example, a dielectric material different from the dielectric material of the ILD layer 332 and different from the dielectric material of the gate spacer 299. For example, in the case where the ILD layer 332 comprises a low-k dielectric material (e.g., porous silicon oxide) and the gate spacer 299 comprises a dielectric material containing silicon and oxygen and / or carbon (e.g., silicon oxide, silicon carbide, and / or silicon carbide), the CESL 330 may include silicon and nitrogen (e.g., silicon nitride), silicon carbonitride, or silicon carbonitride. The ILD protective layer 334 includes a material different from that of ILD layer 332 and provides the etch selectivity and / or planarization selectivity required for fabricating the multi-gate device 200 as described herein. For example, ILD protective layer 334 includes silicon and nitrogen, such as silicon nitride, silicon carbonitride, or silicon carbonitride. In some embodiments, ILD protective layer 334 includes silicon, silicon carbide, silicon oxynitride, silicon carbonitride, other suitable materials, or combinations thereof. Depending on the etch selectivity required during subsequent processing, CESL 330 and ILD protective layer 334 may include the same or different materials.

[0046] ILD layer 332, CESL 330, and / or ILD guard layer 334 are part of multilayer interconnect (MLI) feature 340. In some embodiments, ILD layer 332 and CESL 330 form the bottom layer of MLI feature 340 (e.g., ILD0). MLI feature 340 electrically couples various devices (e.g., p-type and / or n-type transistors of multi-gate device 200, resistors, capacitors, and / or inductors) and / or components of p-type and / or n-type transistors of multi-gate device 200 (e.g., gate electrodes and / or epitaxial source / drain features) such that the various devices and / or components can operate according to the design requirements of multi-gate device 200. MLI feature 340 includes combinations of dielectric layers and conductive layers (e.g., metal layers) that are combined to form various interconnect structures. For example, conductive layers form vertical interconnect features, such as device-level contacts and / or vias, and / or horizontal interconnect features, such as conductive lines. Vertical interconnect features typically connect horizontal interconnect features at different levels (or different layers) of MLI feature 340. During operation, interconnect features route signals between devices and / or components of multi-gate device 200 and / or distribute signals (e.g., clock signals, voltage signals, and / or ground signals) to devices and / or components of multi-gate device 200.

[0047] Go to Figures 18-24 Perform a gate replacement process to replace the dummy gate stack 290 with a metal gate stack, and perform a channel release process (see [link]). Figure 23 A suspended channel layer is formed in the channel region of the multi-gate device 200, wherein a metal gate stack at least partially surrounds the suspended channel layer. For ease of description and understanding, Figures 18-24 It is along Figure 17 The GG line in the diagram passes through a cut (cut) section in the gate structure 300 (hence the term "metal gate cut perspective"). Go to... Figure 18 The gate opening 350 is formed by partially removing the dummy gate electrode 294 and gate spacer 299 of the gate structure 300. For example, an etching process recesses the dummy gate electrode 294 and gate spacer 299 such that the height h3 of the dummy gate electrode 294 and gate spacer 299 is less than the height h4 (i.e., the original height of the dummy gate electrode 294 and gate spacer 299, which is the height of CESL 330 and / or the height of ILD protective layer 334), but greater than the height h1. Therefore, after the etching process, the dummy gate electrode 294 and gate spacer 299 remain above the gate isolation fin 280B. In some embodiments, the height h3 is from about 25 nm to about 55 nm. In some embodiments, the height difference between the top surface of the dummy gate electrode 294 (and the top surface of the gate spacer 299) and the top surface of the gate isolation fin 280B is present in the channel region of the multi-gate device 200. h1 is at least approximately 5 nm to ensure that the gate isolation fin 280B is adequately protected during subsequent etching processes, as described below. The etching process selectively removes the dummy gate electrode 294 and the gate spacer 299 relative to CESL 330 and ILD protective layer 334. In other words, the etching process substantially removes the dummy gate electrode 294 and the gate spacer 299, but does not remove or substantially does not remove CESL 330 and ILD protective layer 334. For example, an etchant is selected for the etching process that etches a silicon- and nitrogen-containing dielectric material (i.e., CESL) at a ratio higher than that used for etching silicon- and nitrogen-containing dielectric materials (i.e., CESL). The etchant etches polysilicon (i.e., the dummy gate electrode 294) and silicon- and carbon-containing dielectric material (i.e., the gate spacer 299) at a higher rate than etching silicon- and nitrogen-containing dielectric material (i.e., CESL 330 and ILD protective layer 334, including, for example, SiN). In another example, an etchant is selected for an etching process that etches polysilicon (i.e., the dummy gate electrode 294) and silicon-, oxygen-, and nitrogen-containing dielectric material (i.e., CESL 330 and ILD protective layer 334, including, for example, SiN) at a higher rate than etching silicon- and nitrogen-containing dielectric material (i.e., CESL 330 and ILD protective layer 334, including, for example, SiN). The dielectric material (i.e., gate spacer 299) (i.e., the etchant has high etch selectivity relative to polysilicon and silicon-, oxygen-, and nitrogen-containing dielectric materials (e.g., SiON)). The etching process is dry etching, wet etching, other suitable etching processes, or a combination thereof. In some embodiments, the etching process includes multiple steps, such as a first etching step selectively etching the dummy gate electrode 294 and a second etching step selectively etching the gate spacer 299 (e.g., the first and second etching steps use different etchants). In some embodiments, the etching process uses a patterned mask layer as an etching mask, wherein the patterned mask layer covers CESL 330 and / or ILD protective layer 334 but exposes the gate structure 300.

[0048] Go to Figures 19-21 The dielectric feature 270 is removed from the gate isolation fin 280A in the channel region of the multi-gate device 200. Figure 19In this process, a photolithography process, such as that described herein, is performed to form a patterned mask layer 360, wherein openings 362A and 362B are formed. In some embodiments, the patterned mask layer 360 is a patterned resist layer. In some embodiments, the patterned mask layer 360 is a patterned hard mask layer. In some embodiments, the patterned mask layer 360 includes multiple layers, such as a patterned resist layer disposed over the patterned hard mask layer. The patterned mask layer 360 covers a dielectric fin, such as a gate isolation fin 280B, spanning a transistor interface region. For example, the patterned mask layer 360 covers a transistor interface region between a first transistor region 202A and a second transistor region 202B, the transistor interface region including: the interface between the first transistor region 202A and the second transistor region 202B, a portion of the first transistor region 202A adjacent to the interface, and a portion of the second transistor region 202B adjacent to the interface. In the depicted embodiment, gate isolation fin 280B spans the transistor interface region and is therefore covered by a patterned mask layer 360. In a further description of the embodiment, the patterned mask layer 360 covers the top and sidewalls of the gate isolation fin 280B in the channel region of the multi-gate device 200, including portions of the dummy gate dielectric 292 and dummy gate electrode 294 disposed thereon. In some embodiments, the patterned mask layer 360 covers only the top of the gate isolation fin 280B, including portions of the dummy gate dielectric 292 and dummy gate electrode 294 disposed thereon. Openings 362A, 362B expose dielectric fins, such as gate isolation fin 280A, spanning the interface region between different device features and / or different transistor features within the transistor region. For example, opening 362A exposes the leftmost gate isolation fin 280A in the first transistor region 202A and a portion of the gate structure 300 therein, and opening 362B exposes the rightmost gate isolation fin 280A in the second transistor region 202B and a portion of the gate structure 300 therein.

[0049] exist Figure 20In this process, the dummy gate electrode 294 (but not the gate spacer 299) is further recessed (e.g., etched back) to extend the gate opening 350. For example, the etching process further recesses the dummy gate electrode 294 but not the gate spacer 299, thereby removing the dummy gate electrode 294 from the top surface of the gate isolation fin 280A in the channel region of the multi-gate device 200. A patterned mask layer 360 protects the gate isolation fin 280B (and portions of the dummy gate electrode 294 thereon) from the etching process. After the etching process, the dummy gate electrode 294 has a height h5, and the gate spacer 299 has a height h3. The height h5 is less than the height h3 and less than the height h1, such that the top surface of the portion of the dummy gate electrode 294 disposed above the semiconductor layer 220 is lower than the top surface of the gate isolation fins 280A, 280B. In some embodiments, the height h5 is about 5 nm to about 20 nm. In some embodiments, the height difference between the top surface of the gate isolation fin 280B in the channel region of the multi-gate device 200 and the top surface of the portion of the dummy gate electrode 294 disposed above the semiconductor layer 220 h2 is at least approximately 4 nm to ensure that the gate isolation fin 280B is adequately protected during subsequent etching processes, as described below. The etching process selectively removes the dummy gate electrode 294 relative to the gate spacer 299, CESL 330, ILD protective layer 334, and / or dummy gate dielectric 292. In other words, the etching process substantially removes the dummy gate electrode 294, but does not remove or substantially does not remove the gate spacer 299, CESL 330, ILD protective layer 334, and / or dummy gate dielectric 292. For example, an etchant is selected for the etching process that etches the polysilicon (i.e., the dummy gate electrode 294) at a higher rate than the etching dielectric material (i.e., the gate spacer 299, CESL 330, ILD protective layer 334, and / or dummy gate dielectric 292) (i.e., the etchant has high etch selectivity relative to the polysilicon). The etching process is dry etching, wet etching, other suitable etching processes, or a combination thereof. In some embodiments, dry etching uses an etching gas comprising HBr and / or Cl2 to selectively etch polysilicon (i.e., dummy gate electrode 294) relative to the dielectric material (i.e., gate spacer 299, CESL 330, ILD protective layer 334, and / or dummy gate dielectric 292). In some embodiments, wet etching uses a tetramethylammonium hydroxide (TMAH) etching solution to selectively etch polysilicon relative to the dielectric material. In some embodiments, the etching process uses a patterned mask layer as an etching mask, wherein the patterned mask layer covers the gate spacer 299, CESL 330, and / or ILD protective layer 334, but exposes the dummy gate electrode 294.

[0050] exist Figure 21In this process, an etching process is performed to remove dielectric features 270 from gate isolation fins 280A in the channel region of the multi-gate device 200, such that the gate isolation fins 280A have a first portion 280A-1 in the channel region of the multi-gate device 200 and a second portion 280A-2 in the source / drain region of the multi-gate device 200. The first portion 280A-1 includes dielectric features 260, while the second portion 280A-2 includes both dielectric features 270 (i.e., dielectric liner 272, dielectric layer 274, and dielectric cap layer 276) and dielectric features 260 (i.e., dielectric liner 262 and oxide layer 264). In the depicted embodiment, the etching process selectively etches dielectric features 270, wherein minimal etching (to no etching) is performed on the gate spacer 299, CESL 330, and / or ILD protection layer 334. In other words, the etching process essentially removes the dielectric feature 270, but does not remove or essentially does not remove the gate spacer 299, CESL 330, and / or ILD protective layer 334. For example, an etchant is selected for the etching process that etches high-k dielectric materials (i.e., dielectric liner 272 and dielectric cap 276, which may include metal- and oxygen-containing dielectric materials) and / or low-k dielectric materials (i.e., dielectric layer 274, which may include silicon- and oxygen-containing dielectric materials configured with a low dielectric constant) at a higher rate than etching other dielectric materials (i.e., gate spacer 299, CESL 330, and / or ILD protective layer 334, which may include silicon- and oxygen-containing dielectric materials) than etching other dielectric materials (i.e., the etchant has high etch selectivity relative to high-k dielectric materials and / or low-k dielectric materials). The etching process is dry etching, wet etching, other suitable etching processes, or a combination thereof. In some embodiments, the etching process includes multiple steps, such as a first etching step selectively etching a high-k dielectric material (e.g., dielectric cap 276 and dielectric liner 272), a second etching step selectively etching a low-k dielectric material (e.g., dielectric layer 274), and / or a third etching step selectively etching a high-k dielectric material (e.g., the remainder of dielectric liner 272). In some embodiments, the etchant has a first etching selectivity between the dielectric feature 270 and the gate spacer 299, CESL 330 and / or ILD protective layer 334 (e.g., a silicon and nitrogen and / or silicon and carbon dielectric material), and a second etching selectivity between the dielectric feature 270 and the dummy gate electrode 294 (e.g., polysilicon) and / or the dummy gate dielectric 292 (e.g., silicon oxide), wherein the first etching selectivity is greater than the second etching selectivity. Figure 21In the illustrated embodiment, the etching process does not remove (or at least removes) the gate spacer 299, CESL 330, and / or ILD protective layer 334, but instead removes the dummy gate electrode 294 and / or the dummy gate dielectric 292. For example, the etching process removes a portion of the dielectric feature 270 covering the gate isolation fin 280A of the dummy gate dielectric 292, and partially removes a portion of the dummy gate electrode 294 covering the gate isolation fin 280B, semiconductor layer 220, and / or silicon-germanium sacrificial layer 258. In some embodiments, the patterned mask layer 360 is removed before performing the etching process to remove the dielectric feature 270 from the gate isolation fin 280A, for example, by resist stripping, etching, other suitable processes, or combinations thereof. In some embodiments, the patterned mask layer 360 is partially or completely removed by the etching process. In such embodiments, after the etching process, the remaining portion of the patterned mask layer 360 can be removed from the multi-gate device 200 by any suitable process.

[0051] exist Figure 22 In this process, the remaining portions of the dummy gate electrode 294 and dummy gate dielectric 292 are removed to further extend the gate opening 350. For example, the etching process completely removes the dummy gate electrode 294 and dummy gate dielectric 292 to expose the semiconductor layer stack 210. The etching process is similar to that used for partial removal of the above reference. Figure 20 The etching process for the dummy gate electrode 294. For example, the etching process is configured to selectively etch the dummy gate electrode 294 and the dummy gate dielectric 292, wherein other features of the multi-gate device 200 (e.g., gate spacers 299, gate isolation fins 280A, 280B, CESL 330, ILD protective layer 334, and / or semiconductor layer 220) are minimally (to none) etched. The etching process is dry etching, wet etching, other suitable etching processes, or a combination thereof. In some embodiments, dry etching uses an etching gas comprising HBr and / or Cl2 to selectively etch polysilicon (i.e., the dummy gate electrode 294) relative to the dielectric material (i.e., gate spacers 299, CESL 330, ILD protective layer 334, and / or dummy gate dielectric 292). In some embodiments, wet etching uses TMAH to selectively etch polysilicon relative to the dielectric material. In some embodiments, the etching process includes multiple steps. For example, an etching process can replace an etchant to individually remove the individual layers of the dummy gate electrode 294. In some embodiments, a photolithography process, such as that described herein, is performed to form a patterned mask layer covering the ILD layer 332, CESL 330, gate isolation fin 280B, and / or gate spacer 299 during the etching process. In some embodiments, for removing Figure 22 The etching process for the remaining portion of the dummy gate electrode 294 differs from that used for partial removal of the reference above. Figure 20 The etching process for the dummy gate electrode 294 is described. For example, the etching process for removing the remaining portion of the dummy gate electrode 294 is wet polysilicon etching, while the process for partially removing the portion mentioned above is [missing information]. Figure 20 The etch process for the described dummy gate electrode 294 is dry polysilicon etching, and vice versa. In some embodiments, it is used to remove... Figure 22 The etching process for the remaining portion of the dummy gate electrode 294 is described in the reference above. Figure 20 The etching process for the dummy gate electrode 294 is the same. For example, both etching processes are dry (or wet) polysilicon etching.

[0052] exist Figure 23In this process, a channel release process is performed to form channels for transistors within the first transistor region 202A and the second transistor region 202B of the multi-gate device 200. For example, semiconductor layer 215 of the semiconductor layer stack 210 exposed by the gate opening 350 is selectively removed from the channel region of the multi-gate device 200, thereby forming suspended semiconductor layers 220' that are spaced apart from each other and / or separated from the fin portion 206' by gap 365A. The silicon-germanium sacrificial layer 258 (and dielectric liner 235) are also selectively removed from the channel region of the multi-gate device 200, thereby forming gap 365B between the suspended semiconductor layer 220' and the gate isolation fins 280A, 280B. Therefore, the first transistor region 202A and the second transistor region 202B each have three suspended semiconductor layers 220' stacked vertically along the z-direction to provide three channels through which current can flow between the corresponding epitaxial source / drain features 320A, 320B during transistor operation corresponding to the first transistor region 202A and the second transistor region 202B, respectively. The suspended semiconductor layer 220' is therefore referred to hereinafter as channel layer 220'. In the depicted embodiment, the top surface of the topmost channel layer 220' is lower than the top surface of the gate isolation fin 280B in the channel region of the multi-gate device 200 (i.e., the transistor channel height is less than the height of the gate isolation fin 280B relative to the top surface of the substrate 206), and is substantially planar with the top surface of the gate isolation fin 280A in the channel region of the multi-gate device 200. Spacing s1 is located between channel layers 220' along the z-direction, and spacing s2 is located between channel layers 220' and gate isolation fins 280A and 280B along the x-direction. Spacing s1 and spacing s2 correspond to the widths of gaps 365A and 365B, respectively. In some embodiments, spacing s1 is approximately equal to the thickness t1 of semiconductor layer 215, and spacing s2 is approximately equal to the sum of the thickness of silicon-germanium sacrificial layer 258 and dielectric liner 235. In some embodiments, spacing s1 is approximately 8 nm to approximately 15 nm. In some embodiments, spacing s2 is approximately 8 nm to approximately 15 nm. In some embodiments, channel layers 220' have nanoscale dimensions and may be referred to individually or collectively as "nanostructures". For example, each channel layer 220' may have a width of approximately 8 nm to approximately 100 nm along the x-direction, a length of approximately 8 nm to approximately 100 nm along the y-direction, and a thickness of approximately 3 nm to approximately 10 nm along the z-direction. The channel layer 220' may have a cylindrical profile (e.g., nanowires), a rectangular profile (e.g., nanorods), a sheet-like profile (e.g., nanosheets) (e.g., dimensions in the XY plane are larger than dimensions in the XZ and YZ planes to form a sheet structure), or any other suitable shape. In some embodiments, the channel layer 220' has sub-nanometer dimensions and / or other suitable dimensions.

[0053] In some embodiments, an etching process is performed to selectively etch the semiconductor layer 215 and the silicon-germanium sacrificial layer 258, wherein the semiconductor layer 220, fin portion 206', isolation feature 255, gate isolation fins 280A, 280B, gate spacer 299, internal spacer 310A, internal spacer 310B, CESL 330, and / or ILD protective layer 334 are minimally etched (to the point of no etching). For example, an etchant is selected for the etching process that etches silicon-germanium (i.e., semiconductor layer 215 and silicon-germanium sacrificial layer 258) and dielectric materials (i.e., isolation feature 255, gate isolation fins 280A, 280B, gate spacer 299, internal spacer 310A, internal spacer 310B, CESL 330, and / or ILD protective layer 334) at a higher rate than etching silicon (i.e., semiconductor layer 220 and fin portion 206') (i.e., the etchant has high etch selectivity relative to silicon-germanium). The etching process is dry etching, wet etching, or a combination thereof. In some embodiments, dry etching uses a fluorine-containing gas (e.g., SF6) to selectively etch the semiconductor layer 215 and the silicon-germanium sacrificial layer 258. In some embodiments, wet etching uses an etching solution comprising NH4OH and H2O to selectively etch the semiconductor layer 215 and the silicon-germanium sacrificial layer 258. In some embodiments, a chemical vapor deposition (CVD) etching process using HCl selectively removes the semiconductor layer 215 and the silicon-germanium sacrificial layer 258. In some embodiments, an oxidation process may be performed prior to the etching process to convert the semiconductor layer 215 and / or the silicon-germanium sacrificial layer 258 into silicon-germanium oxide features, wherein the etching process subsequently removes the silicon-germanium oxide features. In some embodiments, the etching process uses a patterned mask layer as an etching mask, wherein the patterned mask layer covers the ILD protective layer 334, CESL 330, gate spacer 299, and / or gate isolation fins, but has an opening that exposes the semiconductor layer 220 and the silicon-germanium sacrificial layer 258 in the channel region of the multi-gate device 200. In some embodiments, the etching process includes multiple steps. For example, a two-step channel release process may include a first etching for removing the silicon-germanium sacrificial layer 258 and a second etching for removing the semiconductor layer 215 and the dielectric liner 235. In some embodiments, after removing the semiconductor layer 215 and the silicon-germanium sacrificial layer 258, an etching process may be performed to modify the contour of the channel layer 220' to achieve a target size and / or target shape for the channel layer 220'.

[0054] In some embodiments, the channel release process partially, but minimally, etches the dielectric liner 262 of the dielectric feature 260 of the gate isolation fins 280A, 280B and / or the dielectric liner 272 of the dielectric feature 270 of the gate isolation fins 280A, 280B. For example, in Figure 23In this process, the etching process slightly etches the dielectric liner 262 and the dielectric liner 272, thereby reducing the thickness of the dielectric liner 262 along the sidewalls of the dielectric feature 260 in the channel region of the multi-gate device 200, and reducing the thickness of the dielectric liner 272 along the sidewalls of the dielectric feature 270 in the channel region of the multi-gate device 200. In such an embodiment, after the channel release process, the thickness t9 of the sidewall portion of the dielectric liner 262 is less than the thickness t6 (and, in the depicted embodiment, less than the thickness t6 of the bottom portion of the dielectric liner 262), and after the channel release process, the thickness t10 of the sidewall portion of the dielectric liner 272 is less than the thickness t7 (and, in the depicted embodiment, less than the thickness t7 of the bottom portion of the dielectric liner 272). In a further description of such an embodiment, the sidewall portion of the dielectric liner 262 has a thickness t9 in the channel region of the multi-gate device 200, while the sidewall portion of the dielectric liner 262 has a thickness t6 in the source / drain region of the multi-gate device 200. In a further description of such an embodiment, the sidewall portion of the dielectric liner 272 has a thickness t10 in the channel region of the multi-gate device 200, while the sidewall portion of the dielectric liner 272 has a thickness t7 in the source / drain region of the multi-gate device 200. Therefore, the dielectric liner 262 and the dielectric liner 272 can respectively protect the oxide layer 264 and the dielectric layer 274 from etching during the channel release process. In some embodiments, the channel release process partially, but minimally, etches the dielectric cap layer 276 of the dielectric feature 270 of the gate isolation fin 280B. For example, the thickness of the dielectric cap layer 276 after the channel release process can be less than the thickness t8. In some embodiments, the channel release process partially, but minimally, etches the semiconductor layer 220, the fin portion 206', and / or the isolation feature 255. For example, in Figure 23 In the etching process, the fin portion 206' is slightly recessed, such that, relative to the top surface of the substrate 206, the topmost surface of the fin portion 206' in the channel region of the multi-gate device 200 is lower than the topmost surface of the fin portion 206' in the source / drain region of the multi-gate device 200. In a further description of such an embodiment, in Figure 23In this process, the etching process also slightly recesses the portion of the isolation feature 255 exposed by the gate opening 350, such as the portion of the isolation feature 255 not covered by the gate isolation fins 280A and 280B. The etching process does not recess the portion of the oxide layer 250 disposed beneath the gate isolation fins 280A and 280B, such that the isolation feature 255 has an oxide extension 250' in the channel region of the multi-gate device 200. In such an embodiment, the topmost surface of the fin portion 206' in the channel region of the multi-gate device 200 is lower than the topmost surface of the oxide extension 250' of the isolation feature 255 relative to the top surface of the substrate 206. In some embodiments, the topmost surface of the recessed portion of the isolation feature 255 is substantially planar with the topmost surface of the fin portion 206' in the channel region of the multi-gate device 200. In some embodiments, the etching process may reduce the width and / or thickness of the semiconductor layer 220 along the x and z directions, respectively, such that the width and / or thickness of the trench layer 220' is less than the width and / or thickness (e.g., thickness t2) of the semiconductor layer 220 before the etching process.

[0055] Go to Figure 24A metal gate 370 (also referred to as a metal gate stack and / or a high-k / metal gate) is formed in the gate opening 350. The metal gate 370 is configured to achieve the desired functionality according to the design requirements of the multi-gate device 200. Each metal gate 370 includes a gate dielectric 372 (e.g., a gate dielectric layer) and a gate electrode 374 (e.g., a work function layer and a bulk conductive layer). The metal gate 370 may include many other layers, such as a capping layer, an interface layer, a diffusion layer, a barrier layer, a hard mask layer, or a combination thereof. In some embodiments, forming the metal gate 370 includes: depositing a gate dielectric layer over the multi-gate device 200, wherein the gate dielectric layer partially fills the gate opening 350; depositing a gate electrode layer over the gate dielectric layer, wherein the gate electrode layer fills the remaining portion of the gate opening 350; and performing a planarization process to remove excess gate material from the multi-gate device 200. For example, the CMP process is performed until the top surface of the ILD protective layer 334 is reached (exposed), such that after the CMP process, the top surface of the gate structure 300 is substantially planar with the top surface of the ILD protective layer 334. The metal gate 370 fills gaps 365A and 365B. The metal gate 370 surrounds the channel layer 220'. The gate dielectric 372 and gate electrode 374 extend uninterruptedly from the first transistor region 202A to the second transistor region 202B. Since the metal gate 370 spans the first transistor region 202A and the second transistor region 202B, the metal gate 370 can have different layers in the regions corresponding to the first transistor region 202A and the second transistor region 202B. For example, the number, configuration, and / or material of the layers of the gate dielectric 372 and / or gate electrode 374 corresponding to the second transistor region 202B can differ from the number, configuration, and / or material of the layers of the gate dielectric 372 and / or gate electrode 374 corresponding to the first transistor region 202A.

[0056] Gate dielectric 372 partially fills gate opening 350 and surrounds the corresponding channel layer 220', such that gate dielectric 372 partially fills gaps 365A and gaps 365B. In the depicted embodiment, gate dielectric 372 covers the top surface, bottom surface, and sidewalls of channel layer 220'. For example, gate dielectric 372 surrounds channel layer 220' such that each channel layer 220' is surrounded and / or surrounded by a corresponding gate dielectric 372. In some embodiments, in the channel region of multi-gate device 200, gate dielectric 372 is also disposed over fin portion 206', isolation feature 255, first portion 280A-1 of gate isolation fin 280A, and gate isolation fin 280B. In the depicted embodiment, each gate opening 350 is partially filled with a corresponding gate dielectric 372, which is disposed over the fin portion 206', the isolation feature 255, the first portion 280A-1 of the gate isolation fin 280A, and the gate isolation fin 280B, extending uninterruptedly from the first transistor region 202A to the second transistor region 202B. The gate dielectric 372 includes a high-k dielectric layer comprising a high-k dielectric material, which, with respect to the metal gate 370, refers to a dielectric material with a dielectric constant greater than that of silicon dioxide. For example, high-k dielectric layers include HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials for metal gate stacking, or combinations thereof. The high-k dielectric layer is formed by any of the processes described herein, such as ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or combinations thereof. For example, the high-k dielectric layer is deposited by ALD. In some embodiments, ALD is a conformal deposition process that makes the thickness of the high-k dielectric layer substantially uniform across various surfaces of the multi-gate device 200. In some embodiments, the gate dielectric 372 includes an interface layer disposed between the high-k dielectric layer and the channel layer 220'. The interface layer includes a dielectric material, such as SiO2, HfSiO, SiON, other silicon-containing dielectric materials, other suitable dielectric materials, or combinations thereof. The interface layer is formed by any of the processes described herein, such as thermal oxidation, chemical oxidation, ALD, CVD, other suitable processes, or combinations thereof. For example, the interface layer is formed by a chemical oxidation process that exposes the channel layer 220' to hydrofluoric acid. In some embodiments, the interface layer is formed by a thermal oxidation process that exposes the channel layer 220' to an oxygen and / or air environment.In some embodiments, an interface layer is formed after the high-k dielectric layer is formed. For example, after the high-k dielectric layer is formed, the multi-gate device 200 may be annealed in an oxygen and / or nitrogen environment (e.g., nitrogen oxides).

[0057] A gate electrode 374 is formed on the gate dielectric 372, filling the remaining portion of the gate opening 350 and surrounding the corresponding channel layer 220', such that the gate electrode 374 fills the remaining portions of gaps 365A and 365B. In the depicted embodiment, the gate electrode 374 is disposed along the top surface, bottom surface, and sidewalls of the channel layer 220'. For example, the gate electrode 374 surrounds the channel layer 220'. In some embodiments, in the channel region of the multi-gate device 200, the gate electrode 374 is also disposed on the fin portion 206', the isolation feature 255, the first portion 280A-1 of the gate isolation fin 280A, and the gate isolation fin 280B, extending uninterruptedly from the first transistor region 202A to the second transistor region 202B. Gate electrode 374 comprises a conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, molybdenum, cobalt, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some embodiments, gate electrode 374 comprises a work function layer and a bulk conductive layer. The work function layer may be a metal layer tuned to have a desired work function (e.g., an n-type work function or a p-type work function), and the bulk conductive layer may be a bulk metal layer formed on the work function layer. In some embodiments, the work function layer comprises an n-type work function material, such as Ti, silver, manganese, zirconium, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-type work function materials, or combinations thereof. In some embodiments, the work function layer comprises a p-type work function material, such as ruthenium, Mo, Al, TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. The bulk (or filling) conductive layer comprises a suitable conductive material, such as Al, W, Ti, Ta, polysilicon, Cu, metal alloys, other suitable materials, or combinations thereof. The gate electrode 374 is formed by any of the processes described herein, such as ALD, CVD, PVD, electroplating, other suitable processes, or combinations thereof.

[0058] Go to Figure 25 A self-aligned metal gate dicing process is performed to remove a portion of the metal gate 370 to form a metal gate 370A in a first transistor region 202A and a metal gate 370B in a second transistor region 202B (see [link]). Figure 27BThe gate isolation fin 280B separates and isolates the metal gate 370A from the metal gate 370B. For example, an etch-back process is performed to recess the gate electrode 374 until the top surface of the gate isolation fin 280B is free of the gate electrode 374 (i.e., the gate electrode 374 is not disposed on the top surface of the gate isolation fin 280B and does not extend to the top surface of the gate isolation fin 280B). The etch-back process reopens the gate opening 350. After the etch-back process, the gate electrode 374 no longer extends uninterruptedly from the first transistor region 202A to the second transistor region 202B, thereby forming the gate electrode 374A in the first transistor region 202A and the gate electrode 374B in the second transistor region 202B (see [reference]). Figure 27B In this embodiment, gate isolation fin 280B separates gate electrode 374A and gate electrode 374B from each other. In some embodiments, as shown, an etch-back process partially removes the portion of gate electrode 374 disposed above gate isolation fin 280A, such that gate electrodes 374A and 374B remain and extend onto gate isolation fin 280A (specifically, the first portion 280A-1 of gate isolation fin 280A). In some embodiments, the etch-back process also completely removes the portion of gate electrode 374 disposed above gate isolation fin 280B, such that gate electrodes 374A and 374B do not extend onto gate isolation fin 280B. In the depicted embodiment, the top surfaces of gate electrodes 374A and 374B are lower than the top surface of gate isolation fin 280B and higher than the top surface of gate isolation fin 280A relative to the top surface of substrate 206. For example, the height difference between the topmost surface of gate electrodes 374A and 374B and the topmost surface of gate isolation fin 280B (e.g., the topmost surface of dielectric cap layer 276). h3 is approximately 5 nm to approximately 20 nm. In some embodiments, the top surfaces of the gate electrodes 374A and 374B are substantially planar with the top surface of the gate isolation fin 280B. In some embodiments, the top surfaces of the gate electrodes 374A and 374B are substantially planar with the top surface of the gate isolation fin 280A. In a further description of the embodiments, the etch-back process does not etch or etches the gate dielectric 372 minimally, such that the gate dielectric 372 still extends uninterruptedly from the first transistor region 202A to the second transistor region 202B, and is also retained entirely or partially along the sidewalls of the gate spacer 299 depending on the amount of etching. Thus, the metal gate 370A includes a corresponding portion of the respective gate dielectric 372 and the respective gate electrode 374A, and the metal gate 370B includes a corresponding portion of the respective gate dielectric 372 and the respective gate electrode 374B.

[0059] The metal gate dicing process is referred to as "self-aligned" because the gate isolation structure (here, gate isolation fin 280B) is aligned between metal gates 370A and 370B without requiring a photolithography process after the metal gate 370 is formed. This self-aligned arrangement of the gate isolation structure provides electrical isolation between different devices (e.g., transistors) of the multi-gate device 200. The etch-back process is configured to selectively remove the gate electrode 374 relative to the gate dielectric 372, ILD protection layer 334, CESL 330, gate spacer 299, and / or gate isolation fins 280A, 280B. In other words, the etch-back process substantially removes the gate electrode 374 but does not remove or substantially does not remove the gate dielectric 372, ILD protection layer 334, CESL 330, gate spacer 299, and / or gate isolation fins 280A, 280B. For example, an etchant is selected for an etching process that etches a metallic material (e.g., gate electrode 374) at a higher rate than the etching dielectric material (e.g., gate dielectric 372, ILD protective layer 334, CESL 330, gate spacer 299, and / or gate isolation fins 280A, 280B (specifically, dielectric housing 278)) (i.e., the etchant has high etch selectivity relative to the metallic material). The etchback process is dry etching, wet etching, other suitable etching processes, or a combination thereof. In some embodiments, the etchback process is wet etching, using a wet etchant solution comprising NH4OH, H2O2, and H2O to remove the metallic material while substantially not removing the dielectric material. In some embodiments, the etchback process includes multiple steps, such as a first etching step for removing a first layer (or a first set of layers) of the gate electrode 374 and a second etching step for removing a second layer (or a second set of layers) of the gate electrode 374.

[0060] Then, a metal cap layer is formed in the gate opening above the gate electrodes 374A and 374B. For example, a metal cap layer 380A is formed above the gate electrode 374A, and a metal cap layer 380B is formed above the gate electrode 374B. The metal cap layers 380A and 380B have a height difference smaller than the height difference. The thickness h3 is such that the metal cap layers 380A and 380B are disposed below the top surface of the gate isolation fin 280B and partially fill the gate opening 350. In some embodiments, this thickness is about 2 nm to about 6 nm. The metal cap layers 380A and 380B include tungsten, tungsten alloys, ruthenium, ruthenium alloys, cobalt, cobalt alloys, copper, copper alloys, aluminum, aluminum alloys, iridium, iridium alloys, palladium, palladium alloys, platinum, platinum alloys, nickel, nickel alloys, titanium, titanium alloys (e.g., TiN), tantalum, tantalum alloys (e.g., TaN), other low resistivity metal components and / or alloys thereof, or combinations thereof. In the depicted embodiments, the metal cap layers 380A and 380B are tungsten layers, such as fluorine-free tungsten layers. In some embodiments, the metal cap layers 380A and 380B are formed by a bottom-up deposition process, which generally refers to a bottom-up filling of the opening. In some embodiments, the bottom-up deposition process is selective CVD, wherein various parameters of the selective CVD are tuned to selectively grow tungsten, ruthenium, cobalt, or alloys thereof from the metal cap seed layer, while limiting (or preventing) the growth of tungsten, ruthenium, cobalt, or alloys thereof from the gate isolation fins 280A, 280B, CESL 330, and / or ILD protective layer 334. In some embodiments, the metal cap layers 380A, 380B are deposited by another suitable selective deposition process. In some embodiments, the metal cap layers 380A, 380B are formed by uniformly depositing a metal cap material over the multi-gate device 200 and patterning the metal cap material. In some embodiments, a metal cap seed layer is formed over the gate electrodes 374A, 374B prior to, for example, forming the metal cap layers 380A, 380B by PVD. In these embodiments, the metal cap seed layer is considered to be part of the metal cap layers 380A, 380B. The metal cap seed layer comprises a metal-containing material that promotes the growth and / or deposition of the metal cap layers 380A and 380B, and promotes the adhesion of the metal cap layers 380A and 380B to the gate electrodes 374A and 374B. The metal-containing material may include titanium, titanium alloys, tantalum, tantalum alloys, cobalt, cobalt alloys, ruthenium, ruthenium alloys, molybdenum, molybdenum alloys, palladium, palladium alloys, other suitable components, or combinations thereof. For example, the metal cap seed layer includes tantalum, tantalum nitride, aluminum tantalum nitride, silicon tantalum nitride, tantalum carbide, titanium, titanium nitride, silicon titanium nitride, aluminum titanium nitride, titanium carbide, tungsten, tungsten nitride, tungsten carbide, molybdenum nitride, cobalt, cobalt nitride, ruthenium, palladium, or combinations thereof. In the depicted embodiment, when the metal cap layers 380A and 380B are tungsten layers, the metal cap seed layer may be a titanium nitride layer disposed between the metal cap layers 380A and 380B and the gate electrodes 374A and 374B. In some embodiments, the thickness of the metal cap seed layer is less than about 2 nm.

[0061] A dielectric cap layer is then formed over the metal cap layers 380A and 380B within the gate opening. For example, a dielectric cap layer 385 is formed over the metal cap layers 380A and 380B. The dielectric cap layer 385 fills the remaining portion of the gate opening and can improve the photolithography process window associated with forming the source / drain contacts to the epitaxial source / drain features 320A and 320B (e.g., increasing the overlay boundary). Along the x-direction, the dielectric cap layer 385 spans the first transistor region 202A and the second transistor region 202B, and extends over and surrounds the top of the gate isolation fin 280B. Along the y-direction, the dielectric cap layer 385 is disposed between the CESL 330 and the gate spacer 299 and physically contacts the CESL 330 and the gate spacer 299. In some embodiments, as shown, the width of the dielectric cap layer 385 between CESL 330 is greater than the width of the dielectric cap layer 385 between gate spacers 299. The dielectric cap layer 385 comprises a material different from that of the ILD layer 332 to achieve etch selectivity and / or planarization selectivity during subsequent processing. For example, where the ILD layer 332 comprises a silicon- and oxygen-containing material, the dielectric cap layer 385 may comprise a silicon- and nitrogen-containing material, such as silicon nitride, silicon oxynitride, or silicon carbonitride. In some embodiments, the dielectric cap layer 385 comprises silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonate, other suitable materials, or combinations thereof. In some embodiments, the dielectric cap layer 385 comprises a metal- and oxygen-containing material and / or a metal- and nitrogen-containing material, such as aluminum oxide (e.g., AlO or Al2O3), aluminum nitride (e.g., AlN), aluminum oxynitride (e.g., AlON), zirconium oxide (e.g., Zr or ZrO2), zirconium nitride (e.g., ZrN), hafnium oxide (e.g., HfO or HFO2), aluminum zirconium oxide (e.g., ZrAlO), other metal oxides, other metal nitrides, or combinations thereof. In some embodiments, a deposition process and a planarization process are performed to form the dielectric cap layer 385 over the metal cap layers 380A, 380B. For example, fabrication continues: a dielectric cap material is deposited over the multi-gate device 200 filling the remaining portion of the gate opening, and a planarization process (e.g., CMP) is performed on the dielectric cap material until the ILD layer 332, which acts as a planarization stop layer, is reached and exposed. Thus, the planarization process can remove the ILD protective layer 334 from the multi-gate device 200. In some embodiments, a planarization process removes portions of CESL 330 that extend above the top surface of ILD layer 332. The dielectric cap material can be formed by CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof.

[0062] Then, fabrication can continue to form various contacts, such as gate contacts and source / drain contacts, to facilitate the operation of the transistors in the multi-gate device 200. (Go to...) Figure 26 and Figures 27A-27E Gate contact 390 and source / drain contact 392 are formed to epitaxial source / drain features 320A and 320B, and gate contact 390 is formed to metal gates 370A and 370B. For ease of description and understanding, Figure 26 In experiencing and Figures 2-26 A perspective view of the multi-gate device 200 after associated processing; Figure 27A In experiencing and Figures 2-26 Top view of the multi-gate device 200 after associated processing; Figure 27B It is along Figure 27A The cross-sectional view of line BB in the middle (which is along the longitudinal direction of one of the gate structures 300 and can be referred to as the metal gate x-cut cross-sectional view); Figure 27C It is along Figure 27A The cross-sectional view of line CC in the middle (which is along the longitudinal direction of one of the source / drain contacts 392, and can be referred to as the source / drain x-cut cross-sectional view); Figure 27D It is along Figure 27A A cross-sectional view of line DD in the diagram (which runs along gate isolation fin 280B, its longitudinal direction being substantially parallel to the longitudinal direction of the active region of multi-gate device 200 (e.g., channel layer 220' / fin portion 206')); and Figure 27E It is along Figure 27A A cross-sectional view of the line EE (which runs along the gate isolation fin 280A, its longitudinal direction being substantially parallel to the longitudinal direction of the active region of the multi-gate device 200 (e.g., channel layer 220' / fin portion 206'). Figure 26 and Figures 27A-27E In the depicted embodiment, gate contact 390 and source / drain contact 392 extend through ILD layer 395, CESL 397, dielectric cap layer 385, ILD layer 332 and / or CESL 330 to metal gates 370A, 370B and epitaxial source / drain features 320A, 320B, respectively. In the depicted embodiment, gate contact 390 further extends through metal cap layers 380A, 380B and physically contacts gate electrodes 374A, 374B. Source / drain contact 392 may physically contact epitaxial source / drain features 320A, epitaxial source / drain features 320B, or both epitaxial source / drain features 320A and epitaxial source / drain features 320B (see [reference]). Figure 27CIn some embodiments, the gate contact 390 and / or the source / drain contact 392 are formed by depositing a CESL 397 on the multi-gate device 200 (specifically on the dielectric cap layer 385, CESL 330, and ILD layer 332), depositing an ILD layer 395 on the CESL 397, patterning the dielectric layers (e.g., ILD layers 395, 332, CESL 397, 330, and / or dielectric cap layer 385) to form gate openings and / or source / drain contact openings, and filling the gate openings and / or source / drain contact openings with a conductive material. Patterning the ILD layers 395, 332, and / or CESL 397, 330 may include photolithography and / or etching processes. In some embodiments, the photolithography process includes: forming a resist layer over an ILD layer 395, exposing the resist layer to patterning radiation, and developing the exposed resist layer to form a patterned resist layer. This patterned resist layer can serve as a masking element for etching gate openings and / or source / drain contact openings extending through ILD layers 395, CESL 397, ILD layers 332, CESL 330, and / or dielectric cap layer 385 to expose metal gates 370A, 370B and / or epitaxial source / drain features 320A, 320B. The etching process includes dry etching, wet etching, other etching processes, or combinations thereof. Subsequently, the gate openings and / or source / drain contact openings are filled with one or more conductive materials, such as tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, other low-resistivity metal components, alloys thereof, or combinations thereof. One or more conductive materials may be deposited by PVD, CVD, ALD, electroplating, electroless plating, other suitable deposition processes, or combinations thereof. In some embodiments, the gate contact 390 and / or the source / drain contact 392 includes a body layer (also referred to as a conductive plug). In some embodiments, the gate contact 390 and / or the source / drain contact 392 includes a barrier layer, an adhesive layer, and / or other suitable layers disposed between the body layer and the surrounding dielectric layer (e.g., ILD layer 395, CESL 397, ILD layer 332, CESL 330, and / or dielectric cap layer 385). In such embodiments, the barrier layer and / or adhesive layer coincide with the gate opening and / or the source / drain contact opening, such that the barrier layer and / or adhesive layer is disposed on the dielectric layer, and the body layer is disposed on the barrier layer and / or adhesive layer. In some embodiments, the barrier layer, adhesive layer, and / or other suitable layers include titanium, titanium alloys (e.g., TiN), tantalum, tantalum alloys (e.g., TaN), other suitable components, or combinations thereof. Subsequently, any excess conductive material (one or more) can be removed by a planarization process (e.g., CMP) to planarize the top surface of the ILD layer 395 and the top surfaces of the gate contact 390 and / or the source / drain contact 392.In some embodiments, prior to forming the source / drain contacts 392, a silicide layer 398 is formed over the epitaxial source / drain features 320A, 320B by forming a metal layer over the epitaxial source / drain features 320A, 320B and heating the multi-gate device 200 to react the components of the epitaxial source / drain features 320A, 320B with the metal components of the metal layer. The silicide layer 398 can be considered a portion of the epitaxial source / drain features 320A, 320B and / or a portion of the source / drain contacts 392. In some embodiments, the silicide layer 398 comprises a metal component (e.g., nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, other suitable metals or combinations thereof) and a component of the epitaxial source / drain features 320A, 320B (e.g., silicon and / or germanium). In some embodiments, contact spacers 399 are formed along the sidewalls of the source / drain contacts 392. Contact spacer 399 may include any suitable dielectric material as described herein.

[0063] Therefore, the multi-gate device 200 includes a first transistor in a first transistor region 202A and a second transistor in a second transistor region 202B. The first transistor has a metal gate 370A (each metal gate 370A includes a corresponding portion of a gate dielectric 372 and a corresponding portion of a gate electrode 374A), and the second transistor has a metal gate 370B (each metal gate 370B includes a corresponding portion of a gate dielectric 372 and a corresponding portion of a gate electrode 374B). Each first transistor also includes a corresponding epitaxial source / drain feature 320A, and each second transistor also includes a corresponding epitaxial source / drain feature 320B. Each metal gate 370A surrounds a corresponding channel layer 220' and is disposed between the corresponding epitaxial source / drain features 320A. Each metal gate 370B surrounds a corresponding channel layer 220' and is disposed between the corresponding epitaxial source / drain features 320B. (In the metal gate cross-sectional view...) Figure 27BIn this embodiment, a metal gate 370A is disposed between and in physical contact with a gate isolation fin 280B and a corresponding gate isolation fin 280A (specifically, a first portion 280A of the corresponding gate isolation fin 280A), and a metal gate 370B is disposed between and in physical contact with a gate isolation fin 280B and a corresponding gate isolation fin 280A (specifically, a first portion 280A of the corresponding gate isolation fin 280A). Metal gates 370A and 370B are also disposed on and in physical contact with the top, sidewalls, and bottom of the respective channel layers 220', with the top and bottom extending between the respective sidewalls. Therefore, metal gates 370A and 370B completely surround their respective channel layers 220', such that the first and second transistors of the multi-gate device 200 can be referred to as GAA transistors. In the depicted embodiment, metal gates 370A and 370B cover all four sides of their respective channel layers 220'. This disclosure envisions embodiments in which metal gates 370A, 370B cover more or fewer four sides of their respective channel layers 220', depending on the configuration of the channel layers 220' and / or the multi-gate devices 200.

[0064] Gate isolation fins 280B separate and isolate transistor regions, and gate isolation fins 280A separate and / or isolate device features and / or transistor features within transistor regions from each other. For example, gate isolation fins 280B separate and / or isolate the metal gate 370A of the first transistor in the first transistor region 202A from the metal gate 370B of the second transistor in the second transistor region 202B, and gate isolation fins 280A separate and / or isolate the metal gates 370A, 370B and / or the epitaxial source / drain features 320A, 320B from other gate and / or source / drain features within their respective first transistor region 202A or second transistor region 202B. In some embodiments, where the first transistor region 202A and the second transistor region 202B are processed to form a first CMOS transistor and a second CMOS transistor, respectively, a self-aligned metal gate dicing technique separates the metal gate 370A of the first CMOS transistor from the metal gate 370B of the second CMOS transistor. Fabricating the gate isolation fin 280B using the disclosed self-aligned metal gate dicing technique allows for a reduction in the spacing between active regions. Therefore, the disclosed self-aligned metal gate dicing technique described herein does not require consideration of photolithography process variations, thereby allowing for smaller spacing between the active regions of the transistor, resulting in smaller cell heights and further increasing transistor package density and IC patterning density. In some embodiments, the self-aligned metal gate dicing technique described herein can reduce patterning density by approximately 70% to approximately 85% compared to patterning density achieved using non-self-aligned metal gate dicing techniques. In some embodiments, where the first transistor region 202A includes a first CMOS transistor and the second transistor region 202B includes a second CMOS transistor, the leftmost gate isolation fin 280A in the first transistor region 202A can separate and / or isolate the gate (e.g., metal gate 370A) and / or source / drain features (e.g., epitaxial source / drain features 320A) of the p-type transistor of the first CMOS transistor from the gate and / or source / drain features of the n-type transistor of the first CMOS transistor in the first transistor region 202A, or vice versa. Similarly, the rightmost gate isolation fin 280A in the second transistor region 202B can separate and / or isolate the gate (e.g., metal gate 370B) and / or source / drain features (e.g., epitaxial source / drain features 320B) of the n-type transistor of the second CMOS transistor from the gate and / or source / drain features of the p-type transistor of the second CMOS transistor in the second transistor region 202B, or vice versa.

[0065] As described above, the gate isolation fin 280A has different configurations in the channel region and source / drain region of the multi-gate device 200. For example, the gate isolation fin 280A includes a first portion 280A-1 in the channel region of the multi-gate device 200. Figure 27B , Figure 27D ) and includes a second portion 280A-2 in the source / drain region of the multi-gate device 200 ( Figure 27C , Figure 27D The first portion 280A-1 has a dielectric feature 260 (e.g., an oxide layer 264 disposed on a dielectric liner 262), and metal gates 370A and 370B extend over and cover the top surface of the dielectric feature 260 in the first portion 280A-1 of the gate isolation fin 280A. The second portion 280A-2 has a dielectric feature 270 disposed on the dielectric feature 260 (e.g., a dielectric cap layer 276, a dielectric layer 274, and a dielectric liner 272). In the XZ plane ( Figure 27C The second part 280A-2 has a dielectric feature 270 having a dielectric liner 272 surrounding a dielectric layer 274, and a CESL 330 surrounding the dielectric feature 270 of the second part 280A-2 (e.g., the CESL 330 covers the top surface and sidewalls of the dielectric feature 270). In the YZ plane ( Figure 27D The dielectric feature 270 of the second part 280A-2 has a U-shaped portion, which is formed by a first portion of the dielectric feature 270 located below the gate spacer 299 in the spacer region (S) (which can be considered as part of the source / drain region (S / D) and / or channel region (C)) and a second portion of the dielectric feature 270 in the source / drain region (which is not below the gate spacer 299). The first portion has a dielectric layer 274 disposed between the dielectric liner 272 and the dielectric cap layer 276. The second portion has a dielectric layer 274 disposed above the dielectric liner 272. The thickness of the dielectric layer 274 in the first portion is greater than the thickness of the dielectric layer 274 in the second portion. With this configuration, the source / drain contact 392 extends through the ILD layer 395, CESL 394, and dielectric cap layer 385 to the dielectric feature 270 of the gate isolation fin 280A, and in the depicted embodiment, the bottom of the source / drain contact 392 is surrounded by the U-shaped portion of the dielectric feature 270 of the second portion 280A-2 of the gate isolation fin 280A. Furthermore, the gate electrodes 374A, 347B, metal cap layers 380A, 380B, and dielectric cap layer 385 are disposed between the dielectric features 270 of the second portion 280A-2 and above the dielectric feature 260 of the first portion 280A-1.

[0066] The gate isolation fin 280B also has different configurations in the channel region and source / drain region of the multi-gate device 200. For example, the gate isolation fin 280B has a dielectric feature 270 disposed on the dielectric feature 260 in both the channel region and the source / drain region of the multi-gate device 200, and the dielectric feature 270 has different configurations in the channel region and the source / drain region. In the channel region of the multi-gate device 200, the dielectric feature 270 has a dielectric shell 278 (e.g., a dielectric liner 272 and a dielectric cap 276), the dielectric shell 278 being in the XZ plane ( Figure 27B ) surrounds the dielectric layer 274 (i.e., the dielectric core), while the dielectric feature 270 is in the YZ plane ( Figure 27E The device 200 has a dielectric layer 274 disposed between a dielectric liner 272 and a dielectric cap layer 276. In the source / drain region of the multi-gate device 200, the dielectric feature 270 is located in the XZ plane (…). Figure 27C ) has a dielectric liner 272 surrounding the dielectric layer 274, while the dielectric feature 270 is in the YZ plane ( Figure 27E It has a dielectric layer 274 disposed on the dielectric liner 272. In the YZ plane ( Figure 27EThe dielectric feature 270 of the gate isolation fin 280B also has a U-shaped portion formed by a first portion of the dielectric feature 270 in the spacer region and the channel region (not below the gate spacer 299) and a second portion of the dielectric feature 270 in the source / drain region. The first portion has a dielectric layer 274 disposed between the dielectric liner 272 and the dielectric cap layer 276. The second portion has a dielectric layer 274 disposed above the dielectric liner 272. The thickness of the dielectric layer 274 in the first portion is greater than the thickness of the dielectric layer 274 in the second portion. With such a configuration in the YZ plane, the source / drain contact 392 extends through the ILD layer 395, CESL 394 and the dielectric cap layer 385 to the dielectric feature 270 of the gate isolation fin 280B, and in the depicted embodiment, the bottom of the source / drain contact 392 is also surrounded by the dielectric feature 270 of the gate isolation fin 280B. For example, a portion of the dielectric feature 270 in the spacer region is disposed along the sidewall of the source / drain contact 392, and a portion of the dielectric feature in the source / drain region is disposed along the bottom of the source / drain contact 392. Furthermore, a dielectric cap layer 385 is disposed between the gate spacers 299 and above the top surface of the dielectric feature 270 of the gate isolation fin 280B. Additionally, in the depicted embodiment, the height of the dielectric feature 270 of the gate isolation fin 280B in the source / drain region of the multi-gate device 200 is less than the height of the dielectric feature 270 of the gate isolation fin 280B in the channel region and spacer region of the multi-gate device 200. In the depicted embodiment, the interface between the dielectric feature 270 and the dielectric feature 260 of the gate isolation fin 280B is at substantially the same height as the top surface of the topmost channel layer 220' of the multi-gate device 200. In some embodiments, the interface between dielectric features 270 and 260 of the gate isolation fin 280B is below the top surface of the topmost channel layer 220' of the multi-gate device 200, such as... Figure 28 As shown. In some embodiments, the interface between dielectric features 270 and 260 of the gate isolation fin 280B is higher than the top surface of the topmost channel layer 220' of the multi-gate device 200, as... Figure 29 As shown.

[0067] Gate isolation fins 280A and 280B are configured to enhance the performance of the multi-gate device 200. Specifically, since the dielectric feature 270 of gate isolation fins 280A and 280B includes both low-k and high-k dielectric materials, and not just high-k dielectric materials, gate isolation fins 280A and 280B can reduce (and in some embodiments eliminate) leakage paths between the metal gate and source / drain contacts of the multi-gate device 200, which may be caused by voids formed in the high-k dielectric material. For example, it has been observed that voids are easily formed in the high-k dielectric upper portion of the gate isolation fin, where voids provide leakage paths between, for example, the gate of the multi-gate device (e.g., metal gates 370A, 370B) and the source / drain contacts (e.g., source / drain contact 392), which degrades device performance. As provided in multi-gate device 200, incorporating a low-k dielectric core in the upper portion of the gate isolation fin reduces (and in some embodiments eliminates) void formation in the gate isolation fin (specifically in dielectric feature 270), such that a multi-gate device with the proposed gate isolation fin structure can exhibit improved speed and gate-drain capacitance (C0) compared to a multi-gate device with a high-k dielectric core in the upper portion (i.e., the upper portion does not include low-k dielectric material). gd ) and power efficiency (P eff In some embodiments, a multi-gate device 200 having gate isolation fins 280A and 280B can reduce the gate-drain capacitance by about 3% to about 5% compared to a multi-gate device that includes only gate isolation fins of high-k dielectric material at the top. In some embodiments, a multi-gate device 200 having gate isolation fins 280A and 280B can operate about 3% to about 5% faster compared to a multi-gate device that includes only gate isolation fins of high-k dielectric material at the top. In some embodiments, a multi-gate device 200 having gate isolation fins 280A and 280B can improve power efficiency by about 4% to about 6% compared to a multi-gate device that includes only gate isolation fins of high-k dielectric material at the top. Gate isolation fins 280A and 280B thus improve the performance of the first transistor of the multi-gate device 200, the performance of the second transistor of the multi-gate device 200, and / or the overall performance of the multi-gate device 200. Different embodiments may have different advantages, and no particular embodiment necessarily requires a specific advantage.

[0068] Various parameters of the etching process described herein can be adjusted to achieve selective etching of one or more layers of the multi-gate device 200, such as the flow rate of the etching gas, the concentration of the etching gas, the concentration of the carrier gas, the ratio of the concentration of the first etching gas to the concentration of the second etching gas, the ratio of the carrier gas concentration to the etching gas concentration, the concentration of the wet etching solution, the ratio of the concentration of the first wet etching component to the concentration of the second wet etching component in the wet etching solution, the RF source power, the bias voltage, the pressure, the duration of the etching process, the temperature maintained in the process chamber during the etching process, the temperature of the wafer during the etching process, the temperature of the wet etching solution, other suitable etching parameters or combinations thereof. Dry etching can be performed using hydrogen-containing etching gases (e.g., H2 and / or CH4), nitrogen-containing etching gases (e.g., N2 and / or NH3), chlorine-containing etching gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), oxygen-containing etching gases (e.g., O2), fluorine-containing etching gases (e.g., F2, CH3F, CH2F2, CHF3, CF4, C2F6, SF6, and / or NF3), bromine-containing etching gases (e.g., Br, HBr, CH3Br, CH2Br2, and / or CHBr3), iodine-containing etching gases, other suitable etching gases, or combinations thereof. In some embodiments, dry etching can use a carrier gas to deliver the etching gas. The carrier gas includes nitrogen, argon, helium, xenon, other suitable carrier gas components, or combinations thereof. Wet etching can be performed using a wet etchant solution comprising H2SO4 (sulfuric acid), H2O2 (hydrogen peroxide), NH4OH (ammonium hydroxide), HCl (hydrochloric acid), HF (hydrofluoric acid), DHF (diluted HF), HNO3 (nitric acid), H3PO4 (phosphoric acid), H2O (water) (which can be deionized water (DIW) or ozonated deionized water (DIWO3)), ozone (O3), other suitable chemicals, or combinations thereof.

[0069] The gate isolation technique disclosed herein forms gate isolation fins to isolate the metal gates of a multi-gate device, such as a GAA device, from each other before the multi-gate device is formed, specifically before the metal gates of the multi-gate device are formed. As can be seen from the foregoing description, the multi-gate devices described herein offer advantages over conventional multi-gate devices. However, it should be understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein, nor are any specific advantages required for any embodiment.

[0070] This disclosure provides numerous different embodiments. One exemplary device includes: a first multi-gate device having a first source / drain feature and a first metal gate surrounding a first channel layer; and a second multi-gate device having a second source / drain feature and a second metal gate surrounding a second channel layer. Gate isolation fins separating the first metal gate and the second metal gate include dielectric features having: a first dielectric layer having a first dielectric constant (e.g., a low-k dielectric core), and a second dielectric layer surrounding the first dielectric layer (e.g., a high-k dielectric shell). The second dielectric layer has a second dielectric constant greater than the first dielectric constant. In some embodiments, the second dielectric layer has a first thickness along the bottom of the first dielectric layer, a second thickness along the sidewalls of the first dielectric layer, and a third thickness along the top of the first dielectric layer. The third thickness is greater than the first thickness and the second thickness. In some embodiments, the second thickness along the sidewalls of the first dielectric layer is less than the first thickness along the bottom of the first dielectric layer. In some embodiments, the device further includes source / drain contacts for the first source / drain feature and the second source / drain feature. The source / drain contacts are in contact with the dielectric feature of the gate isolation fin. In some embodiments, the gate isolation fin is a first gate isolation fin disposed along a first sidewall of the first metal gate, and the device further includes a second gate isolation fin, wherein the second gate isolation fin is different from the first gate isolation fin. The second gate isolation fin is disposed along a second sidewall of the first metal gate.

[0071] In some embodiments, the dielectric feature is a first dielectric feature, and the gate isolation fin further includes a second dielectric feature. The first dielectric feature is disposed on top of the second dielectric feature. The second dielectric feature has: a third dielectric layer having a third dielectric constant, and a fourth dielectric layer surrounding the third dielectric layer. The fourth dielectric layer has a fourth dielectric constant that is less than the second dielectric constant. In some embodiments, the first dielectric constant is the same as the fourth dielectric constant, and the third dielectric constant is different from both the first and second dielectric constants. In some embodiments, the third dielectric constant is less than both the first and second dielectric constants.

[0072] In some embodiments, the gate isolation fin is further disposed between the first source / drain feature and the second source / drain feature, separating the first source / drain feature and the second source / drain feature. In such an embodiment, the gate isolation fin has a first height between the first source / drain feature and the second source / drain feature, and a second height between the first metal gate and the second metal gate. The first height is less than the second height. In some embodiments, the second dielectric layer of the dielectric feature surrounds the first dielectric layer of the dielectric feature between the first metal gate and the second metal gate, and the second dielectric layer of the dielectric feature surrounds the first dielectric layer of the dielectric feature between the first source / drain feature and the second source / drain feature.

[0073] Another exemplary device includes: an isolation feature disposed on a substrate and a gate isolation fin disposed on the isolation feature. The isolation feature is disposed between a first fin portion and a second fin portion extending from the substrate. The gate isolation fin includes an upper dielectric feature and a lower dielectric feature. The upper dielectric feature has a low-k dielectric core surrounded by a high-k dielectric shell. The device also includes a first multi-gate device having a first channel layer disposed on the first fin portion, a first metal gate surrounding the first channel layer, and a first source / drain feature. The first metal gate is disposed between the first channel layer and the first fin portion. The device also includes a second multi-gate device having a second channel layer disposed on the second fin portion, a second metal gate surrounding the second channel layer, and a second source / drain feature. The second metal gate is disposed between the second channel layer and the second fin portion. The gate isolation fin separates the first metal gate of the first multi-gate device from the second metal gate of the second multi-gate device. In some embodiments, the lower dielectric feature has a low-k dielectric layer surrounding an oxide core. In some embodiments, the high-k dielectric shell includes a high-k dielectric liner and a high-k cap layer. The high-k cap layer is disposed between the sidewall portions of the high-k dielectric liner. In some embodiments, the upper dielectric feature has a first height between the first metal gate and the second metal gate, and a second height between the first source / drain feature and the second source / drain feature.

[0074] In some embodiments, the isolation feature is a first isolation feature, the gate isolation fin is a first gate isolation fin, the lower dielectric feature is a first lower dielectric feature, the upper dielectric feature is a first upper dielectric feature, the low-k dielectric core is a first low-k dielectric core, and the high-k dielectric shell is a first high-k dielectric shell. In such an embodiment, the device further includes a second isolation feature and a second gate isolation fin disposed above the second isolation feature. One of the first metal gate and the first source / drain feature is disposed between the first gate isolation fin and the second gate isolation fin. The second gate isolation fin has a first portion adjacent to the first source / drain feature and a second portion adjacent to the first metal gate. The first portion is different from the second portion. The first portion has a second upper dielectric feature and a second lower dielectric feature. The second upper dielectric feature has a second low-k dielectric core surrounded by a second high-k dielectric shell. In some embodiments, the device further includes a source / drain contact for one of the first source / drain features and one of the second source / drain features. In such an embodiment, a second low-k dielectric core of a second upper dielectric feature of the second gate isolation fin surrounds a first bottom portion of the source / drain contact, and the second bottom portion of the source / drain contact surrounds a first upper dielectric feature of the first gate isolation fin.

[0075] An exemplary method includes forming an isolation feature in a lower portion of a trench and forming a gate isolation fin on top of the isolation feature. The gate isolation fin is formed in an upper portion of the trench and has an upper dielectric feature and a lower dielectric feature. The upper dielectric feature has a dielectric core having a first dielectric constant, and the dielectric core is surrounded by a dielectric shell having a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The method further includes forming a first multi-gate device having a first channel layer, a first metal gate, and a first source / drain feature. The first channel layer is disposed between the first source / drain feature, and the first metal gate surrounds the first channel layer. The method further includes forming a second multi-gate device having a second channel layer, a second metal gate, and a second source / drain feature. The second channel layer is disposed between the second source / drain feature, and the second metal gate surrounds the second channel layer. The gate isolation fin is disposed between the first metal gate of the first multi-gate device and the second metal gate of the second multi-gate device, and separates the first metal gate and the second metal gate.

[0076] In some embodiments, forming the gate isolation fin includes: forming the lower dielectric feature in the bottom portion of the upper portion of the trench; depositing a first dielectric layer having the second dielectric constant along the bottom and sidewalls of the top portion of the upper portion of the trench; and depositing a second dielectric layer having the first dielectric constant over the first dielectric layer. The second dielectric layer fills the remaining portion of the top portion of the upper portion of the trench. In such embodiments, forming the gate isolation fin further includes etching back the second dielectric layer to form a recess having sidewalls formed by the first dielectric layer and a bottom formed by the second dielectric layer; and forming a third dielectric layer having the second dielectric constant in the recess. In some embodiments, forming the gate isolation fin further includes performing a planarization process on the second dielectric layer and the first dielectric layer before etching back the second dielectric layer. In some embodiments, forming the third dielectric layer includes depositing the third dielectric layer over the first dielectric layer and the second dielectric layer, and performing a planarization process on the third dielectric layer.

[0077] This disclosure outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure.

[0078] Example 1. An integrated circuit device, comprising: a first multi-gate device having: a first channel layer disposed between first source / drain features, and a first metal gate surrounding the first channel layer; a second multi-gate device having: a second channel layer disposed between second source / drain features, and a second metal gate surrounding the second channel layer; and a gate isolation fin disposed between the first metal gate and the second metal gate and separating the first metal gate and the second metal gate, wherein the gate isolation fin includes a dielectric feature having: a first dielectric layer having a first dielectric constant, and a second dielectric layer surrounding the first dielectric layer, wherein the second dielectric layer has a second dielectric constant greater than the first dielectric constant.

[0079] Example 2. The device according to Example 1, wherein the dielectric feature is a first dielectric feature, and the gate isolation fin further includes a second dielectric feature, wherein the first dielectric feature is disposed on the second dielectric feature, and the second dielectric feature has: a third dielectric layer having a third dielectric constant, and a fourth dielectric layer surrounding the third dielectric layer, wherein the fourth dielectric layer has a fourth dielectric constant less than the second dielectric constant.

[0080] Example 3. The device according to Example 2, wherein the first dielectric constant is the same as the fourth dielectric constant, and the third dielectric constant is different from the first dielectric constant and the second dielectric constant.

[0081] Example 4. The device according to Example 3, wherein the third dielectric constant is less than the first dielectric constant and the second dielectric constant.

[0082] Example 5. The device according to Example 1, wherein the second dielectric layer has a first thickness along the bottom of the first dielectric layer, a second thickness along the sidewall of the first dielectric layer, and a third thickness along the top of the first dielectric layer, wherein the third thickness is greater than the first thickness and the second thickness.

[0083] Example 6. The device according to Example 5, wherein the second thickness along the sidewall of the first dielectric layer is less than the first thickness along the bottom of the first dielectric layer.

[0084] Example 7. The device according to Example 1 further includes source / drain contacts for the first source / drain feature and the second source / drain feature, wherein the source / drain contacts are in contact with the dielectric feature entity of the gate isolation fin.

[0085] Example 8. The device according to Example 1, wherein the gate isolation fin is a first gate isolation fin disposed along a first sidewall of the first metal gate, the device further comprising a second gate isolation fin, wherein the second gate isolation fin is different from the first gate isolation fin, and the second gate isolation fin is disposed along a second sidewall of the first metal gate.

[0086] Example 9. The device according to Example 1, wherein the gate isolation fin is further disposed between and separating the first source / drain feature and the second source / drain feature, and wherein the gate isolation fin has a first height between the first source / drain feature and the second source / drain feature, and a second height between the first metal gate and the second metal gate, wherein the first height is less than the second height.

[0087] Example 10. The device according to Example 9, wherein: a second dielectric layer of the dielectric feature surrounds a first dielectric layer of the dielectric feature between the first metal gate and the second metal gate; and the second dielectric layer of the dielectric feature surrounds the first dielectric layer of the dielectric feature between the first source / drain feature and the second source / drain feature.

[0088] Example 11. An integrated circuit device comprising: an isolation feature disposed on a substrate, wherein the isolation feature is disposed between a first fin portion and a second fin portion extending from the substrate; a gate isolation fin disposed on the isolation feature, wherein the gate isolation fin includes an upper dielectric feature and a lower dielectric feature, wherein the upper dielectric feature has a low-k dielectric core surrounded by a high-k dielectric shell; a first multi-gate device having a first channel layer disposed on the first fin portion, a first metal gate surrounding the first channel layer, and a first source / drain feature, wherein the first metal gate is disposed between the first channel layer and the first fin portion; and a second multi-gate device having a second channel layer disposed on the second fin portion, a second metal gate surrounding the second channel layer, and a second source / drain feature, wherein the second metal gate is disposed between the second channel layer and the second fin portion, and wherein the gate isolation fin separates the first metal gate of the first multi-gate device from the second metal gate of the second multi-gate device.

[0089] Example 12. The device according to Example 11, wherein the lower dielectric feature has a low-k dielectric layer surrounding the oxide core.

[0090] Example 13. The device according to Example 11, wherein the high-k dielectric housing includes a high-k dielectric liner and a high-k cap layer, wherein the high-k cap layer is disposed between sidewall portions of the high-k dielectric liner.

[0091] Example 14. The device according to Example 11, wherein the isolation feature is a first isolation feature, the gate isolation fin is a first gate isolation fin, the lower dielectric feature is a first lower dielectric feature, the upper dielectric feature is a first upper dielectric feature, the low-k dielectric core is a first low-k dielectric core, and the high-k dielectric shell is a first high-k dielectric shell, and the device further includes: a second isolation feature and a second gate isolation fin disposed on the second isolation feature, wherein: one of the first metal gate and the first source / drain feature is disposed between the first gate isolation fin and the second gate isolation fin; the second gate isolation fin has a first portion adjacent to the first source / drain feature and a second portion adjacent to the first metal gate, wherein the first portion is different from the second portion; and the first portion has a second upper dielectric feature and a second lower dielectric feature, wherein the second upper dielectric feature has a second low-k dielectric core surrounded by a second high-k dielectric shell.

[0092] Example 15. The device according to Example 14 further includes a source / drain contact for one of the first source / drain features and one of the second source / drain features, wherein: a second low-k dielectric core of the second upper dielectric feature of the second gate isolation fin surrounds a first bottom portion of the source / drain contact; and the second bottom portion of the source / drain contact surrounds the first upper dielectric feature of the first gate isolation fin.

[0093] Example 16. The device according to Example 11, wherein the upper dielectric feature has a first height between the first metal gate and the second metal gate, and a second height between the first source / drain feature and the second source / drain feature.

[0094] Example 17. A method of manufacturing an integrated circuit device, comprising: forming an isolation feature in a lower portion of a trench; forming a gate isolation fin over the isolation feature, wherein the gate isolation fin is formed in an upper portion of the trench and the gate isolation fin has an upper dielectric feature and a lower dielectric feature, wherein the upper dielectric feature has a dielectric core having a first dielectric constant, the dielectric core being surrounded by a dielectric shell having a second dielectric constant, wherein the second dielectric constant is greater than the first dielectric constant; forming a first channel layer, a first metal gate, and a first source / drain feature. A multi-gate device, wherein a first channel layer is disposed between first source / drain features and a first metal gate surrounds the first channel layer; and a second multi-gate device having a second channel layer, a second metal gate, and a second source / drain feature, wherein the second channel layer is disposed between the second source / drain features and the second metal gate surrounds the second channel layer, and wherein the gate isolation fin is disposed between the first metal gate of the first multi-gate device and the second metal gate of the second multi-gate device, and separates the first metal gate and the second metal gate.

[0095] Example 18. The method according to Example 17, wherein forming the gate isolation fin includes: forming the lower dielectric feature in the bottom portion of the upper portion of the trench; depositing a first dielectric layer having the second dielectric constant along the bottom and sidewalls of the top portion of the upper portion of the trench; depositing a second dielectric layer having the first dielectric constant over the first dielectric layer, wherein the second dielectric layer fills the remaining portion of the top portion of the upper portion of the trench; etching back the second dielectric layer to form a recess having sidewalls formed by the first dielectric layer and a bottom formed by the second dielectric layer; and forming a third dielectric layer having the second dielectric constant in the recess.

[0096] Example 19. The method according to Example 18, wherein forming the gate isolation fin further includes performing a planarization process on the second dielectric layer and the first dielectric layer before etching back the second dielectric layer.

[0097] Example 20. The method according to Example 18, wherein forming the third dielectric layer includes: depositing the third dielectric layer over the first dielectric layer and the second dielectric layer, and performing a planarization process on the third dielectric layer.

Claims

1. An integrated circuit device, comprising: The first multi-gate device has: The first channel layer is positioned between the first source / drain characteristics, and A first metal gate surrounds the first channel layer; The second multi-gate device has: The second channel layer is positioned between the second source / drain characteristics, and A second metal gate surrounds the second channel layer; as well as A gate isolation fin is disposed between the first metal gate and the second metal gate and separates the first metal gate and the second metal gate. The gate isolation fin includes a first dielectric feature and a second dielectric feature, the first dielectric feature being disposed on top of the second dielectric feature. The first dielectric feature has the following characteristics: A first dielectric layer having a first dielectric constant, and A second dielectric layer surrounds the first dielectric layer, wherein the second dielectric layer has a second dielectric constant greater than the first dielectric constant; The second dielectric characteristic has: The third dielectric layer has a third dielectric constant, and A fourth dielectric layer surrounds the third dielectric layer, wherein the fourth dielectric layer has a fourth dielectric constant that is less than the second dielectric constant.

2. The device according to claim 1, wherein, The first dielectric constant is the same as the fourth dielectric constant, and the third dielectric constant is different from the first dielectric constant and the second dielectric constant.

3. The device according to claim 2, wherein, The third dielectric constant is less than the first dielectric constant and the second dielectric constant.

4. The device according to claim 1, wherein, The second dielectric layer has a first thickness along the bottom of the first dielectric layer, a second thickness along the sidewall of the first dielectric layer, and a third thickness along the top of the first dielectric layer, wherein the third thickness is greater than the first thickness and the second thickness.

5. The device according to claim 4, wherein, The second thickness along the sidewall of the first dielectric layer is less than the first thickness along the bottom of the first dielectric layer.

6. The device of claim 1, further comprising source / drain contacts for the first source / drain feature and the second source / drain feature, wherein, The source / drain contact is in contact with the first dielectric feature of the gate isolation fin.

7. The device according to claim 1, wherein, The gate isolation fin is a first gate isolation fin disposed along a first sidewall of the first metal gate. The device also includes a second gate isolation fin, wherein the second gate isolation fin is different from the first gate isolation fin, and the second gate isolation fin is disposed along a second sidewall of the first metal gate.

8. The device according to claim 1, wherein, The gate isolation fin is further disposed between the first source / drain feature and the second source / drain feature and separates the first source / drain feature and the second source / drain feature, wherein the gate isolation fin has a first height between the first source / drain feature and the second source / drain feature and a second height between the first metal gate and the second metal gate, wherein the first height is smaller than the second height.

9. The device according to claim 8, wherein: A second dielectric layer of the first dielectric feature surrounds the first dielectric layer of the first dielectric feature between the first metal gate and the second metal gate; and The second dielectric layer of the first dielectric feature surrounds the first dielectric layer of the first dielectric feature between the first source / drain feature and the second source / drain feature.

10. An integrated circuit device, comprising: An isolation feature is disposed on a substrate, wherein the isolation feature is disposed between a first fin portion and a second fin portion extending from the substrate; A gate isolation fin is disposed on the isolation feature, wherein the gate isolation fin includes an upper dielectric feature and a lower dielectric feature, wherein the upper dielectric feature has a low-k dielectric core surrounded by a high-k dielectric shell; A first multi-gate device has a first channel layer disposed on a first fin portion, a first metal gate surrounding the first channel layer, and a first source / drain feature, wherein the first metal gate is disposed between the first channel layer and the first fin portion; and The second multi-gate device has a second channel layer disposed on the second fin portion, a second metal gate surrounding the second channel layer, and a second source / drain feature, wherein the second metal gate is disposed between the second channel layer and the second fin portion, and wherein the gate isolation fin separates the first metal gate of the first multi-gate device from the second metal gate of the second multi-gate device.

11. The device according to claim 10, wherein, The lower dielectric feature has a low-k dielectric layer surrounding the oxide core.

12. The device according to claim 10, wherein, The high-k dielectric housing includes a high-k dielectric liner and a high-k cap layer, wherein the high-k cap layer is disposed between the sidewall portions of the high-k dielectric liner.

13. The device according to claim 10, wherein, The isolation feature is a first isolation feature, the gate isolation fin is a first gate isolation fin, the lower dielectric feature is a first lower dielectric feature, the upper dielectric feature is a first upper dielectric feature, the low-k dielectric core is a first low-k dielectric core, and the high-k dielectric shell is a first high-k dielectric shell. The device also includes: A second isolation feature and a second gate isolation fin disposed on the second isolation feature, wherein: One of the source / drain features of the first metal gate and the first source / drain feature is disposed between the first gate isolation fin and the second gate isolation fin; The second gate isolation fin has a first portion adjacent to one of the first source / drain features and a second portion adjacent to the first metal gate, wherein the first portion is different from the second portion; and The first portion has a second upper dielectric feature and a second lower dielectric feature, wherein the second upper dielectric feature has a second low-k dielectric core surrounded by a second high-k dielectric shell.

14. The device of claim 13, further comprising a source / drain contact for one of the first source / drain features and one of the second source / drain features, wherein: The second low-k dielectric core of the second upper dielectric feature of the second gate isolation fin surrounds the first bottom portion of the source / drain contact; and The second bottom portion of the source / drain contact surrounds the first upper dielectric feature of the first gate isolation fin.

15. The device according to claim 10, wherein, The upper dielectric feature has a first height between the first metal gate and the second metal gate, and a second height between the first source / drain feature and the second source / drain feature.

16. A method for manufacturing an integrated circuit device, comprising: Isolation features are formed in the lower part of the trench; A gate isolation fin is formed on the isolation feature, wherein the gate isolation fin is formed in the upper portion of the trench, and the gate isolation fin has an upper dielectric feature and a lower dielectric feature, wherein the upper dielectric feature has a dielectric core having a first dielectric constant, and the dielectric core is surrounded by a dielectric shell having a second dielectric constant, wherein the second dielectric constant is greater than the first dielectric constant; A first multi-gate device is formed having a first channel layer, a first metal gate, and first source / drain features, wherein the first channel layer is disposed between the first source / drain features, and the first metal gate surrounds the first channel layer; and A second multi-gate device is formed having a second channel layer, a second metal gate, and a second source / drain feature, wherein the second channel layer is disposed between the second source / drain features, and the second metal gate surrounds the second channel layer, and wherein the gate isolation fin is disposed between the first metal gate of the first multi-gate device and the second metal gate of the second multi-gate device, and separates the first metal gate and the second metal gate.

17. The method according to claim 16, wherein, Forming the gate isolation fin includes: The lower dielectric feature is formed in the bottom portion of the upper portion of the trench; A first dielectric layer having the second dielectric constant is deposited along the bottom and sidewalls of the top portion of the upper portion of the trench; A second dielectric layer having the first dielectric constant is deposited on top of the first dielectric layer, wherein the second dielectric layer fills the remaining portion of the top portion of the upper portion of the trench; Etching back the second dielectric layer to form a recess, the recess having sidewalls formed by the first dielectric layer and a bottom formed by the second dielectric layer; and A third dielectric layer having the second dielectric constant is formed in the recess.

18. The method according to claim 17, wherein, Forming the gate isolation fin further includes performing a planarization process on the second dielectric layer and the first dielectric layer before etching back the second dielectric layer.

19. The method of claim 17, wherein, Forming the third dielectric layer includes depositing the third dielectric layer on top of the first dielectric layer and the second dielectric layer, and performing a planarization process on the third dielectric layer.

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