A charge pump circuit with low current variation and mismatch over a wide dynamic range

Abstract

The application discloses a charge pump circuit with low current variation and mismatch in a wide dynamic range, which is composed of a reference current source module, a low-dropout current mirror module, a charge-discharge matching module and a switch control module. The reference current source module adopts a self-starting common-source and common-gate reference current source structure independent of a power supply voltage, and generates a reference current not affected by power supply voltage fluctuation. The low-dropout current mirror module includes two reference branches, can accurately copy the reference current in a wide output voltage range, and keeps the current flat, thereby reducing the variation rate of the matching current. The charge-discharge matching module adopts a source switch type charge pump with an operational amplifier negative feedback, can realize accurate matching of charge-discharge currents, and reduces the mismatch rate of the currents. The switch control module is controlled by the output voltage of the charge pump, and feeds back the working of the low-dropout current mirror module. When the TSMC 0.18um process is adopted and the power supply voltage is 1.8V, the output voltage range of the charge pump is 0.01V-1.79V, and the current mismatch rate is less than 0.15%.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a charge pump circuit with low current variation and mismatch in a wide dynamic range. BACKGROUND

[0002] In recent years, with the development of integrated circuit technology, phase-locked loops (PLL) have been widely used in various communication scenarios, such as FM demodulators, signal reconstruction, clock signal recovery, and frequency synthesis. A phase-locked loop can be essentially regarded as a system that automatically adjusts the frequency and phase of an input signal with a negative feedback loop. For a given input reference signal, the phase-locked loop can capture its frequency and phase through the loop, and also achieve signal frequency multiplication and synthesis. Charge pump (CP) is a key element of the phase-locked loop, often used with phase frequency detector (PFD) and loop filter (LP). The input reference signal passes through the phase frequency detector to generate a level pulse, and then the level pulse signal controls the charge pump to charge and discharge the loop filter.

[0003] Ideally, when the phase-locked loop is in a stable state, the charge and discharge currents of the charge pump should be equal, that is, the charge pump does not inject or extract charges to the loop filter, and the voltage on the loop filter should remain constant. However, due to the influence of non-ideal characteristics such as charge injection, clock feedthrough, and charge sharing, the charge pump will have the phenomenon of mismatched charge and discharge currents and matched current variation. In addition, the above non-ideal characteristics will also cause the output end of the charge pump to produce jitter, which will be modulated to the output end of the voltage-controlled oscillator (VCO) in the subsequent circuit of the phase-locked loop, and will worsen the phase noise of the voltage-controlled oscillator. Charge pump current mismatch will affect the spurious performance and static phase offset of the entire phase-locked loop system, and matched current variation will affect the loop bandwidth and loop stability of the phase-locked loop, and the output voltage range will directly affect the frequency regulation range of the voltage-controlled oscillator. Therefore, it is of great importance to improve the performance of the phase-locked loop by increasing the output voltage range of the charge pump while reducing the current mismatch and variation thereof.

[0004] In the prior art, there are two methods to reduce the non-ideal characteristics of the charge pump: one is to increase the output impedance of the current mirror, which can reduce the current mismatch rate of the charge pump, but also easily reduces the output voltage margin of the charge pump and reduces the output voltage range of the charge pump; the second is to design a dynamic current compensation loop, which can match the charging and discharging currents in a wide voltage output range, but since the current change is nonlinear, the compensation loop has the problems of difficult design and complex structure, and the current mismatch and matching current change may be worsened under different process angles. SUMMARY

[0005] The present application solves the problems of the prior art method for reducing the non-ideal characteristics of the charge pump, and provides a charge pump circuit with low current variation and mismatch in a wide dynamic range, which realizes the matching and flattening of the current in a wide dynamic voltage output range and can be directly applied to a phase-locked loop circuit.

[0006] To solve the above problems, the present application is implemented by the following technical solutions:

[0007] A charge pump circuit with low current variation and mismatch in a wide dynamic range, which is composed of a reference current source module, a low-dropout current mirror module, a charging and discharging matching module, and a switch control module; the output end of the reference current source module is connected to the input end of the low-dropout current mirror module, the output end of the low-dropout current mirror module is connected to the input end of the charging and discharging matching module, and the output end of the charging and discharging matching module is connected to the input end of the switch control module; the control output end of the switch control module is connected to the control end of the low-dropout current mirror module and the charging and discharging matching module; the charging and discharging matching module inputs external charging and discharging signals, and outputs a charge pump signal to the outside; the reference current source module adopts a self-starting common-source and common-gate reference current source structure independent of the power supply voltage, to generate a reference current not affected by the power supply voltage fluctuation; the low-dropout current mirror module is biased by the reference current source module to generate a mirror current for the charging and discharging matching module; the charging and discharging matching module adopts a source switch type charge pump with operational amplifier negative feedback to realize accurate matching of the charging and discharging currents; the switch control module is controlled by the output voltage of the charge pump to feedback control different reference branches in the low-dropout current mirror module.

[0008] In the above scheme, the reference current source module comprises MOS transistors M15-M26, and resistors R1 and R2; the sources of MOS transistors M15, M17, M18 and M23 are connected to the power supply VDD; the gates of MOS transistors M15, M17 and M18, and the drain of MOS transistor M19 are connected to the upper end of resistor R1; the drain of MOS transistor M17 is connected to the source of MOS transistor M19; the drain of MOS transistor M18 is connected to the source of MOS transistor M20; the gates of MOS transistors M20 and M19, and the drain of MOS transistor M21 are connected to the lower end of resistor R1; the gates of MOS transistors M16 and M22, and the source of MOS transistor M21 are connected to the upper end of resistor R2; the sources of MOS transistors M16, M22 and M26, and the lower end of resistor R2 are connected to the ground terminal GND; the gate of MOS transistor M21, the drains of MOS transistors M20 and M22, and the source of MOS transistor M24 are connected; the gate and drain of MOS transistor M24, the gate and drain of MOS transistor M23, and the gate and drain of MOS transistor M25 are connected; the source of MOS transistor M25 is connected to the gate and drain of MOS transistor M26; the drain of MOS transistor M16 forms the first output end of the reference current source module, and is connected to the first input end of the low-drop current mirror module; the drain of MOS transistor M15 forms the second output end of the reference current source module, and is connected to the second input end of the low-drop current mirror module.

[0009] In the above scheme, the low-dropout current mirror module comprises MOS tubes M5-M10, M13 and M14, transmission gates TG2-TG4 and TG6-TG8, and a rail-to-rail operational amplifier OP2; the source of MOS tube M6 and MOS tube M13, and the gate of MOS tube M8, MOS tube M9 and MOS tube M14 are connected with the power supply VDD; the drain of MOS tube M13 forms the first input end of the low-dropout current mirror module, and is connected with the first output end of the reference current source module; the drain of MOS tube M13 is connected with the non-inverting input end of the rail-to-rail operational amplifier OP2 through transmission gate TG3 at the same time; the drain of MOS tube M6, the source and drain of MOS tube M9, and the source of MOS tube M5 are connected; the drain of MOS tube M6 is connected with the inverting input end of the rail-to-rail operational amplifier OP2 through transmission gate TG4; the output end of the rail-to-rail operational amplifier OP2 is connected with the gate of MOS tube M5 through transmission gate TG2; the source of MOS tube M14 and MOS tube M8, and the gate of MOS tube M6, MOS tube M10 and MOS tube M13 are connected with the ground terminal GND; the drain of MOS tube M14 forms the second input end of the low-dropout current mirror module, and is connected with the second output end of the reference current source module; the drain of MOS tube M14 is connected with the non-inverting input end of the rail-to-rail operational amplifier OP2 through transmission gate TG7 at the same time; the drain of MOS tube M8, the source and drain of MOS tube M10, and the source of MOS tube M7 are connected; the drain of MOS tube M8 is connected with the inverting input end of the rail-to-rail operational amplifier OP2 through transmission gate TG8; the output end of the rail-to-rail operational amplifier OP2 is connected with the gate of MOS tube M7 through transmission gate TG6; the two control ends of transmission gates TG2-TG4 and TG6-TG8 form two control ends of the low-dropout current mirror module, and are connected with two control output ends of the switch control module; the gate of MOS tube M5 forms the first output end of the low-dropout current mirror module, and is connected with the first input end of the charge-discharge matching module; the gate of MOS tube M7 forms the second output end of the low-dropout current mirror module, and is connected with the second input end of the charge-discharge matching module; the drains of MOS tube M5 and M7 form the reference voltage output end of the low-dropout current mirror module, and are connected with the reference voltage input end of the charge-discharge matching module.

[0010] In the above scheme, the charge-discharge matching module comprises a rail-to-rail operational amplifier OP1, capacitors C1 and C2, transmission gates TG1 and TG5, and MOS transistors M1-M4, M11 and M12; the non-inverting input terminal of the rail-to-rail operational amplifier OP1 forms the reference voltage input terminal of the charge-discharge matching module, and is connected to the reference voltage output terminal of the low-dropout current mirror module; the source of the MOS transistor M2 and the positive terminal of the capacitor C1 are connected to the power supply VDD; the gate of the MOS transistor M2 inputs an external positive charging signal UP; the gate of the MOS transistor M11 inputs an external negative charging signal UPB; the drain of the MOS transistor M2, the source and drain of the MOS transistor M11, and the source of the MOS transistor M1 are connected; the gate of the MOS transistor M1 and the negative terminal of the capacitor C1 form the first input terminal of the charge-discharge matching module, and are connected to the first output terminal of the low-dropout current mirror module; the gate of the MOS transistor M1 is connected to the output terminal of the rail-to-rail operational amplifier OP1 through the transmission gate TG5; the source of the MOS transistor M4 and the negative terminal of the capacitor C2 are connected to the ground terminal GND; the gate of the MOS transistor M4 inputs an external positive discharging signal DN, and the gate of the MOS transistor M12 inputs an external negative discharging signal DNB; the drain of the MOS transistor M4, the source and drain of the MOS transistor M12, and the source of the MOS transistor M3 are connected; the gate of the MOS transistor M3 and the positive terminal of the capacitor C2 form the second input terminal of the charge-discharge matching module, and are connected to the second output terminal of the low-dropout current mirror module; the gate of the MOS transistor M3 is connected to the output terminal of the rail-to-rail operational amplifier OP1 through the transmission gate TG1; the two control terminals of the transmission gates TG1 and TG5 form the two control terminals of the charge-discharge matching module, and are connected to the two control output terminals of the switch control module; the inverting input terminal of the rail-to-rail operational amplifier OP1 forms the output terminal of the charge-discharge matching module, is connected to the input terminal of the switch control module, and outputs an external charge pump signal Vctrl.

[0011] The switch control module comprises MOS tubes M27-M36; the gates of MOS tubes M27-M28 and M32-M33 form the input end of the switch control module, and are connected with the output end of the charge-discharge matching module; the source of MOS tube M27, the drain of MOS tube M34 and the gate of MOS tube M35 are connected with the power supply VDD; the source of MOS tube M32 and M36, the drain of MOS tube M29 and the gate of MOS tube M30 are connected with the ground terminal GND; the drain of MOS tube M27 and the source of MOS tubes M28 and M29 are connected; the drain of MOS tube M32 and the source of MOS tubes M33 and M34 are connected; the drain of MOS tubes M28 and M33 and the gate of MOS tubes M29 and M34 are connected; the gate of MOS tubes M29 and M34, the drain of MOS tubes M35 and M30 and the gate of MOS tubes M36 and M31 are connected; the source of MOS tubes M35 and M30 are connected to form a control output end of the switch control module, and are connected with a control end of the low-voltage differential current mirror module and the charge-discharge matching module; the drain of MOS tubes M36 and M31 are connected to form another control output end of the switch control module, and are connected with another control end of the low-voltage differential current mirror module and the charge-discharge matching module.

[0012] Compared with the prior art, the present application has the following characteristics:

[0013] 1. The low-voltage differential current mirror module is adopted, the variation rate of the charge pump matching current is reduced, and the flatness of the matching current is improved.

[0014] 2. The use of the constant-transconductance high-gain input-output rail-to-rail operational amplifier reduces the mismatch rate of the charge pump current and improves the matching precision of the current.

[0015] 3. The switch control module feeds back to control different reference branches of the low-voltage differential current mirror module, so that the charge-discharge current of the charge pump is accurately matched in a wide voltage output range.

[0016] 4. The use of the dummy transistor in the charge-discharge matching module eliminates the influence of charge injection and clock feedthrough of the charge-discharge branch. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 It is a circuit schematic diagram of a charge pump circuit with low current variation and mismatch in a wide dynamic range.

[0018] Figure 2 It is a mismatch simulation diagram of the charge current and the discharge current of the charge pump of the present application.

[0019] Figure 3 It is a dynamic matching characteristic diagram of the charge pump and the frequency discriminator of the present application. DETAILED DESCRIPTION

[0020] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to specific examples.

[0021] A charge pump circuit with low current variation and mismatch over a wide dynamic range, such as Figure 1 As shown, it consists of a reference current source module, a low-voltage dropout current mirror module, a charge-discharge matching module, and a switch control module. The output of the reference current source module is connected to the input of the low-voltage dropout current mirror module, which in turn is connected to the input of the charge-discharge matching module. The output of the charge-discharge matching module is connected to the input of the switch control module. The control output of the switch control module is connected to the control terminals of the low-voltage dropout current mirror module and the charge-discharge matching module. The charge-discharge matching module inputs external charging and discharging signals, and outputs a charge pump signal to the outside.

[0022] In the present invention, the reference current source module includes MOS transistors M15 to M26 and resistors R1 and R2. MOS transistors M15, M23, and M17 to M20 are PMOS transistors, while MOS transistors M16, M21, M22, and M24 to M26 are NMOS transistors. The sources of the MOS transistors M15, M17, M18, and M23 are connected to the power supply VDD; the gates of the MOS transistors M15, M17, and M18, and the drain of the MOS transistor M19 are connected to the upper end of the resistor R1; the drain of the MOS transistor M17 is connected to the source of the MOS transistor M19; the drain of the MOS transistor M18 is connected to the source of the MOS transistor M20; the gates of the MOS transistors M20 and M19, and the drain of the MOS transistor M21 are connected to the lower end of the resistor R1; the gates of the MOS transistors M16 and M22, and the source of the MOS transistor M21 are connected to the upper end of the resistor R2; the sources of the MOS transistors M16, M22, and M26, The lower end of the resistor R2 is connected to the ground terminal GND; the gate of the MOS transistor M21, the drains of the MOS transistors M20 and M22, and the source of the MOS transistor M24 are connected; the gate and drain of the MOS transistor M24, the gate and drain of the MOS transistor M23, and the gate and drain of the MOS transistor M25 are connected; the source of the MOS transistor M25 is connected to the gate and drain of the MOS transistor M26; the drain of the MOS transistor M16 forms the first output end of the reference current source module, which is connected to the first input end of the low-voltage difference current mirror module; the drain of the MOS transistor M15 forms the second output end of the reference current source module, which is connected to the second input end of the low-voltage difference current mirror module.

[0023] The reference current source module adopts self-starting common-source and common-gate reference current source structure independent of power voltage to generate reference current not affected by power voltage fluctuation. MOS tubes M23-M26 constitute a self-starting circuit to enable the whole reference current source module to work normally. The reference current Ibias generated by the reference current source module is independent of power VDD, and Ibias is not affected by power fluctuation. The size of Ibias can be adjusted by adjusting the size of resistor R2. The drain of MOS tube M15 generates second reference current Iref2 for the NMOS reference branch of the low-dropout current mirror module. The size of Iref2 can be adjusted by adjusting the width-length ratio of MOS tube M15. The drain of MOS tube M16 generates first reference current Iref1 for the PMOS reference branch of the low-dropout current mirror module. The size of Iref1 can be adjusted by adjusting the width-length ratio of NMOS tube M16. The first reference current Iref1 and the second reference current Iref2 are of the same size.

[0024] In the application, the low-dropout current mirror module comprises MOS transistors M5-M10, M13 and M14, transmission gates TG2-TG4 and TG6-TG8, and a rail-to-rail operational amplifier OP2. The MOS transistors M13, M9, and M5-M6 are PMOS transistors, and the MOS transistors M14, M10, M7-M8 are NMOS transistors. The MOS transistors M13, M9, M5-M6, the transmission gates TG2-TG4, and the rail-to-rail operational amplifier OP2 form a PMOS reference branch. The NMOS transistors M14, M10, M7-M8, the transmission gates TG6-TG8, and the rail-to-rail operational amplifier OP2 form an NMOS reference branch. The PMOS reference branch and the NMOS reference branch share the same rail-to-rail operational amplifier OP2. The sources of the MOS transistors M6 and M13, and the gates of the MOS transistors M8, M9 and M14 are connected to a power supply VDD; the drain of the MOS transistor M13 forms a first input terminal of the low-dropout current mirror module, and is connected to a first output terminal of a reference current source module; the drain of the MOS transistor M13 is also connected to a non-inverting input terminal of the rail-to-rail operational amplifier OP2 through the transmission gate TG3; the drain of the MOS transistor M6, the source and drain of the MOS transistor M9, and the source of the MOS transistor M5 are connected; the drain of the MOS transistor M6 is connected to an inverting input terminal of the rail-to-rail operational amplifier OP2 through the transmission gate TG4; an output terminal of the rail-to-rail operational amplifier OP2 is connected to a gate of the MOS transistor M5 through the transmission gate TG2; the sources of the MOS transistors M14 and M8, and the gates of the MOS transistors M6, M10 and M13 are connected to a ground terminal GND; the drain of the MOS transistor M14 forms a second input terminal of the low-dropout current mirror module, and is connected to a second output terminal of the reference current source module; the drain of the MOS transistor M14 is also connected to the non-inverting input terminal of the rail-to-rail operational amplifier OP2 through the transmission gate TG7; the drain of the MOS transistor M8, the source and drain of the MOS transistor M10, and the source of the MOS transistor M7 are connected; the drain of the MOS transistor M8 is connected to the inverting input terminal of the rail-to-rail operational amplifier OP2 through the transmission gate TG8; the output terminal of the rail-to-rail operational amplifier OP2 is connected to a gate of the MOS transistor M7 through the transmission gate TG6; two control terminals of the transmission gates TG2-TG4 and TG6-TG8 form two control terminals of the low-dropout current mirror module, and are connected to two control output terminals of a switch control module; the gate of the MOS transistor M5 forms a first output terminal of the low-dropout current mirror module, and is connected to a first input terminal of a charge-discharge matching module; the gate of the MOS transistor M7 forms a second output terminal of the low-dropout current mirror module, and is connected to a second input terminal of the charge-discharge matching module; the drains of the MOS transistors M5 and M7 form a reference voltage output terminal of the low-dropout current mirror module, and are connected to a reference voltage input terminal of the charge-discharge matching module.

[0025] The low-dropout current mirror module is provided with current bias by the reference current source module, and generates mirror currents for the charge-discharge matching module. The low-dropout current mirror module includes two reference branches, i.e. a PMOS reference branch and an NMOS reference branch. The PMOS reference branch is used to copy the current Iref1 generated by the reference current source module to supply the charge-discharge matching module, and the NMOS reference branch is used to copy the current Iref2 generated by the reference current source module to supply the charge-discharge matching module. The low-dropout current mirror module can accurately copy the reference current in a wide output voltage range, and keep the current flat, thereby reducing the variation rate of the matching current. The "virtual short" feature of the rail-to-rail operational amplifier OP2 can make the voltage at the Va point and the voltage at the Vb point almost completely equal. The MOS transistor M13, the MOS transistor M6, the rail-to-rail operational amplifier OP2, and the transmission gates TG2-TG4 constitute a low-dropout current mirror of a PMOS reference branch. The transmission gates TG2-TG4 are also controlled by the switch control module and can be opened or closed at the same time. The use of the rail-to-rail operational amplifier OP2 can make the first mirror current I1 accurately copy the first reference current Iref1 generated by the reference current source module. The "virtual short" feature of the rail-to-rail operational amplifier OP2 can make the voltage at the Vc point and the voltage at the Vd point almost completely equal. The MOS transistor M14, the MOS transistor M8, the rail-to-rail operational amplifier OP2, and the transmission gates TG6-TG8 constitute a low-dropout current mirror of an NMOS reference branch. The transmission gates TG6-TG8 are also controlled by the switch control module and can be opened or closed at the same time. The use of the rail-to-rail operational amplifier OP2 can make the second mirror current I2 accurately copy the second reference current Iref2 generated by the reference current source module. Since the first mirror current I1 accurately copies the first reference current Iref1 generated by the reference current source module, and the second mirror current I2 accurately copies the second reference current Iref2 generated by the reference current source module, and the first reference current Iref1 and the second reference current Iref2 are of the same size, the first mirror current I1 and the second mirror current I2 are also of the same size, and the currents I1 and I2 are constant in size and have a small variation rate.

[0026] In the application, the charge-discharge matching module comprises a rail-to-rail operational amplifier OP1, capacitors C1 and C2, transmission gates TG1 and TG5, and MOS transistors M1-M4, M11 and M12. The MOS transistors M1-M2 and M11 are PMOS transistors. The MOS transistors M3-M4 and M12 are NMOS transistors. The MOS transistors M1-M2 and M11 form a charging branch. The MOS transistors M3-M4 and M12 form a discharging branch. Both the charging branch and the discharging branch adopt a common-source common-gate structure to increase the output impedance of the circuit and improve the matching degree of the charge-discharge current. The non-inverting input terminal of the rail-to-rail operational amplifier OP1 forms a reference voltage input terminal of the charge-discharge matching module, and is connected to a reference voltage output terminal of the low-dropout current mirror module. The source of the MOS transistor M2 and the positive terminal of the capacitor C1 are connected to a power supply VDD. The gate of the MOS transistor M2 inputs an external positive charging signal UP. The gate of the MOS transistor M11 inputs an external negative charging signal UPB. The drain of the MOS transistor M2, the source and drain of the MOS transistor M11, and the source of the MOS transistor M1 are connected. The gate of the MOS transistor M1 and the negative terminal of the capacitor C1 form a first input terminal of the charge-discharge matching module, and are connected to a first output terminal of the low-dropout current mirror module. The gate of the MOS transistor M1 is connected to the output terminal of the rail-to-rail operational amplifier OP1 through the transmission gate TG5. The source of the MOS transistor M4 and the negative terminal of the capacitor C2 are connected to a ground terminal GND. The gate of the MOS transistor M4 inputs an external positive discharging signal DN, and the gate of the MOS transistor M12 inputs an external negative discharging signal DNB. The drain of the MOS transistor M4, the source and drain of the MOS transistor M12, and the source of the MOS transistor M3 are connected. The gate of the MOS transistor M3 and the positive terminal of the capacitor C2 form a second input terminal of the charge-discharge matching module, and are connected to a second output terminal of the low-dropout current mirror module. The gate of the MOS transistor M3 is connected to the output terminal of the rail-to-rail operational amplifier OP1 through the transmission gate TG1. The two control terminals of the transmission gates TG1 and TG5 form two control terminals of the charge-discharge matching module, and are connected to two control output terminals of the switch control module. The inverting input terminal of the rail-to-rail operational amplifier OP1 forms an output terminal of the charge-discharge matching module, is connected to an input terminal of the switch control module, and outputs an external charge pump signal Vctrl.

[0027] The charge-discharge matching module with the source switch type charge pump with negative feedback of the operational amplifier can realize accurate matching of the charge-discharge current, and reduce the mismatch rate of the current. The rail-to-rail operational amplifier OP1 "forces" the output signal Vctrl and the reference voltage Vref to be the same, so that the charging current Iup can accurately copy the mirror current I1 copied by the PMOS reference branch in the low-dropout current mirror module, and the discharging current Idn can accurately copy the mirror current I2 copied by the NMOS reference branch in the low-dropout current mirror module.

[0028] In the application, the switch control module comprises MOS tubes M27-M36. Among them, MOS tubes M27-M31 are PMOS tubes, and MOS tubes M32-M36 are NMOS tubes. The gates of MOS tubes M27-M28 and M32-M33 form the input end of the switch control module, and are connected with the output end of the charge-discharge matching module; the source of MOS tube M27 and M31, the drain of MOS tube M34, and the gate of MOS tube M35 are connected with the power supply VDD; the source of MOS tube M32 and M36, the drain of MOS tube M29, and the gate of MOS tube M30 are connected with the ground terminal GND; the drain of MOS tube M27, and the source of MOS tube M28 and M29 are connected; the drain of MOS tube M32, and the source of MOS tube M33 and M34 are connected; the drain of MOS tube M28 and M33, and the gate of MOS tube M29 and M34 are connected; the gate of MOS tube M29 and M34, the drain of MOS tube M35 and M30, and the gate of MOS tube M36 and M31 are connected; the source of MOS tube M35 and M30 connected together form a control output end of the switch control module, and are connected with a control end of the low-voltage differential current mirror module and the charge-discharge matching module; the drain of MOS tube M36 and M31 connected together form another control output end of the switch control module, and are connected with another control end of the low-voltage differential current mirror module and the charge-discharge matching module.

[0029] The switch control module is controlled by the charge pump output voltage, and feedback controls different reference branches in the low-dropout current mirror module. The switch control module is controlled by the charge pump voltage Vctrl, and generates control signals K1 and K2. The control signals K1 and K2 can control the transmission gates TG1-TG4 in the low-dropout current mirror module and the charge-discharge matching module to be turned on and off at the same time, and can also control the transmission gates TG5-TG8 in the low-dropout current mirror module and the charge-discharge matching module to be turned on and off at the same time. The change of the voltage on the transmission line K is controlled by the output signal Vctrl voltage. When Vctrl gradually increases from the ground voltage '0' to the threshold voltage of the MOS transistor M33, the voltage at point K remains unchanged at the power supply voltage '1'. When the output signal Vctrl gradually increases from the threshold voltage of M33 to the power supply voltage '1', the voltage at point K decreases from the power supply voltage '1' to the ground voltage '0'. The width-length ratio of the MOS transistors M27-M29 and the MOS transistors M32-M34 can be adjusted to control the K signal to be '0' or '1' in different ranges of the charge pump output voltage Vctrl. The MOS transistor M35 and the MOS transistor M30 constitute an inverter, so the state of the switch control signal K1 is opposite to K. The MOS transistor M36 and the MOS transistor M31 constitute a transmission gate, so the state of the switch control signal K2 is the same as K. The two control signals K1 and K2 with opposite states can simultaneously control the transmission gates TG1-TG4 (transmission gates TG5-TG8) in the low-dropout current mirror module and the charge-discharge matching module to be turned on (cut off) and cut off (turned on) at the same time. When K1='0' and K2='1', the transmission gates TG1-TG4 are turned on, and the transmission gates TG5-TG8 are cut off, at this time the PMOS reference branch in the low-dropout current mirror module works, and the NMOS reference branch does not work. When K1='1' and K2='0', the transmission gates TG5-TG8 are turned on, and the transmission gates TG1-TG4 are cut off, at this time the NMOS reference branch in the low-dropout current mirror module works, and the PMOS reference branch does not work. This working mode can dynamically improve the matching accuracy of the charge pump current and widen the dynamic range of the output voltage of the charge pump current.

[0030] The present application adopts CMOS process, and uses the low-dropout current mirror module to reduce the variation rate of the matching current of the charge pump, and improve the flatness of the matching current. The feedback control effect of the charge pump output voltage on the switch control module selects different reference branches in the low-dropout current mirror module, and realizes accurate matching of the charge-discharge current of the charge pump in a wide voltage output range. Figure 2 The simulation diagram of the mismatch of the charge-discharge current of the charge pump is as follows: Figure 2 It can be known that when the TSMC 0.18um process is adopted and the power supply voltage is 1.8V, the output voltage range of the charge pump is 0.01V-1.79V, and the current mismatch rate is less than 0.15%. Figure 3The dynamic matching characteristic diagram of the charge pump and the phase frequency detector is obtained by simulation of the charge pump combined with the phase frequency detector. Figure 3 It can be seen that the charge pump and the phase frequency detector have good dynamic matching characteristics.

[0031] It should be noted that although the above embodiments of the present application are illustrative, they are not limiting of the present application, and therefore the present application is not limited to the above specific embodiments. Any other embodiments obtained by those skilled in the art under the inspiration of the present application without departing from the principles of the present application are considered to be within the protection scope of the present application.

Claims

1. A charge pump circuit with low current variation and mismatch over a wide dynamic range, characterized in that, The reference current source module, the low-drop current mirror module, the charge-discharge matching module and the switch control module are connected in series; the output end of the reference current source module is connected with the input end of the low-drop current mirror module, the output end of the low-drop current mirror module is connected with the input end of the charge-discharge matching module, and the output end of the charge-discharge matching module is connected with the input end of the switch control module; the control output end of the switch control module is connected with the control ends of the low-drop current mirror module and the charge-discharge matching module; the charge-discharge matching module inputs external charging signals and discharging signals, and outputs charge pump signals to the outside; the reference current source module adopts a self-starting common-source and common-gate reference current source structure independent of the power supply voltage, generates a reference current not affected by the power supply voltage fluctuation; the low-drop current mirror module is provided with current bias by the reference current source module, generates a mirror current for the charge-discharge matching module; the charge-discharge matching module adopts a source switch type charge pump with operational amplifier negative feedback to realize accurate matching of the charge-discharge current; the switch control module is controlled by the charge pump output voltage, and feedback controls different reference branches in the low-drop current mirror module. The low-dropout current mirror module comprises MOS tubes M5-M10, M13 and M14, transfer gates TG2-TG4 and TG6-TG8, and a rail-to-rail operational amplifier OP2; the source of the MOS tube M6 and the MOS tube M13 and the gate of the MOS tube M8, the MOS tube M9 and the MOS tube M14 are connected with a power supply VDD; the drain of the MOS tube M13 forms a first input end of the low-dropout current mirror module and is connected with a first output end of a reference current source module; the drain of the MOS tube M13 is connected with a non-inverting input end of the rail-to-rail operational amplifier OP2 through the transfer gate TG3; the drain of the MOS tube M6, the source and the drain of the MOS tube M9 and the source of the MOS tube M5 are connected; the drain of the MOS tube M6 is connected with an inverting input end of the rail-to-rail operational amplifier OP2 through the transfer gate TG4; the output end of the rail-to-rail operational amplifier OP2 is connected with the gate of the MOS tube M5 through the transfer gate TG2; the source of the MOS tube M14 and the MOS tube M8 and the gate of the MOS tube M6, the MOS tube M10 and the MOS tube M13 are connected with a ground terminal GND; the drain of the MOS tube M14 forms a second input end of the low-dropout current mirror module and is connected with a second output end of the reference current source module; the drain of the MOS tube M14 is connected with the non-inverting input end of the rail-to-rail operational amplifier OP2 through the transfer gate TG7; the drain of the MOS tube M8, the source and the drain of the MOS tube M10 and the source of the MOS tube M7 are connected; the drain of the MOS tube M8 is connected with the inverting input end of the rail-to-rail operational amplifier OP2 through the transfer gate TG8; the output end of the rail-to-rail operational amplifier OP2 is connected with the gate of the MOS tube M7 through the transfer gate TG6; two control ends of the transfer gates TG2-TG4 and TG6-TG8 form two control ends of the low-dropout current mirror module and are connected with two control output ends of a switch control module; the gate of the MOS tube M5 forms a first output end of the low-dropout current mirror module and is connected with a first input end of a charge-discharge matching module; the gate of the MOS tube M7 forms a second output end of the low-dropout current mirror module and is connected with a second input end of the charge-discharge matching module; the drains of the MOS tubes M5 and M7 form a reference voltage output end of the low-dropout current mirror module and are connected with a reference voltage input end of the charge-discharge matching module.

2. A charge pump circuit with low current variation and mismatch in wide dynamic range according to claim 1, characterized in that, The reference current source module comprises MOS tubes M15-M26 and resistors R1 and R2. The sources of the MOS transistors M15, M17, M18, and M23 are connected to the power supply VDD; the gates of the MOS transistors M15, M17, and M18, and the drain of the MOS transistor M19 are connected to the upper end of the resistor R1; the drain of the MOS transistor M17 is connected to the source of the MOS transistor M19; the drain of the MOS transistor M18 is connected to the source of the MOS transistor M20; the gates of the MOS transistors M20 and M19, and the drain of the MOS transistor M21 are connected to the lower end of the resistor R1; the gates of the MOS transistors M16 and M22, and the source of the MOS transistor M21 are connected to the upper end of the resistor R2; the sources of the MOS transistors M16, M22, and M26, The lower end of the resistor R2 is connected to the ground terminal GND; the gate of the MOS transistor M21, the drains of the MOS transistors M20 and M22, and the source of the MOS transistor M24 are connected; the gate and drain of the MOS transistor M24, the gate and drain of the MOS transistor M23, and the gate and drain of the MOS transistor M25 are connected; the source of the MOS transistor M25 is connected to the gate and drain of the MOS transistor M26; the drain of the MOS transistor M16 forms the first output end of the reference current source module, which is connected to the first input end of the low-voltage difference current mirror module; the drain of the MOS transistor M15 forms the second output end of the reference current source module, which is connected to the second input end of the low-voltage difference current mirror module.

3. A charge pump circuit with low current variation and mismatch in wide dynamic range according to claim 1, characterized in that, The charge and discharge matching module includes a rail-to-rail operational amplifier OP1, capacitors C1 and C2, transmission gates TG1 and TG5, and MOS transistors M1 to M4, M11, and M12; The positive input end of the rail-to-rail operational amplifier OP1 forms a reference voltage input end of the charge-discharge matching module, and connects a reference voltage output end of the low-dropout current mirror module; the source of the MOS transistor M2 and the positive end of the capacitor C1 are connected with a power supply VDD; the gate of the MOS transistor M2 inputs an external positive charging signal UP; the gate of the MOS transistor M11 inputs an external negative charging signal UPB; the drain of the MOS transistor M2, the source and the drain of the MOS transistor M11, and the source of the MOS transistor M1 are connected; the gate of the MOS transistor M1 and the negative end of the capacitor C1 form a first input end of the charge-discharge matching module, and connect a first output end of the low-dropout current mirror module; the gate of the MOS transistor M1 is connected with the output end of the rail-to-rail operational amplifier OP1 through the transmission gate TG5; the source of the MOS transistor M4 and the negative end of the capacitor C2 are connected with a ground terminal GND; the gate of the MOS transistor M4 inputs an external positive discharging signal DN, and the gate of the MOS transistor M12 inputs an external negative discharging signal DNB; the drain of the MOS transistor M4, the source and the drain of the MOS transistor M12, and the source of the MOS transistor M3 are connected; the gate of the MOS transistor M3 and the positive end of the capacitor C2 form a second input end of the charge-discharge matching module, and connect a second output end of the low-dropout current mirror module; the gate of the MOS transistor M3 is connected with the output end of the rail-to-rail operational amplifier OP1 through the transmission gate TG1; the two control ends of the transmission gates TG1 and TG5 form two control ends of the charge-discharge matching module, and connect two control output ends of the switch control module; the inverting end of the rail-to-rail operational amplifier OP1 forms an output end of the charge-discharge matching module, connects an input end of the switch control module, and outputs an external charge pump signal Vctrl.

4. A charge pump circuit with low current variation and mismatch in wide dynamic range according to claim 1, characterized in that, The switch control module comprises MOS transistors M27-M36; The gates of the MOS transistors M27-M28 and M32-M33 form an input end of the switch control module, and connect an output end of the charge-discharge matching module; the source of the MOS transistors M27 and M31, the drain of the MOS transistor M34, and the gate of the MOS transistor M35 are connected with the power supply VDD; the source of the MOS transistor M32 and M36, the drain of the MOS transistor M29, and the gate of the MOS transistor M30 are connected with the ground terminal GND; the drain of the MOS transistor M27, and the sources of the MOS transistors M28 and M29 are connected; the drain of the MOS transistor M32, and the sources of the MOS transistors M33 and M34 are connected; the drains of the MOS transistors M28 and M33, and the gates of the MOS transistors M29 and M34 are connected; the gates of the MOS transistors M29 and M34, the drains of the MOS transistors M35 and M30, and the gates of the MOS transistors M36 and M31 are connected; the sources of the MOS transistors M35 and M30 are connected to form a control output end of the switch control module, and connect a control end of the low-dropout current mirror module and the charge-discharge matching module; the drains of the MOS transistors M36 and M31 are connected to form another control output end of the switch control module, and connect another control end of the low-dropout current mirror module and the charge-discharge matching module.

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