A universal analog-to-digital converter testing device

Abstract

The application provides a universal analog-digital converter testing device, which comprises at least an analog-digital converter testing module, a plurality of testing interface boards, a testing mainboard, an external power supply, a signal generator and a logic analyzer, the analog-digital converter testing module is sequentially connected to the testing interface boards and the testing mainboard, the external power supply, the signal generator and the logic analyzer are connected to each other and to the analog-digital converter testing module. The testing device can be modularly and independently operated, has strong expandability, can realize different functions in a simple form of building blocks, each component can be operated independently, and can be spliced when needed. The more the spliced module components are, the stronger the realized functions are. The testing device has simple operation and good maintainability, and can well solve the testing problem of analog-digital converters in practice.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of chip testing, and particularly relates to a universal analog-to-digital converter testing device. BACKGROUND

[0002] In order to adapt to the evaluation of various types of analog-to-digital converters (ADCs), such as Flash, SAR, Pipeline, Sigma Delta, etc., a general integrated automatic testing system (ATE) testing machine is generally used in the traditional testing method. Such a machine mainly aims at wafer testing, such as Teradyne, UltraFlex, Advantest, Agilent, etc. Although the architecture is universal and the hardware is unified, the performance test is difficult to truly reflect the performance of the IP for high-precision high-speed ADC testing. Because the hardware of the universal machine is unified, in order to cover the test items, the test condition coverage range of the hardware is required to be wide, and the cost is very high. However, in some low-voltage, high-precision and high-speed tests, the parasitic parameters of the universal test channel will affect the performance index. If high-level probes and hardware configurations are used, the cost is very high. In the face of differentiated ADC testing, a scalable customized testing platform is becoming more and more important in various types of IP testing.

[0003] Another universal testing scheme is a dedicated package testing system, such as the National Instruments NILabview in the United States, which provides a complete solution, such as a DUT test board, a dedicated signal excitation source, a signal acquisition and processing unit.

[0004] Another evaluation scheme is a dedicated ADC evaluation system of international manufacturers such as ADI and TI, which has a relatively systematic software and hardware evaluation scheme, mainly for demonstrating the functions and performance of packaged user products. These customized product demonstration systems have undergone optimal single-board circuit design. According to the division, these product companies divide the ADC testing into low-speed and high-speed two levels. The low-speed interface is generally a CMOS serial or parallel interface, and the interface rate is lower than 200MHz. The high-speed interface is generally an LVDS, JESD204B / C Transceiver interface, and the rate has reached 12.5Gbps. Therefore, a flexible and convenient testing scheme that takes into account high-speed and low-speed ADC testing is very important for ADC IP testing, that is, the hardware configuration is unified, and the maintenance is very convenient.

[0005] In summary, in order to perform final product evaluation, especially for mixed-signal IPs such as ADC, package-level testing or application-level testing of final products is generally used, because such a scheme takes into account the influence of actual product packaging, and the performance of final testing is closer to the performance in real environment, therefore, how to design a customized scalable testing platform, which can integrate mainstream product evaluation methods, high-precision instruments and meters, and automated testing, is very needed in actual work. SUMMARY

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide a general-purpose analog-to-digital converter testing device, which can meet the requirements of modular design, can integrate required testing instruments and meters, and can integrate third-party evaluation systems, so as to enhance or expand the evaluation capabilities of analog-to-digital converter IPs of different processes.

[0007] To achieve the above-mentioned purpose and other related purposes, the present application provides a general-purpose analog-to-digital converter testing device, which at least comprises: an analog-to-digital converter testing module, a plurality of testing interface boards, a testing mainboard, an external power supply, a signal generator, and a logic analyzer, the analog-to-digital converter testing module is connected to the testing interface boards and the testing mainboard in sequence, the external power supply, the signal generator, and the logic analyzer are connected to each other and are connected to the analog-to-digital converter testing module.

[0008] Preferably, the analog-to-digital converter testing module comprises a signal conditioning unit, a sine wave generator unit, an analog-to-digital converter, a multiplexing unit, a power management unit, a high-speed connection seat unit, a module code and standard sample unit, the signal conditioning unit is connected to the signal generator and the sine wave generator unit, for conditioning the signal output by the signal generator or the sine wave generator unit, and outputting the signal to the analog-to-digital converter; the multiplexing unit is connected to the external power supply, the signal conditioning unit, the analog-to-digital converter, the power management unit, and the high-speed connection seat unit; the power management unit is connected to a 5V power adapter; the analog-to-digital converter is connected to an FPGA / logic analyzer interface and an FPGA / third-party evaluation board interface through the high-speed connection seat unit; the module code is connected to the analog-to-digital converter and the high-speed connection seat unit.

[0009] Preferably, a bridge resistor is further connected between the high-speed connection seat unit and the analog-to-digital converter.

[0010] Preferably, the analog-to-digital converter comprises a source input, a reference power supply, an IP power supply, a control input, a digital output and a coding pin; the source input is connected with the signal conditioning unit, the reference power supply and the IP power supply are connected with the multiplexing unit, the control input and the digital output unit are connected with the high-speed connector unit, and the coding pin is connected with the module coding.

[0011] Preferably, the analog-to-digital converter is one of a Flash analog-to-digital converter, a SAR analog-to-digital converter, a Pipeline analog-to-digital converter and a Sigma Delta analog-to-digital converter.

[0012] Preferably, the external power supply is an external power supply of an instrument and / or a precision voltage source.

[0013] Preferably, the test device further comprises a main control computer connected with the test mainboard, the analog-to-digital converter test module, the external power supply and the signal generator, and the main control computer is further connected to a network server and a data processing server.

[0014] Preferably, the test device further comprises a high-low temperature control box connected with the main control computer, the analog-to-digital converter test module and the test interface board.

[0015] As described above, the universal analog-to-digital converter test device of the present application has the following beneficial effects:

[0016] The test device provided by the present application can be modularly and independently operated, has strong expandability, and can realize different functions only by being simply stacked in the form of building blocks. Before establishing the entire system, each component can be operated independently, and can be spliced when needed. The more the spliced module components are, the stronger the realized functions are. In order to adapt to the test and evaluation of analog-to-digital converters of various different processes, different types and different working conditions as much as possible, and to fully utilize the resources of advanced instrument equipment in the existing laboratory, a complex and comprehensive system is not designed. The purpose is to simplify the design of the analog-to-digital converter module to improve the system performance of the analog-to-digital converter, integrate other resources, and quickly establish the ability of the system to fully meet the test requirements of the analog-to-digital converter.

[0017] The test device provided by the present application is modular and open-architected, and is suitable for testing analog-to-digital converter chips of different levels.

[0018] The test device provided by the present application is inexpensive and has strong adaptability. The entire architecture does not change, and only the instruments, meters and test boards need to be replaced to solve all ADC tests.

[0019] The test device provided by the present application is low in cost, and the system can be easily characterized in view of the change of the measured object IP.

[0020] The test device system and the special coding of the DUT provided by the application are convenient for different scene applications.

[0021] The test process of the test device provided by the application is standardized, and the system management and maintenance are facilitated.

[0022] The test device system provided by the application adopts the LABVIEW image language and the GPIB interface, and is convenient for modular debugging and expansion of the instrument system. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The schematic diagram of the universal analog-to-digital converter test device of the application.

[0024] Figure 2 The schematic diagram of the analog-to-digital converter test module in the universal analog-to-digital converter test device of the application.

[0025] Figure 3 The specific implementation block diagram of the analog-to-digital converter test module in the universal analog-to-digital converter test device of the application.

[0026] Figure 4 The hardware configuration diagram of the universal analog-to-digital converter test device of the application.

[0027] ELEMENT NUMBER EXPLANATION

[0028] 1 analog-to-digital converter test module

[0029] 11 signal conditioning unit

[0030] 12 sine wave generator unit

[0031] 13 analog-to-digital converter

[0032] 14 multiplexing unit

[0033] 15 power management unit

[0034] 16 high-speed connection seat unit

[0035] 17 module coding

[0036] 18 standard sample unit

[0037] 2 test interface board

[0038] 3 test mainboard

[0039] 4 external power supply

[0040] 41 instrument external power supply

[0041] 42 precision voltage source

[0042] 5 signal generator

[0043] 6 logic analyzer

[0044] 7 main control computer

[0045] 8 network server

[0046] 9 data processing server

[0047] 10 high-low temperature control box DETAILED DESCRIPTION

[0048] The present application is herein described, by way of example only, with the

[0049] Please refer to the drawings. It is to be understood that the drawings provided in this embodiment are only schematic and are non-limiting regarding the scope of the present application. The drawings are intended to be more conceptual than realistic in order to assist in understanding the present application. Hence, the actual implementation of the present application can vary from the drawings shown, and the variations are intended to be included in the present application. The following legends are used in the accompanying drawings: 1: analog-to-digital converter test module; 2: test interface board; 3: test main board; 4: external power supply; 5: signal generator; 6: logic analyzer; 7: main control computer; 8: network server; 9: data processing server; 10: high-low temperature control box.

[0050] Embodiment 1

[0051] As shown in FIG. 1, the present embodiment provides a general analog-to-digital converter test device, which comprises at least an analog-to-digital converter test module 1, a plurality of test interface boards 2, a test main board 3, an external power supply 4, a signal generator 5, and a logic analyzer 6. The analog-to-digital converter test module 1 is connected to the test interface boards 2 and the test main board 3 in sequence. The external power supply 4, the signal generator 5, and the logic analyzer 6 are connected to each other and to the analog-to-digital converter test module 1. Figure 1 As shown in FIG. 2, the test device further comprises a main control computer 7, which is connected to the test main board 3, the analog-to-digital converter test module 1, the external power supply 4, and the signal generator 5. The main control computer 7 is further connected to a network server 8 and a data processing server 9.

[0052] Figure 1 As shown in FIG. 3, the test device further comprises a high-low temperature control box 10, which is connected to the main control computer 7.

[0053] As shown in FIG. 4, the test device further comprises a high-low temperature control box 10, which is connected to the main control computer 7. Figure 1 ​As shown, the test device further comprises a high-low temperature control box 10 connected with the main control computer 7, the analog-digital converter test module 1 and the test interface board 2. The external power supply 4 is an instrument external power supply 41 and / or a precision voltage source 42.

[0054] The network server and the data processing server can realize all test data processing, analysis and test report generation, and are responsible for external network services. The main control computer 7 realizes communication control through GPIB, Ethernet, USB, serial port and the instrument external power supply 41, the signal generator 5, the precision voltage source 42, the logic analyzer 6, the analog-digital converter test module 1, the test mainboard 3 and the high-low temperature control box 10, and completes the control of the whole system. The software of the main control computer can be controlled by LABVIEW graphical software, and software programming is more convenient.

[0055] Specifically, as shown in the figure, Figure 2 The analog-digital converter test module 1 comprises a signal conditioning unit 11, a sine wave generator unit 12, an analog-digital converter 13, a multiplexing unit 14, a power management unit 15, a high-speed connection seat unit 16, a module code 17 and a standard sample unit 18.

[0056] The signal conditioning unit 11 is connected with the signal generator 5 and the sine wave generator unit 12, and is used for conditioning the signal output by the signal generator 5 or the sine wave generator unit 12, and outputting the signal to the analog-digital converter 1. Further, the embodiment adopts a DDS sine wave generator, which is simple in scheme, small in size and convenient for FPGA system control. The signal conditioning unit 11 can be a low-pass filter, which realizes signal conditioning such as amplification and buffering, anti-aliasing filtering, noise reduction and the like of the sine wave signal or an external arbitrary waveform generator, and the purpose is to realize the best matching with the analog-digital converter test chip. The signal conditioning unit has a positive power supply VDD, a negative power supply VEE and a common-mode power supply VCOM of the amplifier, and these power supplies are configured to be manually adjustable, so as to satisfy the best input signal amplitude matching of the analog-digital converter test chip. In addition to the on-board sine wave generator, when the signal quality cannot satisfy the input signal quality of the analog-digital converter to-be-tested chip, an external precision signal source can be used. This configuration can satisfy the requirements of different IP test precisions.

[0057] The multiplexing unit 14 is connected with the external power supply 4, the signal conditioning unit 11, the analog-digital converter 13, the power management unit 15 and the high-speed connection seat unit 16.

[0058] The power management unit 15 is connected with a 5V power adapter. The power management unit 15 includes power configurations of the analog-to-digital converter 13, power configurations of the signal conditioning unit 11, and power configurations of the sine wave generator unit 12 and the standard sample unit 18. In order to adapt to requirements of different types of analog-to-digital converter chips to be tested, the system reserves multiple groups of power supplies. In order to maximize the performance of the system, linear adjustment power supplies (LDO) with very low power supply noise are basically selected, and the RMS noise is less than 20uV. This is equivalent to 1.8V of the analog-to-digital converter chip 16bit precision. The several groups of power supplies are all set to be adjustable, so as to meet different requirements of the chips to be tested. When the on-board power supply cannot meet the input signal quality of the chip to be tested, an external precision voltage and current source can be used. This configuration method is very flexible and can meet the requirements of different IP test precisions.

[0059] The analog-to-digital converter 13 is connected with a FPGA / logic analyzer interface and a FPGA / third-party evaluation board interface through the high-speed connection seat unit 16. The high-speed connection seat unit 16 is an interface between the analog-to-digital converter test chip and the FPGA (which can be located on the test mainboard). For different processes, the input and output IO voltages can be different. In order to facilitate connection, the IO power supply on the FPGA board is provided by the analog-to-digital converter test module 1. When the IP is different, as long as the VCCIO power supply of the analog-to-digital converter test module 1 is changed, the corresponding power supply of the level converter of the main control board is also set to the correct value, so that the design requirements can be met. The FPGA / logic analyzer interface is used to connect the FPGA or external instruments (such as a logic analyzer) to collect the output data of the analog-to-digital converter. The FPGA / third-party evaluation board interface is used to connect a test interface board, which can integrate a third-party evaluation system (such as TI, ADI). For example, the evaluation system of the same type of product of TI and ADI is connected. The implementation of this scheme is mainly through a FPGA conversion bridge to connect the output signal of the mixed signal IP to the FPGA. The FPGA converts the digital input of the IP according to the interface of the TI or ADI evaluation system. It can appear parallel-to-serial conversion, serial-to-parallel conversion, bit conversion, format conversion, and rate conversion. The purpose is to realize that the correct analog-to-digital converter data is sampled.

[0060] As an example, a bridge resistance is further connected between the high-speed connection seat unit 16 and the analog-to-digital converter 1. When there is an unused IO port of the high-speed connection seat in the analog-to-digital converter test module 1, the bridge resistance should be disconnected to improve the signal integrity of the high-speed connection seat.

[0061] The module code 17 is connected with the analog-digital converter 13 and the high-speed connection seat unit 16. The module code 17 is set for module identification, firmware loading and self-checking during system automatic test, and can use hard code or non-volatile memory to save the characteristic information of the test module. The module code 17 can be located in the analog-digital converter 13 or other positions of the test module. In the analog-digital converter 13, one scheme is to use coded resistors. Different IPs are represented by different coded resistors. For example, the size of the coded resistor value is used for differentiation. Different voltages are obtained by connecting with external resistors in series. The system controller collects the voltage to identify different IPs and load different applications. In addition, it needs to be explained that in order to adapt to the test of all analog-digital converters, the analog-digital converters are classified according to IP rate, which can be divided into low-speed and high-speed. The test schemes of the analog-digital converters of the two speeds are basically the same. From the hardware aspect, only the connection channels of the high-speed interface are different. The low-speed and high-speed are connected through different interfaces. The low-speed uses CMOS level serial and parallel interfaces. The high-speed is connected through LVDS, SSTL and other high-speed electrical serial standards. At present, the super-high-speed ADC IP supports JESD204B / C serial transceiver standard. The JESD204B interface is developed for the growing bandwidth demand of the support of higher-speed converters, and provides higher channel rate (up to 12.5 Gbps per channel). With the help of the compatible open market FPGA solution and the expandable high-performance converter, a large amount of data to be processed can be easily transmitted. Since the test mainboard in the test architecture includes the FPGA part, it is very convenient to build a high-speed ADC IP test platform. The high-speed analog-digital converter and the low-speed analog-digital converter test are basically the same in other test contents except the different interfaces, such as static indicators, dynamic indicators, timing, power consumption test, etc.

[0062] The standard sample unit 18 is a standard part of the analog-digital converter 13 or a similar product part of a third party, and the purpose is to perform performance comparison between the two and for environmental check and verification test comparison.

[0063] The analog-digital converter test module 1 further includes a signal source interface, an instrument interface and a power supply interface. The signal conditioning unit 11 is connected with the signal generator 5 through the signal source interface. The multiplexing unit 14 is connected with the external power supply 4 through the instrument interface. The power management unit 15 is connected with the 5V power adapter through the power supply interface.

[0064] More specifically, as shown in Figure 2 The analog-to-digital converter 13 includes a source input, a reference power supply, an IP power supply, a control input, a digital output, and a coding pin; the source input is connected to the signal conditioning unit 11, the reference power supply and the IP power supply are connected to the multiplexing unit 14, the control input and the digital output unit are connected to the high-speed connector unit 16, and the coding pin is connected to the module coding 17.

[0065] The source input V1+, V1- can also have multiple channels. The input signal can be single-ended or differential input, and the signal amplitude is maximally supported at 5V.

[0066] The analog-to-digital converter 13 can also include an excitation source, which is on-board or externally optional, and can extend the external precision signal source or instrument to maximize the test capability of the system.

[0067] The reference power supply VREF is a precision reference source on board, which can be provided on board. If the on-board cannot meet the requirements, it can be provided by external instruments through the instrument interface.

[0068] The IP power supply is used to provide power for the analog-to-digital converter 13, which can be provided on board. If the on-board cannot meet the requirements, it can be provided by external instruments through the instrument interface.

[0069] The control input DIN, such as the conversion clock or start signal of the analog-to-digital converter and the mode setting signal, is controlled by the digital DIN of the entire test unit, which can be generated by an arbitrary signal generator or an FPGA.

[0070] The digital output DOUT is used for the code value output after the conversion control of the analog-to-digital converter, mainly 8, 10, 12, 14, 16, and 18 bits.

[0071] Analog signals are input at the source input end of the analog-to-digital converter, the reference power supply VREF, and the digital input DIN under the control of the timing sequence to generate the digital code value output corresponding to the analog level. This analog-to-digital converter can be a different voltage and precision chip to be tested, and can have multiple analog input channels. The tested analog-to-digital converter can also be different types of chips, such as Flash analog-to-digital converter, SAR analog-to-digital converter, Pipeline analog-to-digital converter, Sigma Delta analog-to-digital converter, etc.

[0072] In addition, in the embodiment, the signal source interface is externally optional, such as a standard function generator or a standard arbitrary signal generator. The instrument interface is externally optional, and in the IP test of high-precision and wide range, the external supply may be required, so that the test capability of the environment is greatly improved. The power supply interface is an externally optional power supply interface, and if the on-board power supply cannot meet the requirements, an external supply is generally required, so that the test capability of the environment is greatly improved. If boundary performance testing is performed, a wide range of power supply and a wide range of analog input signal are also required. How to maintain the index requirements of the wide range of signals also poses a challenge to the test device. In the test process, in order to meet the test requirements of the analog-to-digital converter IP of different precision, speed and interface, the working conditions of the existing single board cannot completely cover the test requirements of the IP, and in order to cover all the condition tests, the use of such an expandable interface greatly enhances the breadth and depth of the evaluation of the IP.

[0073] The universal analog-to-digital converter test device of the application has the capability of compatible high and low speed hardware interface, the interface signal level is automatically connected with the analog-to-digital converter, and the high speed connection seat is shared with the analog-to-digital converter. The interface voltages of different processes are also different. Due to the difference in processes, the core and IO voltage of the chip are different, from 14nm to 55nm, and the voltage between 0.7V and 5.5V power supply can be supported. In this way, the IO voltage of the IP of different processes is very easy to match, and it can also be suitable for the international standard high speed ADC interface JESD204B / C circuit. Different speed interfaces use different hardware connection pins. The LVDS high speed signal can be connected to the high speed analog-to-digital converter test board, the single-ended input and output can be connected to the low speed analog-to-digital converter test board, and the VCCIO is the power signal for connecting the main board level converter and the analog-to-digital converter IO level. The power signal is the power signal provided to the analog-to-digital converter. In the whole system, the conversion control and conversion output of the analog-to-digital converter need to be connected with the data acquisition and control unit. These signals are actually provided to the FPGA after being converted to the appropriate voltage by the level converter of the main control board. In order to facilitate, the power of the level converter on the main control board is not fixed, but matched with the VCCIO of the analog-to-digital converter module. In this way, no matter how the IO voltage of the unit under test is, the input and output of the main control board can be guaranteed to be the same as the level of the analog-to-digital converter, so that the problem of level matching is well solved.

[0074] The test device of the application can be modularly and independently operated, has strong expandability, and can realize different functions only by simple building block form. Before establishing the entire system, each component can be operated individually, and can be spliced when needed. The more the spliced module components, the stronger the realized functions. In order to adapt to various different processes, different types, and different working conditions of the analog-to-digital converter as much as possible, and to fully utilize the resources of advanced instruments and equipment in the existing laboratory, a complex and comprehensive system is not designed. The purpose is to simplify the analog-to-digital converter module design to improve the system performance of the analog-to-digital converter, integrate other resources, and quickly establish the ability of the system. The functions that can be realized by several typical module combinations are as follows:

[0075] Scheme one: main control board (test main board) + analog-to-digital converter test module + 5V power adapter, which can realize functions: IP complete function test, performance test (may be partial performance), cannot realize power consumption test, can be used as IP demonstration, prototype system verification.

[0076] Scheme two: test main board + analog-to-digital converter test module + signal source (optional) + external power supply (optional), which can realize functions: IP complete function test, performance test, DC test.

[0077] Scheme three: test main board + analog-to-digital converter test module + 5V power adapter + third-party IP evaluation board (test interface board), which can realize functions: IP complete function test, performance test (may be partial performance), cannot realize power consumption test, can be used as IP demonstration.

[0078] Scheme four: test main board + analog-to-digital converter test module + signal source (optional) + external power supply (optional) + third-party IP evaluation board (test interface board), which can realize functions: IP complete function test, performance test, DC test, test comparison.

[0079] Scheme five: analog-to-digital converter test module + 5V power supply + external signal source + pattern generator + logic analyzer + data analysis processing software, which can manually complete the test function of the analog-to-digital converter, and test comparison.

[0080] In all the schemes, the performance of the standard sample unit can be evaluated, the test environment can be verified to meet the design requirements, the performance comparison between the standard sample unit can be verified, and the differences between chips can be further analyzed and studied. The automatic test is realized through LABVIEW or PC software, and the test project process is basically the same. The general program flowchart of the analog-to-digital converter test device is as follows:

[0081] Firstly, the system determines the peripheral power supply of the test instrument, the state of the instrument, and completes the preparation work of the test environment according to the test project;

[0082] Then, the test item sends test commands to the lower computer through the host computer, and the system main control processor or FPGA receives the test commands of the host computer, analyzes the commands and generates corresponding control signals to the analog-to-digital converter test module;

[0083] Then, the analog-to-digital converter test module generates corresponding actions, such as a sine wave generator, a relay response, etc., and the unit under test generates an output response according to the input excitation;

[0084] Finally, the test control mainboard collects data and calculates the results and saves them, or transmits the original data to the host computer for analysis and processing, and saves the results or original data.

[0085] Embodiment 2

[0086] This embodiment provides a general analog-to-digital converter test device, as shown in Figure 3 The difference between this device and embodiment one is that the types and unit circuits of each unit in the analog-to-digital converter test module 1 are further listed.

[0087] As shown in Figure 3 The analog-to-digital converter test module 1 includes a signal conditioning unit 11, a sine wave generator unit 12, an analog-to-digital converter 13, a multiplexing unit 14, a power management unit 15, a high-speed connection seat unit 16, a module code 17, and a standard sample unit 18.

[0088] The signal conditioning unit 11 is connected with the signal generator 5 and the sine wave generator unit 12, used for conditioning the signal output by the signal generator 5 or the sine wave generator unit 12, and outputting the signal to the analog-to-digital converter 13. This system scheme adopts a DDS sine wave generator, which is simple and easy to control. For example, the ADI company in the United States, the high-integration frequency synthesizer AD9850 contains a programmable DDS system and a high-speed comparator, which can realize full-digital programmable control of frequency synthesis. The core of the programmable DDS system is a phase accumulator, which is composed of an adder and an N-bit phase register, N is generally 24-32, and the lookup table maps the phase information of the input address into a sine wave amplitude signal, and then drives the DAC to output the mode quantity.

[0089] The signal conditioning unit 11 can realize the conditioning of sine wave signal or external arbitrary waveform generator, such as amplification buffer, anti-aliasing filter, noise reduction and other signal conditioning, the purpose is to realize the best matching with the analog-to-digital converter test chip, the signal conditioning unit has independent buffer (BUFFER) positive power supply VDD, negative power supply VEE, the common mode power supply VCOM of the amplifier, these power supplies are not completely fixed, but configured to be manually adjustable, to meet the best input signal amplitude matching of the test chip, in addition to the on-board sine wave generator, the signal conditioning unit can also use external precision signal source, the differential amplifier of the signal conditioning uses TI THS4551 product, this configuration can meet the IP test precision requirement, low noise, precision, 150MHz, full differential amplifier, differential input voltage noise: 3.3nV / √Hz, 18-bit settling time: 4V step, <500ns, suitable for 16-bit to 20-bit differential high-speed successive approximation register (SAR) driver, THS4551 full differential amplifier can provide a simple interface between single-ended and differential output, so as to meet the needs of various high-precision analog-to-digital converters (ADC), this device has excellent DC precision, low noise and robust capacitive load driving capability, and is very suitable for data acquisition systems with high precision requirements; at the same time, under the cooperation of the amplifier and the ADC, excellent signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) can be obtained.

[0090] The multiplexing unit 14 is connected with the external power supply 4, the signal conditioning unit 11, the analog-to-digital converter 13, the power management unit 15, and the high-speed connection seat unit 16.

[0091] The power management unit 15 is connected with the 5V power adapter. The power management unit 15 includes the power supply configuration of the analog-to-digital converter 13, the power supply configuration of the signal conditioning unit 11, and the power supply configuration of the sine wave generator unit 12 and the standard sample unit 18. In order to meet the requirements of different types of analog-to-digital converter chips to be tested, the system reserves multiple power supplies. In order to meet the requirements of 16-bit high-precision, TI TLV75801PDBVR LDO is selected, which can adjust the output from 0.55V to 5.5V. These groups of power supplies are adjustable to meet the requirements of different chips to be tested. When the power supply cannot meet the input signal quality of the chip to be tested, an external precision voltage and current source can be used. This configuration is very flexible and can meet the requirements of different IP test precision.

[0092] The analog-to-digital converter 13 is connected with the FPGA / logic analyzer interface and the FPGA / third-party evaluation board interface through the high-speed connector unit 16. The high-speed connector unit 16 selects the SAMTEC QTH / QSH series 180PIN connector, which is reliable in performance and has the model QTH-090-07-F-D-A. The high-speed connector unit is an interface between the analog-to-digital converter test chip and the FPGA (which can be located on the test mainboard). For different processes, the input and output IO voltages can be different. In order to facilitate connection, the IO power supply on the FPGA board is provided by the analog-to-digital converter test module. When the IP is different, as long as the VCCIO power supply of the analog-to-digital converter test module is changed, the corresponding power supply of the level converter of the host board is also set to the correct value, so that the design requirements can be met.

[0093] The FPGA / logic analyzer interface is used to connect the FPGA or external instruments (such as the logic analyzer TEKTLA6103) to collect the output data of the analog-to-digital converter. The logic analyzer can only collect the output data of the analog-to-digital converter, and cannot calculate the result. The FPGA can directly complete data collection and operation. The FPGA / third-party evaluation board interface is used to connect the test interface board, which can integrate the third-party evaluation system TI ADS7057EVM, which is a 14bit SAR 2M sampling rate ADC. The implementation of this scheme mainly provides the bridging function between the ADC IP and TI ADS7057EVM through a FPGA conversion logic. The output signal of the analog-to-digital converter IP is connected to the FPGA, and the FPGA converts the digital input of the analog-to-digital converter IP according to the interface requirements of TI ADS7057EVM, so that the correct analog-to-digital converter data is sampled.

[0094] The bridge resistor is further connected between the high-speed connector unit 16 and the analog-to-digital converter 13.

[0095] The module code 17 is connected with the analog-to-digital converter 13 and the high-speed connector unit 16. The module code 17 can be located in the analog-to-digital converter 13 or other positions of the test module. In the analog-to-digital converter 13, one scheme is to use resistors R_DIE of different sizes to distinguish, which are connected in series with external resistors RUP to obtain different voltage divisions. The system controller collects the voltage division to identify different IPs and load different applications. R_DIE can be implemented by using active or passive devices.

[0096] The standard sample unit 18 is a standard part of the analog-to-digital converter 13 or a similar product of a third party. The purpose is to compare the performance between the two and to test the environmental inspection verification.

[0097] More specifically, as Figure 3As shown, the analog-to-digital converter 13 includes a source input, a reference power supply, an IP power supply, a control input, and a digital output; the source input is connected to the signal conditioning unit 11, the reference power supply and the IP power supply are connected to the multiplexing unit 14, and the control input and the digital output unit are connected to the high-speed connector unit 16.

[0098] The signal selection of the source input V1+ and V1- is obtained after conditioning by TEK AFG3102C 14-bit precision or ADI AD5791 20-bit DAC evaluation board.

[0099] The reference power supply VREF is a board-mounted precision reference source selected from TI REF1925AIDDCR. If the board-mounted one cannot meet the requirements, it can be provided by an external instrument, such as GS200.

[0100] The IP power supply (VCC) is used to provide power supply for the analog-to-digital converter, which can be provided by a board-mounted TI TLV75801PDBVR adjustable LDO with a range of 0.55V-5.5V. If the board-mounted one cannot meet the requirements, it can be provided by an external instrument, such as Keysight N6075B / C.

[0101] The control input DIN, such as the conversion clock or start signal of the analog-to-digital converter and the mode setting signal, is controlled by the digital DIN throughout the test unit. In the SAR analog-to-digital converter, DIN includes a clock signal SCLK, a start control signal STC, and a mode setting signal Mode setting. The generation method is various, and in the present system, it is generated by FPGA programmable logic, and the FPGA is selected as Xilinx Spartan XC6SLX16.

[0102] The digital output DOUT is used for the code value output after the conversion control of the analog-to-digital converter, and the signal includes an end-of-conversion signal ETC, a digital output signal Dout[N:0], and N values mainly have 8, 10, 12, 14, 16, and 18 bits. In the present embodiment, it is generated by FPGA programmable logic, and the FPGA is selected as Xilinx Spartan XC6SLX16.

[0103] An analog signal is input at the source input end of the analog-to-digital converter, the reference power supply VREF, and the digital input end DIN under the control of the timing sequence to generate the digital code value output corresponding to the analog level of the conversion. Such analog-to-digital converters can be different voltage and different precision chips to be tested, and there can be multiple analog input channels. The tested analog-to-digital converter can also be different types of chips, such as Flash analog-to-digital converters, SAR analog-to-digital converters, Pipeline analog-to-digital converters, Sigma Delta analog-to-digital converters, etc.

[0104] In addition, in the embodiment, the signal source interface is optional, and the instrument interface and the external power supply interface are mandatory. If boundary performance testing is performed, a wide range of power supplies and wide range analog input signals are also needed. How to maintain the index requirements of the wide range of signals also poses a challenge to the test device. In the testing process, in order to meet the testing requirements of analog-to-digital converter IPs of different precisions, speeds and interfaces, the working conditions of the existing single board cannot completely cover the testing requirements of the IPs. In order to cover all the condition tests, the use of such an extensible interface greatly enhances the breadth and depth of the evaluation of the IPs.

[0105] The universal analog-to-digital converter testing device of the application has the capability of compatible high and low speed hardware interface, the interface signal level is automatically connected with the analog-to-digital converter, and the high speed connection seat is shared with the analog-to-digital converter. The interface voltages of different processes are also different. Due to the difference in processes, the core and IO voltages of the chip are different, from 14nm to 55nm, and the supported voltage is between 0.7V and 5.5V power supply. In this way, the IO voltage of the IP of different processes is very easy to match, and it can also be suitable for the international standard high speed ADC interface JESD204B / C circuit. Different speed interfaces use different hardware connection pins. The LVDS high speed signal can be connected to the high speed analog-to-digital converter test board, the single-ended input and output can be connected to the low speed analog-to-digital converter test board, and the VCCIO is the power signal for connecting the main board level converter and the analog-to-digital converter IO level. The power signal is the power signal provided to the analog-to-digital converter. In the whole system, the conversion control and conversion output of the analog-to-digital converter need to be connected with the data acquisition and control unit. These signals are actually provided to the FPGA after being converted to the appropriate voltage by the level converter of the main control board. In order to facilitate, the power of the level converter on the main control board is not fixed, but matched with the VCCIO of the analog-to-digital converter module. In this way, no matter how the IO voltage of the unit under test is, the input and output of the main control board can be guaranteed to be the same as the level of the analog-to-digital converter. In this way, the problem of level matching is well solved.

[0106] The testing device of the embodiment can work independently and has strong scalability. Only simple building block form is needed to realize different functions. Before the whole system is established, each component can be operated independently and can be spliced when needed. The more modules that are spliced, the stronger the function that is realized. In order to adapt to various analog-to-digital converters of different processes, different types and different working conditions as much as possible, and to fully utilize the advanced instrument and equipment resources of the existing laboratory, a complex and comprehensive system is not designed. The purpose is to simplify the design of the analog-to-digital converter module to improve the system performance of the analog-to-digital converter, integrate other resources and quickly establish the ability of the system. The functions that can be realized by the typical combination of several modules are as follows:

[0107] Solution one: main control board (test mainboard) + analog-digital converter test module + 5V power adapter, which can realize the functions of IP complete function test, performance test (may be partial performance), cannot realize power consumption test, can be used as IP demonstration, and prototype system verification.

[0108] Solution two: main control board + analog-digital converter test module + signal source (AFG3102 is optional) + external power supply (GS200 is optional), which can realize the functions of IP complete function test, performance test, and DC test.

[0109] Solution three: main control board + analog-digital converter test module + 5V power adapter + third-party IP evaluation board (ADS9100EVM), which can realize the functions of IP complete function test, performance test (may be partial performance), cannot realize power consumption test, and can be used as IP demonstration.

[0110] Solution four: main control board + analog-digital converter test module + signal source (AFG3102 is optional) + external power supply (GS200 is optional) + third-party IP evaluation board (ADS9100EVM), which can realize the functions of IP complete function test, performance test, DC test, and test comparison.

[0111] Solution five: analog-digital converter test module + 5V power supply + external signal source + control signal generation AWG5014C + logic analyzer + data analysis processing software, which can manually realize the test function of analog-digital converter.

[0112] As Figure 4 shown is a hardware configuration diagram of the analog-digital converter module. The system HSTC high-speed interface (high-speed connection seat unit) is connected to the stacked PCB, and the output signals of the interface are all connected with series resistors and close to the socket (SOCKET) side. When not in use, in order to improve the performance of the test system, it is necessary to weld and remove.

[0113] As Figure 4 shown, the flow scheme of this embodiment is as follows:

[0114] Solution one, analog-digital converter ADC IP + resistance + FPGA_HSTC + FPGA + PC (computer), which can realize analog-digital converter ADC test.

[0115] Solution two, analog-digital converter ADC IP + resistance + FPGA_HSTC + FPGA + resistance + J1 / J2 to the appropriate position + TIEVM Capature Board Socket + TI EVM + PC, which can realize TI system evaluation.

[0116] In all the schemes, the standard sample can be subjected to performance evaluation, the test environment can be verified to meet the design requirements, the performance comparison between the standard sample and the sample can be verified, and further comparison analysis can be performed. The automatic test is realized by LABVIEW or PC software, and the processes of all test items are basically the same. The following is an example of the test flow of the dynamic performance index of the analog-to-digital converter, and the test flows of other items are the same.

[0117] Firstly, the system determines the peripheral power supply of the test instrument, the state of the instrument and completes the preparation work of the test environment according to the test item;

[0118] Then, the test module receives the test command of the host computer;

[0119] Then, the signal excitation such as the sine wave generation and the working mode setting of the analog-to-digital converter IP are realized.

[0120] Then, the FPGA of the main board collects the digital code after the analog-to-digital conversion of the analog-to-digital converter IP.

[0121] Then, the host board or PC completes the continuous collection of data points, and calculates the test index by FFT.

[0122] Finally, the test results and the original data are saved,

[0123] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A universal analog-to-digital converter test apparatus, characterized by, The test device at least comprises: an analog-to-digital converter test module, a plurality of test interface boards, a test mainboard, an external power supply, a signal generator, and a logic analyzer, the analog-to-digital converter test module is connected to the test interface boards and the test mainboard in sequence, the external power supply, the signal generator, and the logic analyzer are connected to each other and are connected to the analog-to-digital converter test module; The analog-to-digital converter test module comprises a signal conditioning unit, a sine wave generator unit, an analog-to-digital converter, a multiplexing unit, a power management unit, a high-speed connection seat unit, a module code and a standard sample unit; The signal conditioning unit is connected to the signal generator and the sine wave generator unit, and is used for conditioning the signal output by the signal generator or the sine wave generator unit, and outputting the signal to the analog-to-digital converter; The multiplexing unit is connected to the external power supply, the signal conditioning unit, the analog-to-digital converter, the power management unit, and the high-speed connection seat unit; The power management unit is connected to a 5V power adapter; The analog-to-digital converter is connected to an FPGA / logic analyzer interface and an FPGA / third-party evaluation board interface through the high-speed connection seat unit; The module code is connected to the analog-to-digital converter and the high-speed connection seat unit.

2. The universal analog-to-digital converter test apparatus of claim 1, wherein: A bridge resistor is further connected between the high-speed connection seat unit and the analog-to-digital converter.

3. The universal analog-to-digital converter test apparatus of claim 1, wherein: The analog-to-digital converter comprises a signal source input, a reference power supply, an IP power supply, a control input, a digital output, and a code pin; the signal source input is connected to the signal conditioning unit, the reference power supply and the IP power supply are connected to the multiplexing unit, the control input and the digital output unit are connected to the high-speed connection seat unit, and the code pin is connected to the module code.

4. The universal analog-to-digital converter test apparatus of claim 1, wherein: The analog-to-digital converter is one of a Flash analog-to-digital converter, a SAR analog-to-digital converter, a Pipeline analog-to-digital converter, and a Sigma Delta analog-to-digital converter.

5. The universal analog-to-digital converter testing apparatus of claim 1, wherein: The external power supply is an instrument external power supply and / or a precision voltage source.

6. The universal analog-to-digital converter test apparatus of claim 1, wherein: The test device further comprises a main control computer, the main control computer is connected to the test mainboard, the analog-to-digital converter test module, the external power supply, and the signal generator, and the main control computer is further connected to a network server and a data processing server.

7. A universal analog-to-digital converter test apparatus according to claim 6, wherein: The test device further comprises a high-low temperature control box, the high-low temperature control box is connected to the main control computer, the analog-to-digital converter test module, and the test interface boards.

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